DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Seiji (JP 2002-255697 A) in view of Kim (KR 100945668 B1) and Eichler et al. (US 2022/0106702 A1).
Regarding Claim 1, Seiji teaches a n-type GaAs wafer (Paragraph 0012) having 1.0×10 18 to 1.0×1019/cm3 of Si atoms, 1.0×1018 to 1.0×1019/cm3 of B atoms and 1.0×1018 to 2.0×1019/cm3 of In atoms (Paragraph 0009-0011). These ranges overlap the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP §2144.05). Seiji does not specifically teach the carrier concentration range of the wafer.
Kim teaches a Si and N doped GaAs wafer, where the carrier concentration ranges from 1.0×1015 to 1.0×1018 cm−3. (Page 2). These ranges overlap the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP §2144.05). Kim teaches this range avoid Si precipitation and ensures single crystal growth. (Page 2). Thus, it would have been obvious to one with ordinary skill in the art to set the carrier concentration of wafter of Seiji to the claimed range.
Seiji teaches the average dislocation density should be 50 cm−2 or less. (Paragraph 0008). Seiji does not specifically teach a proportion of the area of a region with zero dislocation density is 91% or more.
Eichler teaches a GaAs wafer (Abstract; Claim 20-24 of Eichler). Eichler teaches the area of the crystal and resulting wafer should have 95% or more of area free from dislocations. (Paragraph 0037). Eichler teaches this will improve the yield of forming components, which improves economic efficiency of the wafer. (Paragraph 0038). Eichler does not specifically teach the claimed method of measuring a proportion of the area of a region with zero dislocation density. However, it would be reasonable to one with ordinary skill in the art the teachings of Eichler would direct one of ordinary skill in the art to overlap the range of the proportion of the area of a region with zero dislocation density of Seiji measured under the claimed method to the claimed range, as higher proportion of area of a region with zero dislocation density improves the economic efficiency of resulting wafers.
Regarding Claim 2, Seiji teaches the average dislocation density should be 50 cm−2 or less. (Paragraph 0008). These ranges overlap the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP §2144.05). Seiji does not specifically teach the claimed method of measuring average dislocation density. However, it would be reasonable to one with ordinary skill in the art the teachings of Seiji and Eichler to reduce the dislocation density under any method to improve yield of the wafer when forming components, as discussed above.
Regarding Claim 3, Seiji teaches forming 3-inch wafers (Paragraph 0025).
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Seiji in view of Kim, Eichler, Freiberger (NPL) and UNSW (NPL).
Regarding Claim 4-6, Seiji teaches a n-type GaAs wafer (Paragraph 0012) having 1.0×10 18 to 1.0×1019/cm3 of Si atoms, 1.0×1018 to 1.0×1019/cm3 of B atoms and 1.0×1018 to 2.0×1019/cm3 of In atoms (Paragraph 0009-0011). These ranges overlap the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP §2144.05). Seiji does not specifically teach the carrier concentration range of the wafer.
Kim teaches a Si and N doped GaAs wafer, where the carrier concentration ranges from 1.0×1015 to 1.0×1018 cm−3. (Page 2). These ranges overlap the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP §2144.05). Kim teaches this range avoid Si precipitation and ensures single crystal growth. (Page 2). Thus, it would have been obvious to one with ordinary skill in the art to set the carrier concentration of wafter of Seiji to the claimed range.
Seiji does not specifically teach a proportion of the area of a region with zero dislocation density is 91% or more.
Eichler teaches a GaAs wafer (Abstract; Claim 20-24 of Eichler). Eichler teaches the area of the crystal and resulting wafer should have 95% or more of area free from dislocations. (Paragraph 0037). Eichler teaches this will improve the yield of forming components, which improves economic efficiency of the wafer. (Paragraph 0038). Eichler does not specifically teach the claimed method of measuring a proportion of the area of a region with zero dislocation density. However, it would be reasonable to one with ordinary skill in the art the teachings of Eichler would direct one of ordinary skill in the art to overlap the range of the proportion of the area of a region with zero dislocation density of Seiji measured under the claimed method to the claimed range, as higher proportion of area of a region with zero dislocation density improves the economic efficiency of resulting wafers.
Seiji teaches the average dislocation density should be 50 cm−2 or less. (Paragraph 0008). Seiji does not specifically teach the claimed method of measuring average dislocation density. However, it would be reasonable to one with ordinary skill in the art the teachings of Seiji and Eichler to reduce the dislocation density under any method to improve yield of the wafer when forming components, as discussed above.
Seiji, Kim and Eichler do not specifically tach the GaAs wafers are obtained from center portion of a straight body portion of an identical GaAs ingot.
Freiberger teaches GaAs wafers are formed by creating a GaAs crystal ingot and cutting wafers from the ingot, where cuts are made through the center portion of a straight body portion of one identical ingot. USNW teaches a plurality of wafers are formed by cutting multiple wafers from the center portion of a straight body portion of one identical ingot, which allows the plurality of wafers to be used for a commercial purpose. Thus, it would have been obvious to one with ordinary skill in the art to form a plurality of wafers from a center portion of the straight body portion of a GaAs ingot as taught by Freiberger and UNSW in order to yield commercially plurality of wafers.
Regarding Claim 7, the limitation that the plurality of the GaAs wafers is half or more of the total wafers from the straight body portion of the identical GaAs ingot is product-by-process limitation, as it limits the number of wafers extract from ingot. This does not seem to place a structural limit on the plurality of GaAs wafers themselves; thus, the numbers of wafers that are formed or not formed form an ingot does not place a structural limitation on the resulting wafer group. In addition, Freiberger and UNSW teaches slicing the entire ingot to form wafers.
Regarding Claim 8, UNSW teaches GaAs wafers are cut from the straight body portion of an identical ingot from tail side to a seed side, as those are portions of an ingot formed from CZ method. (Paragraph 0029).
Claim 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kretzer (JP 6018382 B2) in view of Itani et al. (US 2004/0187768 A1) and Eichler.
Regarding Claim 1, Kretzer teaches a n-type GaAs wafer (Claims 1-4 of Kretzer) doped with Si and B, along with transition metals (Paragraph 0021-022). Kretzer teaches the carrier concentration ranges from 1.0×1016 to 1.0×1018 cm−3. (Paragraph 0013). These ranges overlap the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP §2144.05).
Kretzer does not teach the dopant ranges of Si, In or B.
Itani teaches a GaAs wafer (Abstract; Paragraph 0040) have 1.0×10 17 to 5.0×1019/cm3 of Si atoms, 1.0×1017 to 5.0×1019/cm3 of B atoms, and 1.0×1017 to 5.0×1019/cm3 of In atoms. Paragraph (0012-0013). These ranges overlap the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP §2144.05). Itani teaches reduces dislocation density to below 100 cm-2. (Paragraph 0025-0026) Thus, it would have been obvious to one with ordinary skill in the art to use the dopant concentrations taught by Itani in Kretzer for lower dislocation density.
Kretzer does not specifically teach a proportion of the area of a region with zero dislocation density is 91% or more.
Eichler teaches a GaAs wafer (Abstract; Claim 20-24 of Eichler). Eichler teaches the area of the crystal and resulting wafer should have 95% or more of area free from dislocations. (Paragraph 0037). Eichler teaches this will improve the yield of forming components, which improves economic efficiency of the wafer. (Paragraph 0038). Eichler does not specifically teach the claimed method of measuring a proportion of the area of a region with zero dislocation density. However, it would be reasonable to one with ordinary skill in the art the teachings of Eichler would direct one of ordinary skill in the art to overlap the range of the proportion of the area of a region with zero dislocation density of Kretzer measured under the claimed method to the claimed range, as higher proportion of area of a region with zero dislocation density improves the economic efficiency of resulting wafers.
Regarding Claim 2, Itani teaches the average dislocation density should be 100 cm−2 or less. (Abstract; Claim 1 of Itani). Itani teaches lower average dislocation density leads to be more reliability when the wafer is processed for use. (Paragraph 0040). Itani does not specifically teach the claimed method of measuring average dislocation density. However, it would be reasonable to one with ordinary skill in the art the teachings of Itani would direct one of ordinary skill in the art to overlap the claimed average dislocation density measured under the claimed method, as Itani teaches lower average dislocation density improves the reliability when the wafer is used.
Regarding Claim 3, Itani teaches 3-inch wafers re suitable for further processing. (Paragraph 0040). Thus, it would have been obvious to one with ordinary skill in the art to make the wafer to Kretzer to the same size range from further processing.
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kretzer, in view of Itani, Eichler, Freiberger (NPL) and UNSW (NPL).
Regarding Claims 4 and 6, Kretzer teaches a n-type GaAs wafer (Claims 1-4 of Kretzer) doped with Si and B, along with transition metals (Paragraph 0021-022). Kretzer teaches the carrier concentration ranges from 1.0×1016 to 1.0×1018 cm−3. (Paragraph 0013). These ranges overlap the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP §2144.05).
Kretzer does not teach the dopant ranges of Si, In or B.
Itani teaches a GaAs wafer (Abstract; Paragraph 0040) have 1.0×10 17 to 5.0×1019/cm3 of Si atoms, 1.0×1017 to 5.0×1019/cm3 of B atoms, and 1.0×1017 to 5.0×1019/cm3 of In atoms. Paragraph (0012-0013). These ranges overlap the claimed range. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. (MPEP §2144.05). Itani teaches reduces dislocation density to below 100 cm-2. (Paragraph 0025-0026) Thus, it would have been obvious to one with ordinary skill in the art to use the dopant concentrations taught by Itani in Kretzer for lower dislocation density.
Kretzer does not specifically teach a proportion of the area of a region with zero dislocation density is 91% or more.
Eichler teaches a GaAs wafer (Abstract; Claim 20-24 of Eichler). Eichler teaches the area of the crystal and resulting wafer should have 95% or more of area free from dislocations. (Paragraph 0037). Eichler teaches this will improve the yield of forming components, which improves economic efficiency of the wafer. (Paragraph 0038). Eichler does not specifically teach the claimed method of measuring a proportion of the area of a region with zero dislocation density. However, it would be reasonable to one with ordinary skill in the art the teachings of Eichler would direct one of ordinary skill in the art to overlap the range of the proportion of the area of a region with zero dislocation density of Kretzer measured under the claimed method to the claimed range, as higher proportion of area of a region with zero dislocation density improves the economic efficiency of resulting wafers.
Krezter, Itani and Eichler do not specifically tach the GaAs wafers are obtained from center portion of a straight body portion of an identical GaAs ingot.
Freiberger teaches GaAs wafers are formed by creating a GaAs crystal ingot and cutting wafers from the ingot, where cuts are made through the center portion of a straight body portion of one identical ingot. USNW teaches a plurality of wafers are formed by cutting multiple wafers from the center portion of a straight body portion of one identical ingot, which allows the plurality of wafers to be used for a commercial purpose. Thus, it would have been obvious to one with ordinary skill in the art to form a plurality of wafers from a center portion of the straight body portion of a GaAs ingot as taught by Freiberger and UNSW in order to yield commercially plurality of wafers.
Regarding Claim 5, Itani teaches the average dislocation density should be 100 cm−2 or less. (Abstract; Claim 1 of Itani). Itani teaches lower average dislocation density leads to be more reliability when the wafer is processed for use. (Paragraph 0040). Itani does not specifically teach the claimed method of measuring average dislocation density. However, it would be reasonable to one with ordinary skill in the art the teachings of Itani would direct one of ordinary skill in the art to overlap the claimed average dislocation density measured under the claimed method, as Itani teaches lower average dislocation density improves the reliability when the wafer is used.
Regarding Claim 7, the limitation that the plurality of the GaAs wafers is half or more of the total wafers from the straight body portion of the identical GaAs ingot is product-by-process limitation, as it limits the number of wafers extract from ingot. This does not seem to place a structural limit on the plurality of GaAs wafers themselves; thus, the numbers of wafers that are formed or not formed form an ingot does not place a structural limitation on the resulting wafer group. In addition, Freiberger and UNSW teaches slicing the entire ingot to form wafers.
Regarding Claim 8, UNSW teaches GaAs wafers are cut from the straight body portion of an identical ingot from tail side to a seed side, as those are portions of an ingot formed from CZ method. (Paragraph 0029).
Response to Arguments
Applicant’s arguments have been fully considered.
New grounds of rejection have been made in view of Applicant’s amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ZHANG whose telephone number is (571)270-0358. The examiner can normally be reached Monday through Friday: 9:30am-3:30pm, 8:30PM-10:30PM.
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/Michael Zhang/Primary Examiner, Art Unit 1781
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