Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In reply to the Non-Final Office Action mailed on 3/4/2026, the applicant has filed a response on 5/15/2026 amending claims 1, 8, 13 and 20. Claims 10-12 have been cancelled. Claim 21 has been added. Claims 1-9 and 13-21 are pending in this application.
Previous objection to the drawing is withdrawn in view of applicant’s amendments filed on 5/15/2026.
Previous claim objections are withdrawn in view of applicant’s amendments filed on 5/15/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhou et al. (CN 115798387 A), machine translation provided by the examiner and referenced throughout the rejection.
Regarding claim 1, Zhou discloses a gate driving circuit (see gate driving unit 10 in Fig. 1), comprising:
an inverting module, electrically connected to a first voltage terminal (regarding Fig. 1, see inverter 17 connected to low potential signal terminals VGL1/VGL2/VGL3, taken as the claimed first voltage terminal), a first node (see node Q[n] in Fig. 1), a second node (see node at a gate of transistor T53 in Fig. 1), and a third node (see node QB[n] in Fig. 1), configured to control a signal transmission between the first voltage terminal and the third node in response to a potential of the first node (inverter 17 is configured to control a signal transmission between e.g. terminal VGL1 and the node at the gate of transistor T53 in response to a potential of Q[n] applied to a gate of transistor T54, as shown in Fig. 1), and configured to control a signal transmission between a low-frequency clock signal terminal and the third node in response to a potential of the second node (inverter 17 is configured to control a signal transmission between a low frequency clock signal terminal LC and node QB[n] in response to a potential of the node at the gate of transistor T53, as shown in Fig. 1);
a pull-down holding module, electrically connected to the first voltage terminal, the first node, and the third node (see pull-down maintaining unit 14, connected e.g. to terminal VGL1, node Q[n] and node QB[n], as shown in Fig. 1), and configured to control a signal transmission between the first voltage terminal and the first node in response to a potential of the third node (pull-down maintaining unit 14 is configured to control a signal transmission between terminal VGL1 and node Q[n] in response to a potential of node QB[n] at gates of transistor T43A and T44A, as shown in Fig. 1); and
a pull-up control module, electrically connected to the first voltage terminal, the first node, and the second node (see pull-up control unit comprising transistors T11, T12, T52 and T56, connected to e.g. terminals VGL1/VGL2, node Q[n] and the node at the gate of transistor T53, as shown in Fig. 1), configured to pull up the potential of the first node in response to a pull-up control signal (regarding Figs. 1-2, when “terminal Cout-PU input high potential, the ninth transistor T11 and the tenth transistor T12 turn on” and “node Q[n] is pulled up to the high potential”; page 13, 5th paragraph), and configured to control a signal transmission between the first voltage terminal and the second node in response to the pull-up control signal (regarding Figs. 1-2, when node Q[n] is pulled up to the high potential and applied to a gate of transistor T52, a signal transmission between e.g. terminal VGL2 and the node at the gate of transistor T53 is controlled, in response to the signal at terminal Cout-PU (claimed pull-up control signal)),
wherein the pull-up control module is directly connected to the first node and the second node respectively (see in Fig. 1 that the pull-up control unit comprises transistors T11, T12, T52 and T56, that transistor T12 is directly connected to node Q[n] (claimed first node), and that transistor T52 is directly connected to the node at the gate of transistor T53 (claimed second node)), such that the pull-up control module is configured to parallelly pull up the potential of the first node and control the signal transmission between the first voltage terminal and the second node in response to the pull-up control signal (see page 24; based on the broadest reasonable interpretation of the claimed limitations, “as shown in fig. 1 and fig. 2, in the first stage T1, the second stage signal terminal Cout-PU inputs a high potential, the ninth transistor T11 and the tenth transistor T12 are turned on, the first node Q [N] is pulled up to the high potential”, and at the same time, in response to this, transistor T52 is turned on and the low potential signal VGL2 is applied to the gate of transistor T53, as claimed);
wherein when the pull-up control module is configured to electrically connect the first voltage terminal and the second node in response to the pull-up control signal, the inverting module is configured to disconnect an electrical connection between the low-frequency clock signal terminal and the third node in response to the potential of the second node (regarding Figs. 1-2, when terminal VGL2 and the node at the gate of transistor T53 are connected in response to the signal at terminal Cout-PU, inverter 17 is configured to disconnect the low frequency clock signal terminal LC and node QB[n], by turning off transistor T53 in response to the low potential signal VGL2 applied to the gate of transistor T53 (the claimed second node) through transistor T52), the inverting module is also configured to control an electrical connection between the first voltage terminal and the third node in response to the potential of the first node (regarding Figs. 1-2, inverter 17 is also configured to control a connection between e.g. terminal VGL1 and node QB[n] in response to the potential of node Q[n] applied to the gate of transistor T54), and the pull-down holding module is configured to disconnect an electrical connection between the first voltage terminal and the first node in response to the potential of the third node (regarding Figs. 1-2, the pull-down maintaining unit 14 is configured to disconnect e.g. terminal VGL1 and Q[n] in response to the low potential signal VGL1 at QB[n] applied to the gates of transistors T43A and T44A).
Regarding claim 2, Zhou discloses all the claim limitations as applied above (see claim 1). In addition, Zhou discloses the pull-up control module comprises:
a first control unit, comprising a first transistor, wherein a control terminal of the first transistor is configured to receive the pull-up control signal, an input terminal of the first transistor is electrically connected to the control terminal of the first transistor, and an output terminal of the first transistor is electrically connected to the first node (see e.g. transistor T11 and/or transistor T12 in Fig. 1); and
a second control unit, comprising a second transistor, wherein a control terminal of the second transistor is configured to receive the pull-up control signal, an input terminal of the second transistor is electrically connected to the first voltage terminal, and an output terminal of the second transistor is electrically connected to the second node (see e.g. transistor T52 in Fig. 1).
Regarding claim 3, Zhou discloses all the claim limitations as applied above (see claim 2). In addition, Zhou discloses the inverting module comprises:
a third transistor, wherein a control terminal of the third transistor is electrically connected to the low-frequency clock signal terminal, an input terminal of the third transistor is electrically connected to the control terminal of the third transistor, and an output terminal of the third transistor is electrically connected to the second node (see e.g. transistor T51A and/or transistor T51B in Fig. 1);
a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the second node, an input terminal of the fourth transistor is electrically connected to the low-frequency clock signal terminal, and an output terminal of the fourth transistor is electrically connected to the third node (see e.g. transistor T53 in Fig. 1);
a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the first node, an input terminal of the fifth transistor is electrically connected to the first voltage terminal, and an output terminal of the fifth transistor is electrically connected to the second node (see e.g. transistor T52 in Fig. 1, also as the claimed fifth transistor); and
a sixth transistor, wherein a control terminal of the sixth transistor is electrically connected to the first node, an input terminal of the sixth transistor is electrically connected to the first voltage terminal, and an output terminal of the sixth transistor is electrically connected to the third node (see e.g. transistor T54 in Fig. 1).
Regarding claim 4, Zhou discloses all the claim limitations as applied above (see claim 3). In addition, Zhou discloses the pull-down holding module comprises:
a seventh transistor, wherein a control terminal of the seventh transistor is electrically connected to the third node, an input terminal of the seventh transistor is electrically connected to the first voltage terminal, and an output terminal of the seventh transistor is electrically connected to the first node (see e.g. transistor T43A and/or transistor T44A in Fig. 1).
Regarding claim 5, Zhou discloses all the claim limitations as applied above (see claim 4). In addition, Zhou discloses the pull-up control module further comprises:
a third control unit, comprising an eighth transistor, wherein a control terminal of the eighth transistor is configured to receive the pull-up control signal, an input terminal of the eighth transistor is electrically connected to the first voltage terminal, and an output terminal of the eighth transistor is electrically connected to the third node (see e.g. transistor T56 in Fig. 1).
Regarding claim 7, Zhou discloses all the claim limitations as applied above (see claim 1). In addition, Zhou discloses the pull-down holding module comprises a ninth transistor, a control terminal of the ninth transistor is electrically connected to the third node, an input terminal of the ninth transistor is electrically connected to the first voltage terminal, and an output terminal of the ninth transistor is electrically connected to a signal output terminal of the gate driving circuit (see the claimed pull-down holding module also comprising e.g. transistor T31A in Fig. 1).
Regarding claim 8, Zhou discloses all the claim limitations as applied above (see claim 1). In addition, Zhou discloses an output module, comprising an output transistor and a first capacitor (see transistors T21 and/or T22, and capacitors C1 and/or C2 in Fig. 1), wherein a control terminal of the output transistor is electrically connected to the first node (see gate of transistors T1 and/or T22 connected to node Q[n] in Fig. 1), an input terminal of the output transistor is electrically connected to a high-frequency clock signal terminal, and an output terminal of the output transistor is electrically connected to a signal output terminal of the gate driving circuit (see terminals of transistors T21 and/or T22 connected to clock signal terminals Cka and/or CKb and to terminals Cout[n] and/or WR[n], as shown in Fig. 1), and the first capacitor is in series between the first node and the signal output terminal (see capacitors C1 and/or C2 in series with node Q[n] and terminals Cout[n] and/or WR[n], as shown in Fig. 1);
a pull-down control module, comprising a first pull-down transistor, wherein a control terminal of the first pull-down transistor is configured to receive a pull-down control signal, an input terminal of the first pull-down transistor is electrically connected to the first voltage terminal, and an output terminal of the first pull-down transistor is electrically connected to the first node (see e.g. pull-down unit 13 comprising transistor T42 with its gate receiving a signal from Cout-PD, its input terminal connected to low potential signal terminal VGL1, and its output terminal connected to node Q[n], as shown in Fig. 1); and
a reset module, comprising a first reset transistor and a second reset transistor, wherein a control terminal of the first reset transistor and a control terminal of the second reset transistor are configured to receive a reset control signal (see reset unit 16 in Fig. 1 including transistors T46 and T45 which receive a reset signal at VST at their gate terminals), an input terminal of the first reset transistor and an input terminal of the second reset transistor are electrically connected to the first voltage terminal (input terminals of transistors T46 and T45 connected to terminal VGL3, as shown in Fig. 1), an output terminal of the first reset transistor is electrically connected to the first node (e.g., output terminal of transistor T46 is connected to node Q[n] through transistor T45, as shown in Fig. 1), and an output terminal of the second reset transistor is electrically connected to [[a]] the signal output terminal of the gate driving circuit (e.g., output terminal of transistor T45 is connected to Cout[n] through capacitor C1 and to WR[n] through C2, as shown in Fig. 1).
Regarding claim 9, Zhou discloses all the claim limitations as applied above (see claim 8). In addition, Zhou discloses the pull-down control module comprises a second pull-down transistor, a control terminal of the second pull-down transistor is configured to receive the pulldown control signal, an input terminal of the second pull-down transistor electrically connected to the first voltage terminal, and an output terminal of the second pull-down transistor is electrically connected to the signal output terminal (see e.g. pull-down unit 13 comprising transistor T41 with its gate receiving the signal from Cout-PD, its input terminal connected to low potential signal terminal VGL1 through transistor T42, and its output terminal connected to Cout[n], as shown in Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (CN 115798387 A), machine translation provided by the examiner and referenced throughout the rejection, in view of Wang (CN 115019718 A), machine translation provided by the examiner and referenced throughout the rejection.
Regarding claim 13, Zhou discloses a display panel, comprising a gate driving unit, the gate driving unit comprising a plurality of gate driving circuits arranged in cascade (see page 14, 1st paragraph; a display panel comprising a plurality of cascaded gate driving units), and at least one of the gate driving circuits comprising:
an inverting module, electrically connected to a first voltage terminal (regarding Fig. 1, see inverter 17 connected to low potential signal terminals VGL1/VGL2/VGL3, taken as the claimed first voltage terminal), a first node (see node Q[n] in Fig. 1), a second node (see node at a gate of transistor T53 in Fig. 1), and a third node (see node QB[n] in Fig. 1), configured to control a signal transmission between the first voltage terminal and the third node in response to a potential of the first node (inverter 17 is configured to control a signal transmission between e.g. terminal VGL1 and the node at the gate of transistor T53 in response to a potential of Q[n] applied to a gate of transistor T54, as shown in Fig. 1), and configured to control a signal transmission between a low-frequency clock signal terminal and the third node in response to a potential of the second node (inverter 17 is configured to control a signal transmission between a low frequency clock signal terminal LC and node QB[n] in response to a potential of the node at the gate of transistor T53, as shown in Fig. 1);
a pull-down holding module, electrically connected to the first voltage terminal, the first node, and the third node (see pull-down maintaining unit 14, connected e.g. to terminal VGL1, node Q[n] and node QB[n], as shown in Fig. 1), and configured to control a signal transmission between the first voltage terminal and the first node in response to a potential of the third node (pull-down maintaining unit 14 is configured to control a signal transmission between terminal VGL1 and node Q[n] in response to a potential of node QB[n] at gates of transistor T43A and T44A, as shown in Fig. 1); and
a pull-up control module, electrically connected to the first voltage terminal, the first node, and the second node (see pull-up control unit comprising transistors T11, T12, T52 and T56, connected to e.g. terminals VGL1/VGL2, node Q[n] and the node at the gate of transistor T53, as shown in Fig. 1), configured to pull up the potential of the first node in response to a pull-up control signal (regarding Figs. 1-2, when “terminal Cout-PU input high potential, the ninth transistor T11 and the tenth transistor T12 turn on” and “node Q[n] is pulled up to the high potential”; page 13, 5th paragraph), and configured to control a signal transmission between the first voltage terminal and the second node in response to the pull-up control signal (regarding Figs. 1-2, when node Q[n] is pulled up to the high potential and applied to a gate of transistor T52, a signal transmission between e.g. terminal VGL2 and the node at the gate of transistor T53 is controlled, in response to the signal at terminal Cout-PU (claimed pull-up control signal)),
wherein the pull-up control module is directly connected to the first node and the second node respectively (see in Fig. 1 that the pull-up control unit comprises transistors T11, T12, T52 and T56, that transistor T12 is directly connected to node Q[n] (claimed first node), and that transistor T52 is directly connected to the node at the gate of transistor T53 (claimed second node)), such that the pull-up control module is configured to parallelly pull up the potential of the first node and control the signal transmission between the first voltage terminal and the second node in response to the pull-up control signal (see page 24; based on the broadest reasonable interpretation of the claimed limitations, “as shown in fig. 1 and fig. 2, in the first stage T1, the second stage signal terminal Cout-PU inputs a high potential, the ninth transistor T11 and the tenth transistor T12 are turned on, the first node Q [N] is pulled up to the high potential”, and at the same time, in response to this, transistor T52 is turned on and the low potential signal VGL2 is applied to the gate of transistor T53, as claimed);
wherein when the pull-up control module is configured to electrically connect the first voltage terminal and the second node in response to the pull-up control signal, the inverting module is configured to disconnect an electrical connection between the low-frequency clock signal terminal and the third node in response to the potential of the second node (regarding Figs. 1-2, when terminal VGL2 and the node at the gate of transistor T53 are connected in response to the signal at terminal Cout-PU, inverter 17 is configured to disconnect the low frequency clock signal terminal LC and node QB[n], by turning off transistor T53 in response to the low potential signal VGL2 applied to the gate of transistor T53 (the claimed second node) through transistor T52), the inverting module is also configured to control an electrical connection between the first voltage terminal and the third node in response to the potential of the first node (regarding Figs. 1-2, inverter 17 is also configured to control a connection between e.g. terminal VGL1 and node QB[n] in response to the potential of node Q[n] applied to the gate of transistor T54), and the pull-down holding module is configured to disconnect an electrical connection between the first voltage terminal and the first node in response to the potential of the third node (regarding Figs. 1-2, the pull-down maintaining unit 14 is configured to disconnect e.g. terminal VGL1 and Q[n] in response to the low potential signal VGL1 at QB[n] applied to the gates of transistors T43A and T44A).
However, Zhou does not appear to expressly disclose an (n-4)th stage gate control signal output by an (n-4)th stage gate driving circuit serves as the pull-up control signal received by the pull-up control module of the n-th stage gate driving circuit.
Wang discloses an (n-4)th stage gate control signal output by an (n-4)th stage gate driving circuit serves as a pull-up control signal received by a pull-up control module of the n-th stage gate driving circuit (see page 7; regarding Figs. 1-3, an (n-4)th stage gate driving circuit GOA serves as a pull-up control signal ST(n-4) received by a pull-up control module 101 of the n-th stage gate driving circuit GOA; “the pull-up control module 101 is connected to the first stage first stage transmission signal ST (n-4)”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Zhou’s invention, with the teachings in Wang’s invention, to have an (n-4)th stage gate control signal output by an (n-4)th stage gate driving circuit serves as the pull-up control signal received by the pull-up control module of the n-th stage gate driving circuit, for the advantage improving stability of the gate driving circuit in order to display normally while facilitating a narrow frame design of the display panel (see Abstract).
Regarding claim 15, Zhou and Wang disclose all the claim limitations as applied above (see claim 13). In addition, Zhou discloses a plurality of sub-pixels electrically connected to the gate driving unit (regarding Fig. 1, it is clear that since, e.g., “the output signal end WR [n] turn on the signal of the switch transistor in the pixel of the present stage”, and since “the existing display device uses the GOA (Gate Driver On Array, array substrate row driving technology)”, each gate driving unit 10 is connected to a plurality of pixels in a corresponding row; page 1, 3rd paragraph; page 13, 4th paragraph).
Regarding claim 16, Zhou and Wang disclose all the claim limitations as applied above (see claim 13). In addition, Zhou discloses the pull-up control module comprises:
a first transistor, wherein a control terminal of the first transistor is configured to receive the pull-up control signal, an input terminal of the first transistor is electrically connected to the control terminal of the first transistor, and an output terminal of the first transistor is electrically connected to the first node (see e.g. transistor T11 and/or transistor T12 in Fig. 1); and
a second transistor, wherein a control terminal of the second transistor is configured to receive the pull-up control signal, an input terminal of the second transistor is electrically connected to the first voltage terminal, and an output terminal of the second transistor is electrically connected to the second node (see e.g. transistor T52 in Fig. 1).
Regarding claim 17, Zhou and Wang disclose all the claim limitations as applied above (see claim 16). In addition, Zhou discloses the inverting module comprises:
a third transistor, wherein a control terminal of the third transistor is electrically connected to the low-frequency clock signal terminal, an input terminal of the third transistor is electrically connected to the control terminal of the third transistor, and an output terminal of the third transistor is electrically connected to the second node (see e.g. transistor T51A and/or transistor T51B in Fig. 1);
a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the second node, an input terminal of the fourth transistor is electrically connected to the low-frequency clock signal terminal, and an output terminal of the fourth transistor is electrically connected to the third node (see e.g. transistor T53 in Fig. 1);
a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the first node, an input terminal of the fifth transistor is electrically connected to the first voltage terminal, and an output terminal of the fifth transistor is electrically connected to the second node (see e.g. transistor T52 in Fig. 1, also as the claimed fifth transistor); and
a sixth transistor, wherein a control terminal of the sixth transistor is electrically connected to the first node, an input terminal of the sixth transistor is electrically connected to the first voltage terminal, and an output terminal of the sixth transistor is electrically connected to the third node (see e.g. transistor T54 in Fig. 1).
Regarding claim 18, Zhou and Wang disclose all the claim limitations as applied above (see claim 17). In addition, Zhou discloses the pull-down holding module comprises:
a seventh transistor, wherein a control terminal of the seventh transistor is electrically connected to the third node, an input terminal of the seventh transistor is electrically connected to the first voltage terminal, and an output terminal of the seventh transistor is electrically connected to the first node (see e.g. transistor T43A and/or transistor T44A in Fig. 1).
Regarding claim 19, Zhou and Wang disclose all the claim limitations as applied above (see claim 18). In addition, Zhou discloses the pull-up control module further comprises:
an eighth transistor, wherein a control terminal of the eighth transistor is configured to receive the pull-up control signal, an input terminal of the eighth transistor is electrically connected to the first voltage terminal, and an output terminal of the eighth transistor is electrically connected to the third node (see e.g. transistor T56 in Fig. 1).
Regarding claim 20, Zhou and Wang disclose all the claim limitations as applied above (see claim 13). In addition, Zhou discloses the at least one of the gate driving circuits further comprises:
an output module, comprising an output transistor and a first capacitor (see transistors T21 and/or T22, and capacitors C1 and/or C2 in Fig. 1), wherein a control terminal of the output transistor is electrically connected to the first node (see gate of transistors T1 and/or T22 connected to node Q[n] in Fig. 1), an input terminal of the output transistor is electrically connected to a high-frequency clock signal terminal, and an output terminal of the output transistor is electrically connected to a signal output terminal of the gate driving circuit (see terminals of transistors T21 and/or T22 connected to clock signal terminals Cka and/or CKb and to terminals Cout[n] and/or WR[n], as shown in Fig. 1), and the first capacitor is in series between the first node and the signal output terminal (see capacitors C1 and/or C2 in series with node Q[n] and terminals Cout[n] and/or WR[n], as shown in Fig. 1);
a pull-down control module, comprising a first pull-down transistor, wherein a control terminal of the first pull-down transistor is configured to receive a pull-down control signal, an input terminal of the first pull-down transistor is electrically connected to the first voltage terminal, and an output terminal of the first pull-down transistor is electrically connected to the first node (see e.g. pull-down unit 13 comprising transistor T42 with its gate receiving a signal from Cout-PD, its input terminal connected to low potential signal terminal VGL1, and its output terminal connected to node Q[n], as shown in Fig. 1); and
a reset module, comprising a first reset transistor and a second reset transistor, wherein a control terminal of the first reset transistor and a control terminal of the second reset transistor are configured to receive a reset control signal (see reset unit 16 in Fig. 1 including transistors T46 and T45 which receive a reset signal at VST at their gate terminals), an input terminal of the first reset transistor and an input terminal of the second reset transistor are electrically connected to the first voltage terminal (input terminals of transistors T46 and T45 connected to terminal VGL3, as shown in Fig. 1), an output terminal of the first reset transistor is electrically connected to the first node (e.g., output terminal of transistor T46 is connected to node Q[n] through transistor T45, as shown in Fig. 1), and an output terminal of the second reset transistor is electrically connected to [[a]] the signal output terminal of the gate driving circuit (e.g., output terminal of transistor T45 is connected to Cout[n] through capacitor C1 and to WR[n] through C2, as shown in Fig. 1).
Allowable Subject Matter
Claims 6 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, the reasons for the indication of allowable subject matter provided in the Non-Final office action mailed on 3/4/2026.
Claim 21 is allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 21, the prior art, taken alone or in combination, fails to teach or suggest the following limitations in combination with the rest of the claim, that is, the claim as a whole: “A display panel, comprising a gate driving unit, the gate driving unit comprising: a plurality of gate driving circuits arranged in cascade, and at least one of the gate driving circuits comprising: an inverting module, electrically connected to a first voltage terminal, a first node, a second node, and a third node, configured to control a signal transmission between the first voltage terminal and the third node in response to a potential of the first node, and configured to control a signal transmission between a low-frequency clock signal terminal and the third node in response to a potential of the second node; a pull-down holding module, electrically connected to the first voltage terminal, the first node, and the third node, and configured to control a signal transmission between the first voltage terminal and the first node in response to a potential of the third node; and a pull-up control module, electrically connected to the first voltage terminal, the first node, and the second node, configured to pull up the potential of the first node in response to a pull-up control signal, and configured to control a signal transmission between the first voltage terminal and the second node in response to the pull-up control signal, wherein when the pull-up control module is configured to electrically connect the first voltage terminal and the second node and pull up the potential of the first node in response to the pull-up control signal, the inverting module is configured to disconnect an electrical connection between the low-frequency clock signal terminal and the third node in response to the potential of the second node, the inverting module is also configured to control an electrical connection between the first voltage terminal and the third node in response to the potential of the first node, and the pull-down holding module is configured to disconnect an electrical connection between the first voltage terminal and the first node in response to the potential of the third node; and wherein an (n-4)th stage gate control signal output by an (n-4)th stage gate driving circuit serves as the pull-up control signal received by the pull-up control module of then-th stage gate driving circuit; and wherein a voltage of a low-frequency clock signal transmitted by the low-frequency clock signal terminal during a sensing phase of the display panel is less than a voltage of the low-frequency clock signal during a display phase of the display panel”, as claimed in claim 21.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed on 5/15/2026 have been fully considered but they are not persuasive.
Regarding claim 1 (and similar claim 13), the applicant argues on pages 3-6 that
“Zhou fails to disclose, teach, or suggest the limitations of "wherein the pull-up control module is directly connected to the first node and the second node respectively, such that the pull-up control module is configured to parallelly pull up the potential of the first node and control the signal transmission between the first voltage terminal and the second node in response to the pull-up control signal; wherein when the pull-up control module is configured to electrically connect the first voltage terminal and the second node in response to the pull-up control signal, the inverting module is configured to disconnect an electrical connection between the low-frequency clock signal terminal and the third node in response to the potential of the second node, the inverting module is also configured to control an electrical connection between the first voltage terminal and the third node in response to the potential of the first node, and the pull-down holding module is configured to disconnect an electrical connection between the first voltage terminal and the first node in response to the potential of the third
node" as recited in the amended claim 1”. The examiner respectfully disagrees. As shown in the above rejection, Zhou discloses the pull-up control module is directly connected to the first node and the second node respectively (see in Fig. 1 that the pull-up control unit comprises transistors T11, T12, T52 and T56, that transistor T12 is directly connected to node Q[n] (claimed first node), and that transistor T52 is directly connected to the node at the gate of transistor T53 (claimed second node)), such that the pull-up control module is configured to parallelly pull up the potential of the first node and control the signal transmission between the first voltage terminal and the second node in response to the pull-up control signal (see page 24; based on the broadest reasonable interpretation of the claimed limitations, “as shown in fig. 1 and fig. 2, in the first stage T1, the second stage signal terminal Cout-PU inputs a high potential, the ninth transistor T11 and the tenth transistor T12 are turned on, the first node Q [N] is pulled up to the high potential”, and at the same time, in response to this, transistor T52 is turned on and the low potential signal VGL2 is applied to the gate of transistor T53, as claimed); wherein when the pull-up control module is configured to electrically connect the first voltage terminal and the second node in response to the pull-up control signal, the inverting module is configured to disconnect an electrical connection between the low-frequency clock signal terminal and the third node in response to the potential of the second node (regarding Figs. 1-2, when terminal VGL2 and the node at the gate of transistor T53 are connected in response to the signal at terminal Cout-PU, inverter 17 is configured to disconnect the low frequency clock signal terminal LC and node QB[n], by turning off transistor T53 in response to the low potential signal VGL2 applied to the gate of transistor T53 (the claimed second node) through transistor T52), the inverting module is also configured to control an electrical connection between the first voltage terminal and the third node in response to the potential of the first node (regarding Figs. 1-2, inverter 17 is also configured to control a connection between e.g. terminal VGL1 and node QB[n] in response to the potential of node Q[n] applied to the gate of transistor T54), and the pull-down holding module is configured to disconnect an electrical connection between the first voltage terminal and the first node in response to the potential of the third node (regarding Figs. 1-2, the pull-down maintaining unit 14 is configured to disconnect e.g. terminal VGL1 and Q[n] in response to the low potential signal VGL1 at QB[n] applied to the gates of transistors T43A and T44A).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GLORYVID FIGUEROA-GIBSON whose telephone number is (571)272-5506. The examiner can normally be reached on 9am-5pm, Monday -Friday, Eastern Time.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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