Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "K is equal to M, and the mth first turn-on signal line”. There is insufficient antecedent basis for this limitation in the claim. Specifically, M and m are defined in claim 3, however, claim 9 is ultimately dependent upon claim 2 which does not provide an antecedent basis for such limitations.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita et al., US 2015/0356934 A1, hereinafter “Yamashita”.
Regarding claim 1, Yamashita teaches a display panel (fig. 3, element 10, ¶ 60), comprising: a plurality of gate lines (fig. 3, lines 46, ¶ 62); and a plurality of shift register units (fig. 9, element 38-1, 121-1 and 38-2, 121-2; ¶ 81), wherein a target shift register unit of the plurality of shift register units comprises: a frame trigger selecting circuit (fig. 9, element 121, ¶ 82) and a gate driving circuit (fig. 9, element 38, ¶ 81); the gate driving circuit comprises a plurality of first shift registers (fig. 9, element 122, ¶ 81), a driving output terminal of each first shift register is coupled to at least one of the gate lines (¶ 81), the plurality of first shift registers are divided into N cascade groups (fig. 9 discloses 4 cascade groups 120), the first shift registers in each cascade group are cascaded (¶ 82, see connection of a respective GSP signal to a first stage of the shift register 120), and different cascade groups are coupled to different frame starting signal terminals (¶ 82, fig. 9); N is an integer greater than 1, wherein the frame trigger selecting circuit is coupled to a frame trigger input terminal (fig. 9, GSP-L) and the frame starting signal terminals corresponding to the N cascade groups (fig. 10, SP signals are received by the gate driver segments 120, ¶ 83); the frame trigger selecting circuit is configured to output, in response to an nth turn-on signal of N turn-on signals corresponding to an nth cascade group of the N cascade groups, a starting signal input to the frame trigger input terminal to a frame starting signal terminal corresponding to the nth cascade group (see ¶ 83 and fig. 10); n is more than or equal to 1 and less than or equal to N, and n is an integer; and the nth cascade group is configured to scan the gate lines coupled thereto line by line after the frame starting signal terminal corresponding thereto receives the starting signal (¶ 69; note that the start signal for each cascaded group starts such a row by row scanning).
Regarding claim 2, Yamashita teaches that the frame trigger selecting circuit comprises: N frame trigger selecting sub-circuits (fig. 10, see the “pass transistors” 123 for each SP line), the N frame trigger selecting sub-circuits corresponding to the N cascade groups and the N tum-on signals one by one (fig. 10, SP1-SP4 corresponding to four cascade groups also correspond to CTR[1] to CTR[4]); input terminals of the N frame trigger selecting sub-circuits are coupled to the frame trigger input terminal (fig. 10, see connection to GSP), and an output terminal of an nth frame trigger selecting sub-circuit of the N frame trigger selecting sub-circuits is coupled to the frame starting signal terminal corresponding to the nth cascade group (fig. 10, see connection to SPn); and the nth frame trigger selecting sub-circuit is configured to output, in response to the nth tum-on signal, the starting signal input to the frame trigger input terminal to the frame starting signal terminal corresponding to the nth cascade group (¶ 83).
Regarding claim 3, Yamashita teaches that the nth frame trigger selecting sub-circuit comprises: M trigger transistors (fig. 10, see trigger or pass transistors 123, ¶ 83), a first electrode of a first trigger transistor of the M trigger transistors is coupled to the frame trigger input terminal, a second electrode of a former one of every two adjacent trigger transistors is coupled to a first electrode of a latter one of the two adjacent trigger transistors, and a second electrode of a last trigger transistor of the M trigger transistors is coupled to the frame starting signal terminal corresponding to the nth cascade group (see fig. 10, ¶ 83); the n turn-on signal comprises M level signals, and a gate of an mth trigger transistor of the M trigger transistors is configured to receive an mth level signal of the M level signals; and M is an integer greater than 0, m is greater than or equal to 1 and less than or equal to M, and m is an integer (fig. 10, ¶ 83).
Regarding claim 4, Yamashita teaches that the trigger transistors in at least part of the frame trigger selecting sub-circuits are of different types (¶ 83: “demultiplexing circuit 121 may be implemented using … using n-channel or p-channel TFTs, and/or any suitable type of switching circuits); the display panel further comprises: M first turn-on signal lines (fig. 10, CTR lines), the mth level signal is input through an mth first tum-on signal line of the M first turn-on signal lines; and the gate of the mth trigger transistor in each frame trigger selecting sub-circuit is coupled to the mth first turn-on signal line of the M first turn-on signal lines (¶ 83).
Regarding claim 15, Yamashita teaches a display apparatus, comprising the display panel of claim 1 (fig. 1, element 6, ¶ 49).
Regarding claim 16, Yamashita teaches a method for driving the display panel of claims1 comprising: in response to that a first driving mode is adopted, during a display frame, the N turn-on signals are sequentially applied to the frame trigger selecting circuit, then the N cascade groups respectively receive the starting signal through frame starting signal terminals corresponding thereto to control the cascade groups to operate in sequence and the shift registers in each cascade group scans the gate lines coupled thereto line by line, and the plurality of gate lines are scanned line by line (fig. 10, ¶ 83, each of SP1-10 may be controlled to be output sequentially in order to drive the display according to such a first driving mode); and in response to that a second driving mode is adopted, during a display frame, a turn-on signal corresponding to a specified cascade group is applied to the frame trigger selecting circuit, then the specified cascade group receives the starting signal through a frame starting signal terminal corresponding thereto to control the shift registers in the specified cascade group to scan the gate lines coupled thereto line by line (fig. 10, ¶ 83, each of SP1-10 may be controlled individually and in any order to drive the display according to a second driving mode).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita.
Regarding claim 5, Yamashita teaches that the trigger transistors in all of the frame trigger selecting sub-circuits are of the same type (fig. 10, elements 123).
Yamashita does not specifically teach that the display panel further comprises: M signal line groups, each of the M signal line groups comprises a second turn-on signal line and a third tum-on signal line, the second turn-on signal line and the third tum-on signal line in each signal line group simultaneously transmit signals with opposite phases; the mth trigger transistor in each frame trigger selecting sub-circuit corresponds to an mth signal line group of the M signal line groups, and the gates of the mth trigger transistors in part of the frame trigger selecting sub-circuits are coupled to the second turn-on signal line in the mth signal line group, and the gates of the mth trigger transistors in the rest of the frame trigger selecting sub-circuits are coupled to the third turn-on signal line in the mth signal line group.
However, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Yamashita in order to achieve such a configuration. Per ¶ 83 of Yamashita, the demultiplexer configuration of fig. 10 is “merely illustrative” and “any suitable type of switching circuits” may be used to implement such a circuit. As such, one would have been motivated to modify the demultiplexer circuit of Yamashita using any suitable configuration with the expectation of achieving the same result of sending the GSP signal to an appropriate SP line.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita, in view of Jang et al., US 2006/0146979 A1, hereinafter “Jang”.
Regarding claim 6, Yamashita does not specifically teach that the target shift register unit further comprises: N noise reduction circuits, the N noise reduction circuits corresponding to the N frame trigger selecting sub-circuits and N noise reduction control signals one by one; and an nth noise reduction circuit of the N noise reduction circuits is configured to output, in response to an nth noise reduction control signal of the N noise reduction control signals, a signal at a noise reduction reference signal terminal to the frame starting signal terminal corresponding to the nth cascade group.
Jang, however, teaches that each start signal output for a shift register unit comprises a noise reduction circuit (fig. 5, Tc, ¶ 39), and the noise reduction circuit is configured to output, in response to a noise control reduction control signal (C1 and or C2), a signal at a noise reduction reference signal terminal (fig. 5, see the ground signal, ¶ 41), to the starting signal terminal (fig. 5, VST1/2).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Yamashita in view of Jang in order to apply a noise reduction signal to each of the SP lines of Yamashita. One would have been motivated to make such a combination since Jang clearly teaches that by adopting such a noise reduction circuit “improper operation of the shift register due to noise is prevented”.
Regarding claim 7, Yamashita does not teach that the nth noise reduction circuit comprises: K noise reduction transistors, a first electrode of each of the K noise reduction transistors is coupled to the noise reduction reference signal terminal, and a second electrode of each of the K noise reduction transistors is coupled to the frame starting signal terminal; an nth noise reduction control signal comprises K level signals, and the gate of a kth noise reduction transistor of the K noise reduction transistors is configured to receive a kth level signal of the K level signals; and K is an integer greater than 0, k is greater than or equal to 1 and less than or equal to K, and k is an integer.
Jang teaches that the nth noise reduction circuit comprises: K noise reduction transistors (fig. 5, transistor Tc), a first electrode of each of the K noise reduction transistors is coupled to the noise reduction reference signal terminal (ground), and a second electrode of each of the K noise reduction transistors is coupled to the frame starting signal terminal (VST); an nth noise reduction control signal comprises K level signals, and the gate of a kth noise reduction transistor of the K noise reduction transistors is configured to receive a kth level signal of the K level signals (fig. 5, C1 and or C2, ¶ 40-42); and K is an integer greater than 0, k is greater than or equal to 1 and less than or equal to K, and k is an integer.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Yamashita in view of Jang in order to apply a noise reduction signal to each of the SP lines of Yamashita. One would have been motivated to make such a combination since Jang clearly teaches that by adopting such a noise reduction circuit “improper operation of the shift register due to noise is prevented”.
Regarding claim 8, Yamashita does not teach that the noise reduction transistors in at least part of the noise reduction circuits are different in type; the display panel further comprises: K noise reduction control signal lines; the kth level signal is input through a kth noise reduction control signal line of the K noise reduction control signal lines; and the gate of the kth noise reduction transistor in each noise reduction circuit is coupled to the kth noise reduction control signal line of the K noise reduction control signal lines.
Jang teaches that the noise reduction transistors in at least part of the noise reduction circuits are the same type (fig. 5, Tc transistors); the display panel further comprises: K noise reduction control signal lines (C1 and C2); the kth level signal is input through a kth noise reduction control signal line of the K noise reduction control signal lines (¶ 40-42); and the gate of the kth noise reduction transistor in each noise reduction circuit is coupled to the kth noise reduction control signal line of the K noise reduction control signal lines (¶ 40-42).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Yamashita in view of Jang in order to apply a noise reduction signal to each of the SP lines of Yamashita. One would have been motivated to make such a combination since Jang clearly teaches that by adopting such a noise reduction circuit “improper operation of the shift register due to noise is prevented”. Furthermore, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to simply modify the type of some of at least one of the Tc transistors in Jang. Per ¶ 40-42 of Jang, and fig. 6, the transistors operate inversely to each other and are connected to two lines C1 and C2 carrying inverse signals. As such, one would have been motivated to use a different type of transistor for at least one of the Tc transistors in order to control the transistors using a same control line such as C1, thereby facilitating the implementation of such transistors.
Regarding claim 9, Yamashita does not teach that K is equal to M, and the mth first turn-on signal line and kth noise reduction control signal line simultaneously transmit signals having the same or opposite phases.
Jang, however, teaches that K is equal to M (two control lines and two VST output lines), and the mth first turn-on signal line and kth noise reduction control signal line simultaneously transmit signals having the same or opposite phases (¶ 42 and fig. 6, the signals are “synchronized” in order to apply noise reduction at the time that VST is being transferred).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Yamashita in view of Jang in order to apply a noise reduction signal to each of the SP lines of Yamashita. One would have been motivated to make such a combination since Jang clearly teaches that by adopting such a noise reduction circuit “improper operation of the shift register due to noise is prevented”.
Claims 10-14 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita, in view of Takahara, US 2015/0255015 A1, hereinafter “Takahara”
Regarding claim 10, Yamashita teaches that the plurality of gate lines comprises a plurality of first gate lines (fig. 3, lines 46-1, ¶ 62); the target shift register unit comprises a first target shift register unit (fig. 3, element 38-1, ¶ 62); a driving output terminal of each first shift register in the first target shift register unit is coupled to at least one of the first gate lines (see fig. 3).
Yamashita does not teach that the display panel comprises a pixel circuit, the pixel circuit comprises a turn-on control transistor; one of the first gate lines is coupled to a gate of the tum-on control transistor, and is configured to drive the tum-on control transistor.
Takahara, however, teaches that the display panel comprises a pixel circuit (fig. 40), the pixel circuit comprises a turn-on control transistor (fig. 40, Q125, ¶ 441); one of the first gate lines is coupled to a gate of the tum-on control transistor (fig. 40, CNT125), and is configured to drive the tum-on control transistor (¶ 441).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Yamashita in view of Takahara. The references teach display devices including pixels and Takahara teaches further details regarding such pixels and their corresponding circuits. As such, one would have been motivated to make such a combination in order to provide an appropriate circuit for the pixels and control such pixels using the gate signals as driven per teachings of Yamashita, thereby providing a display device as required by the references.
Regarding claims 11 and 17, Yamashita teaches that the plurality of gate lines comprises a plurality of second gate lines (fig. 3, lines 46-2, ¶ 62); the target shift register unit comprises a second target shift register unit (fig. 3, element 38-2, ¶ 62); a driving output terminal of each first shift register in the second target shift register unit is coupled to at least one of the second gate lines (see fig. 3).
Yamashita does not teach that the display panel comprises a pixel circuit, the pixel circuit comprises a data writing transistor; one of the second gate lines is coupled to a gate of the data writing transistor, and configured to drive the data writing transistor.
Takahara, however, teaches that the display panel comprises a pixel circuit, the pixel circuit comprises a data writing transistor (fig. 40, Q122, ¶ 427); one of the second gate lines is coupled to a gate of the data writing transistor (fig. 40, CNT122, ¶ 451), and configured to drive the data writing transistor (¶ 451).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Yamashita in view of Takahara. The references teach display devices including pixels and Takahara teaches further details regarding such pixels and their corresponding circuits. As such, one would have been motivated to make such a combination in order to provide an appropriate circuit for the pixels and control such pixels using the gate signals as driven per teachings of Yamashita, thereby providing a display device as required by the references.
Regarding claims 12 and 18, Yamashita teaches that each first shift register in the target shift register unit comprises a left first shift register (fig. 3, element 38-1, ¶ 62) and a right first shift register coupled to the gate line at two sides of the gate line (fig. 3, element 38-2, ¶ 62), respectively;
Yamashita does not specifically teach that the left first shift register and the right first shift register are configured to simultaneously drive the gate line coupled thereto.
Takahara, however, teaches that the left first shift register and the right first shift register are configured to simultaneously drive the gate line coupled thereto (figs. 33-37, ¶ 316).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Yamashita in view of Takahara. The references teach display devices including pixels and Takahara teaches further details regarding such pixels, their corresponding circuits and driving schemes. Per Takahara in ¶ 316, such bilateral driving enables faster scan speeds, motivating one of ordinary skill to make such a combination.
Regarding claims 13 and 19, Yamashita does not specifically teach that the display panel further comprises: a plurality of light emission control signal lines; the plurality of shift register units further comprise: a light emission control circuit; the light emission control circuit comprises a plurality of second shift registers, and a driving output terminal of each second shift register is coupled to at least one of the light emission control signal lines; and the display panel comprises a pixel circuit; the pixel circuit comprises a first light emission control transistor; the light emission control signal line is coupled to a gate of the first light emission control transistor, and is configured to drive the first light emission control transistor.
Takahara, however, teaches that the display panel further comprises: a plurality of light emission control signal lines (fig. 40, lines CNT123, ¶ 455); the plurality of shift register units further comprise: a light emission control circuit (fig. 43, ¶ 489-490, elements 130 and 132B); the light emission control circuit comprises a plurality of second shift registers, and a driving output terminal of each second shift register is coupled to at least one of the light emission control signal lines (see fig. 43, ¶ 489-490); and the display panel comprises a pixel circuit; the pixel circuit comprises a first light emission control transistor (fig. 40, element Q123, ¶ 427); the light emission control signal line is coupled to a gate of the first light emission control transistor, and is configured to drive the first light emission control transistor (¶ 427).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Yamashita in view of Takahara. The references teach display devices including pixels and Takahara teaches further details regarding such pixels and their corresponding circuits. As such, one would have been motivated to make such a combination in order to provide an appropriate circuit for the pixels and control such pixels using the gate signals as driven per teachings of Yamashita, thereby providing a display device as required by the references.
Regarding claims 14 and 20, Yamashita does not teach that the display panel further comprises: a plurality of reset control signal lines; the plurality of shift register units further comprise: a reset control circuit; the reset control circuit comprises a plurality of third shift registers, and a driving output terminal of each third shift register is coupled to at least one of the reset control signal lines; and the display panel comprises a pixel circuit; the pixel circuit comprises an anode reset transistor; the reset control signal line is coupled to a gate of the anode reset transistor and is configured to drive the anode reset transistor.
Takahara, however, teaches that the display panel further comprises: a plurality of reset control signal lines (fig. 40, CNT124, ¶ 441-442); the plurality of shift register units further comprise: a reset control circuit (fig. 43, ¶ 489-490, elements 130 and 132C); the reset control circuit comprises a plurality of third shift registers, and a driving output terminal of each third shift register is coupled to at least one of the reset control signal lines (see fig. 43, ¶ 489-490); and the display panel comprises a pixel circuit; the pixel circuit comprises an anode reset transistor (fig. 40, Q124, ¶ 441-442); the reset control signal line is coupled to a gate of the anode reset transistor and is configured to drive the anode reset transistor (¶ 441-442).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Yamashita in view of Takahara. The references teach display devices including pixels and Takahara teaches further details regarding such pixels and their corresponding circuits. As such, one would have been motivated to make such a combination in order to provide an appropriate circuit for the pixels and control such pixels using the gate signals as driven per teachings of Yamashita, thereby providing a display device as required by the references.
Conclusion
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/SEPEHR AZARI/ Primary Examiner, Art Unit 2621