DETAILED ACTION
1. Applicant’s Amendment filed 07/28/2026 has been reviewed and placed of record in the file.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
2. Claims 1, 6-7 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KUAMI HIROSHI JP 2004146483, MANUFACTURING METHOD OF GALLIUM NITRIDE-BASED SOLID SOLUTION THIN FILM (hereinafter referred to as the ‘483 reference, of record and cited in a Japanese Office Action (12-page NPL) regarding a corresponding Japanese patent application), citation below is based on an English translation by PE2E (04/30/2026 NPL).
Referring to claim 1, the reference discloses a semiconductor substrate, comprising:
a substrate (30 and/or underlying layer 31 (30/31), Figs. 1, 3, para [28, 31] (paragraph(s) [0028], [0031])); and
a semiconductor layer (32, Fig. 3, para [31]) disposed on an upper portion of the substrate (30/31).
Note that the limitation “wherein the semiconductor layer is a sputter-deposited semiconductor layer, and wherein the semiconductor layer has been formed under application of additional energy comprising at least one selected from the group consisting of an electron beam, laser light, and LED light” has been taken to be a product-by-process limitation and considered non-limitation in a product claim (MPEP 2112.01 and MPEP 2113). In the instant case, product-by-process limitations “wherein the semiconductor layer is a sputter-deposited semiconductor layer” and “wherein the semiconductor layer has been formed under application of additional energy comprising at least one selected from the group consisting of an electron beam, laser light, and LED light” as claimed, while not improper in a product claim, is only evaluated to determine the final claimed properties and claimed characteristics of the product (MPEP 2113 [R-1]); and as such, in the instant case, no claimed properties and characteristics can be found for the purpose of comparing the claim “semiconductor layer” with the prior art “semiconductor layer”; and as such, said limitations appear to be a non-limitation.
Referring to claim 6, although not explicitly disclosed, the substrate (30) comprises a polycrystalline substrate because it is formed at a high temperature (2000 °C, para [28]). See, for example, SCHWABEDISSEN et al. U.S. Patent Application Publication 20240038909, para [46], that even at 1000 °C polycrystalline is established.
Referring to claim 7, the reference further discloses that the substrate (30) comprises a glass substrate (“sapphire”, para [28]), meeting the claim limitation ”at least one of a glass substrate, a quartz substrate, a stainless steel substrate, and a polymer substrate”.
Referring to claim 11, the reference further discloses a middle layer (31, Fig. 3) disposed between the substrate (30) and the semiconductor layer (32) and consisting of aluminum nitride (para [31]), meeting the claim limitation “at least one of aluminum nitride and zinc oxide”.
3. Claims 1, 7 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Coombe U.S. Patent 5,382,457 (the ‘457 reference).
Referring to claim 1, the ‘457 reference discloses a semiconductor substrate, comprising:
a substrate (102, Fig. 1, col. 3, lines 24-26); and
a semiconductor layer (a thin film of II-VI compound, col. 3, lines 24-26) disposed on an upper portion of the substrate (102).
In a manner similar to that detailed above for claim 1 in paragraph numbered 2, the limitation “wherein the semiconductor layer is a sputter-deposited semiconductor layer, and wherein the semiconductor layer has been formed under application of additional energy comprising at least one selected from the group consisting of an electron beam, laser light, and LED light” has been taken to be a product-by-process limitation and considered non-limitation in a product claim.
Referring to claim 7, the reference further discloses that the substrate (102) comprises a glass substrate (silica, col. 7, lines 5-10), meeting the claim limitation ”at least one of a glass substrate, a quartz substrate, a stainless steel substrate, and a polymer substrate”.
Referring to claim 13 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a method of manufacturing a semiconductor structure, the method comprising:
providing a substrate (102, Fig. 1); and
depositing a semiconductor layer on an upper portion of the substrate by sputtering (col. 4, lines 34+) while supplying additional energy during deposition of the semiconductor layer (col. 4, lines 56+/- “…they remain illuminated by laser beam 126…”), wherein the additional energy comprises laser light, meeting the claim limitation “at least one selected from the group consisting of an electron beam, laser light, and LED light”.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
4. Claims 8-10 are rejected under 35 U.S.C. §103 as being unpatentable over KUAMI HIROSHI JP 2004146483 (the ‘483 reference) in view of Hattori et al. U.S. Patent Application Publication 20120205649 (both of record).
Referring to claims 8-10, the ‘483 reference discloses a semiconductor device including the semiconductor layer 32, but does not discloses (claim 8) that the semiconductor layer is a silicon semiconductor layer having any one of polycrystalline, microcrystalline, and nanocrystalline crystal structures, (claim 9) that the semiconductor layer is an InGaZnO-based oxide semiconductor layer, and (claim 10) that the semiconductor layer is a CuInSe2-based group 1-3-5 compound semiconductor layer.
Hattori, in disclosing a semiconductor device comprising a semiconductor layer, teaches that the semiconductor layer comprises polycrystalline silicon (para [42]), InGaZnO (para [59]), or CuInSe2-based semiconductor (para [5]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s semiconductor layer utilizing polycrystalline silicon, InGaZnO, or CuInSe2-based semiconductor. One would have been motivated to make such a modification in view of the teachings in Hattori to utilize the known and available materials and to expand the economic base of the semiconductor substrate.
5. Claims 2 and 12 are rejected under 35 U.S.C. §103 as being unpatentable over Coombe U.S. Patent 5,382,457 (the ‘457 reference) in view of Matsuda et al. U.S. Patent Application Publication 2004/0187914.
Referring to claims 2 and 12, the ‘457 reference discloses a semiconductor substrate and a method of manufacturing a semiconductor structure as detailed above for claims 1 and 13 including a substrate (102), a semiconductor layer disposed on an upper portion of the substrate, and a thin film deposition apparatus (Fig. 1, col. 3, lines 20+) comprising a thin film deposition device for growing the semiconductor layer. The ‘457 reference further discloses that the substate is a glass substrate (fused silica, col. 7, lines 5-10), but does not disclose that the semiconductor layer is a nitride semiconductor layer having a single crystal plane.
Matsuda - in disclosing a semiconductor substrate and a method of manufacturing a semiconductor structure including a substrate (para [99]), a semiconductor layer disposed on an upper portion of the substrate, and a thin film deposition apparatus comprising a thin film deposition device (sputtering unit, para [101]) for growing the semiconductor layer, teaches that the semiconductor layer comprises a nitride semiconductor layer having a single crystal plane (single-crystalline GaN, para [83]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s semiconductor layer utilizing a nitride semiconductor layer having a single crystal plane. One would have been motivated to make such a modification in view of the teachings in Matsuda to utilize the known and available material for expanding the economic base of the semiconductor substrate.
Thus, such a modification would have resulted in:
referring to claim 2, a semiconductor substrate wherein the substrate (102) is a glass substrate (fused silica, col. 7, lines 5-10), the semiconductor layer would have been a nitride semiconductor layer having a single crystal plane;
and
referring to claim 12, a semiconductor thin film deposition apparatus, comprising:
a thin film deposition device (Fig. 1, col. 3, lines 20+) for growing a nitride semiconductor layer having a single crystal plane (as taught by Matsuda) on an upper portion of a substrate (102) through sputtering; and
an energy supplier (124) for supplying additional energy to the substrate comprising laser light (col. 4, lines 11-15), meeting the claim limitation “at least one selected from the group consisting of an electron beam, laser light, and LED light”, wherein the energy supplier (laser light) supplies the additional energy to the substrate while the thin film deposition device grows the nitride semiconductor layer on an upper portion of the substrate (col. 4, lines 56+/- “…they remain illuminated by laser beam 126…”).
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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09-01-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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