Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant is advised that should claim 15 be found allowable, claim 16 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 7-8, 11-14, and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al., US 2018/0261668.
Yang et al. shows the invention as claimed including a nanostructure comprising a pair of nanosheet field effect transistors configured to conduct charge by charge carriers of opposite polarity (region I is an NMOS region and region II is a PMOS region---see paragraph 0122), each transistor comprising a respective channel, gate, source, and drain, each channel (130/330) comprising a respective gate dielectric (121,122,321,322) and gate electrode (120,320), and each source and each drain (150/350---see paragraph 0123) comprising respective volumes of semiconductor material located on either side of the one or more sheets, wherein the first transistor of the pair of transistors comprises: one or more dielectric inner spacers 142 between the gate electrode of the first transistor and the source of the first transistor, and one or more dielectric inner spacers 142 between the gate electrode of the first transistor and the drain of the first transistor, and the second transistor of the pair of transistors comprises no dielectric inner spacers between the gate electrode of the second transistor and the source or drain of the second transistor (see, for example, paragraph 0124 and for entire structure see paragraphs 0120-0125).
Regarding dependent claims 2 and 13, note that Yang et al. discloses wherein the channel of one of the pair of transistors comprises multiple sheets stacked one on top of each other (see, for example, fig. 2).
As to dependent claims 3 and 14, note that Yang et al. discloses wherein the pair of transistors are complementary NMOS and PMOS transistors, wherein the channels of the pair of transistors are formed of silicon, wherein the first transistor is the NMOS transistor, and wherein the second transistor is the PMOS transistor (see paragraphs 0041, 0045, 0122, and 0124).
Regarding dependent claim 5, note that Yang et al. discloses wherein a SiGe layer is provided underneath the second transistor, for example (see paragraphs 0027).
As to dependent claims 7 and 17, Yang et al. discloses wherein the first transistor further comprises a bottom isolation layer 143 underneath at least the source and drain of the first transistor and is not provided underneath the second transistor (see fig. 20).
Concerning dependent claims 8 and 18, note that in Yang et al. the first and second transistors are formed side by side on a semiconductor substrate (see fig. 19).
With respect to dependent claim 11, Yang et al. discloses wherein a length of the channel sheets of the second transistor, in a direction from the source to the drain of the second transistor, is the same as a length of the gate electrode of the second transistor (see fig. 20 and its description).
As to independent claim 12, Yang et al. shows the invention as claimed including an integrated circuit chip comprising:
A nanostructure comprising a pair of nanosheet field effect transistors configured to conduct charge by charge carriers of opposite polarity (region I is an NMOS region and region II is a PMOS region---see paragraph 0122), each transistor comprising a respective channel, gate, source, and drain, each channel (130/330) comprising a respective one or more elongate sheets of semiconductor material, each gate comprising a respective gate dielectric (121,122,321,322) and a respective gate electrode (120,320), and each source and each drain comprising respective volumes of semiconductor material located on either side of the one or more sheets, wherein the first transistor of the pair of transistors comprises:
One or more dielectric inner spacers 142 between the gate electrode of the first transistor and the source of the first transistor, and one or more dielectric inner spacers 142 between the gate electrode of the first transistor and the drain of the first transistor; and
The second transistor of the pair of transistors comprises no dielectric inner spacers between the gate electrode of the second transistor and the source or drain of the second transistor (see, for example, paragraph 0124 and for entire structure see paragraphs 0120-0125).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4, 15-16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al., US 2018/0261668 in view of Wang et al., 2021/098605.
Yang et al. is applied as above but does not expressly disclose wherein the channels of the pair of transistors are formed of germanium. Wang et al. discloses the formation of nanostructures that have germanium channels (see paragraphs 0019, 0025, 0030, and 0033). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Yang et al. so as to form germanium channels in the pair of transistors because Wang et al. discloses germanium channels to be suitable for nanodevices.
Regarding dependent claim 20, note that Yang et al. discloses wherein a SiGe layer is provided underneath the second transistor, for example (see paragraphs 0027).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al., US 2018/0261668 in view of Young et al., US 2021/0035870.
Yang et al. is applied as above but does not expressly disclose wherein the SiGe layer comprises dopant elements configured to reduce a leakage current from the source to the drain of the second transistor. Young et al. discloses the use of dopant elements which will reduce a leakage current from the source to the drain of a transistor (see paragraph 0018). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Yang et al. so as to comprise the claimed dopant elements because Young et al. shows that this is a conventional configuration for a field effect based device in order to produce improved properties.
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al., US 2018/0261668 in view of Zhang et al., US 2021/0210486.
Yang et al. is applied as above but does not expressly disclose wherein the first and second transistors are formed as a forksheet structure that comprises a dielectric wall that separates the transistors. Zhang et al. discloses wherein first and second transistors are formed as a forksheet structure that comprises a dielectric wall that separates the transistors (see figs. 6 and 16-17 and paragraph 0038). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Yang et al. so as to comprise the claimed forksheet structure because in such a way a reduction of the logic cell size can be achieved.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al., US 2018/0261668 in view of Frougier et al., U.S. Patent 10,256,158.
Yang et al. is applied as above but does not expressly disclose wherein the second transistor is formed on top of the first transistor. Frougier et al. discloses a stacked transistor configuration where a second transistor is formed on top of a first transistor (see fig. 1). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Yang et al. so as to comprise the claimed stacked transistor configuration as Frougier et al. shows this to be a suitable alternative transistor configuration and because in such a way the surface area taken up on the chip will be reduced thereby improving integration.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent 12,745,440 discloses a three-dimensional device with nanosheets (see, for example, fig. 1B), and US Patent 12,745,452 also discloses a nanosheet device with an overlying gate electrode (see fig. 5A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/Primary Examiner, Art Unit 2812
September 19, 2026
