Prosecution Insights
Last updated: July 17, 2026
Application No. 18/689,015

CACHE STATUS RECORDING METHOD, DATA ACCESS METHOD AND RELATED APPARATUSES AND DEVICES

Final Rejection §103
Filed
Mar 04, 2024
Priority
Dec 13, 2022 — CN 202211593112.3 +1 more
Examiner
FAAL, BABOUCARR
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Chengdu Haiguang Integrated Circuit Design Co. Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
432 granted / 537 resolved
+25.4% vs TC avg
Moderate +14% lift
Without
With
+14.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
23 currently pending
Career history
570
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
75.3%
+35.3% vs TC avg
§102
15.3%
-24.7% vs TC avg
§112
2.8%
-37.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 537 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-5, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsien et al. 20190196574 herein Tsien in view of Mittal et al 20220100523 herein Mittal. Per claim 1, Tsien discloses: A cache status recording method, wherein the method is applied to a probe filter, wherein a host cache record table is configured in the probe filter, (¶0031; In an embodiment, communication fabric 120 maintains probe filter 113. In various embodiments, probe filter 113 is implemented as a directory with multiple entries) the host cache record table is used for recording a status of cache data of a host in a host cache and a peripheral sharing identifier corresponding to the cache data, the peripheral sharing identifier is used for indicating whether the cache data is shared by a peripheral device, (¶0031; The entries of probe filter 113 contain information indicating the existence of cached copies of data. In some embodiments, each entry stores a valid bit, a tag of a cache line, an indication that specifies a cache coherency state of the cache line, a node ownership identifier (ID), one or more node IDs of remote nodes with remote clients storing a cached copy of data in local system memory, a clean/dirty state, and so forth. In some embodiments, the cache coherency states are modified, owned, exclusive, shared, and invalid). Tsien discloses a probe filter recording the status of data stored in the cache but does not specifically disclose: and the method comprises: when the peripheral device shares the cache data in the host cache, updating the peripheral sharing identifier such that the peripheral sharing identifier indicates a corresponding cache data is shared by the peripheral device; and when a processor core exclusively owns the cache data, updating the peripheral sharing identifier such that the peripheral sharing identifier indicates that the corresponding cache data is not shared by the peripheral device. However, Mittal discloses: and the method comprises: when the peripheral device shares the cache data in the host cache, updating the peripheral sharing identifier such that the peripheral sharing identifier indicates a corresponding cache data is shared by the peripheral device; and when a processor core exclusively owns the cache data, updating the peripheral sharing identifier such that the peripheral sharing identifier indicates that the corresponding cache data is not shared by the peripheral device (fig. 2, ¶0022-0023; In another state, the CSA 135 functions as a local HA but in a shared state. In this state, the CSA 135 and the host HA 115 may share ownership of the data. That is, the CSA 135 and the host HA 115 may both track the data. An example of this state is where both the RA 110 in the host 105 and the RA 140 in the I/O device 130 have requested the data. In a third state, the CSA 135 owns the data as a local HA while the host HA 115 does not (referred to as an exclusive state). In one embodiment, the host HA 115 does not have any record that the data is owned by the CSA 135. Put differently, the host HA 115 may not track that it has transferred ownership data to the CSA 135.). It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Tsien and Mittal’s cache coherent system to ensure coherent view of accessed, modified and cached data. Mittal tracking reduces overhead in the host. (¶0040; the host HA updates the tracked data list to stop tracking the data in both the host RA and the I/O device RA, thereby reducing the overhead in the host HA.). The examiner notes that the new amendment of “when the peripheral device exclusively owns the caching data, deleting a status entry corresponding to the cache data in the host cache record table” from the peripheral device sharing the cache data. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires “updating the peripheral sharing identifier, when the caching data is shared” or “deleting a status entry in the host table, when the peripheral device exclusively owns the caching data.” If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. The broadest reasonable interpretation requires teaching at least one of the three contingent limitation two of which have been addressed. Mittal discloses sharing the caching data and updating the sharing identifier. When analyzing the claimed method as a whole, the PTAB determined that giving the claim its broadest reasonable interpretation, "[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" Per claim 2, Mittal discloses: wherein when the peripheral device exclusively owns the cache data, the method further comprises: deleting a status entry corresponding to the cache data in the host cache record table (fig. 2, ¶0023; In a third state, the CSA 135 owns the data as a local HA while the host HA 115 does not (referred to as an exclusive state). ¶0028; If the CSA is to own the data in the exclusive state, the method 200 proceeds to block 220 where the host HA invalidates any cached copies of the data in the host. In one embodiment, the host HA issues a flush CMO to remove the cached copies. Further, although not shown in the method 200, when flush and invalidating the cached copies of the data in the host, the host HA can also remove the data from its tracked data list since the local HA (i.e., the CSA) will own the data in the exclusive state. Thus, the host HA no longer has to track the data). Per claim 3, Mittal discloses: wherein when the peripheral device exclusively owns the cache data, the method further comprises: sending a device cache information updating request to update device cache information in a memory, such that the device cache information indicates that corresponding data in the memory is cached by the peripheral device as exclusive (fig. 2, ¶0028; If theCSA is to own the data in the exclusive state, the method 200 proceeds to block 220 where the host HA invalidates any cached copies of the data in the host. In one embodiment, the host HA issues a flush CMO to remove the cached copies. Further, although not shown in the method 200, when flush and invalidating the cached copies of the data in the host, the host HA can also remove the data from its tracked data list since the local HA (i.e., the CSA) will own the data in the exclusive state. Thus, the host HA no longer has to track the data). Per claim 4, Mittal discloses: wherein when the processor core exclusively owns the cache data, the method further comprises: updating a status of the cache data in the host cache in the host cache record table, such that the status of the cache data in the host cache record table indicates that the cache data is exclusively owned by the processor core (fig. 2, ¶0022; In a first state, the CSA 135 does not track or own the data. For example, the I/O device 130 may be used by the host 105 as an expansion memory where data is stored in memory on the I/O device 130, but the I/O device 130 does not process the data (e.g., the accelerator function may not be operating on the data). This can be referred to as an invalid state since the CSA 135 does not serve as a local HA for the data). Per claim 5, Mittal discloses: wherein when the processor core exclusively owns the cache data, and the host cache record table does not comprise a status of cache data which is to be accessed, the method further comprises: sending a device cache information updating request to a memory controller to update a device cache information in a memory, such that the device cache information indicates that corresponding data in the memory is cached by the peripheral device as invalid (fig. 3, ¶0033; The method 300 assumes that the CSA has transitioned to a local HA in either the shared or exclusive state as described in the method 200 in FIG. 2. When the GSA owns the data (either partially or exclusively), the host HA receives a request from an RA in the host to modify the data. Before permitting an RA on the host to edit the data, the host HA must again have exclusive ownership of the data). Per claim 18, Tsien discloses: A cache status recording apparatus which is applied to a probe filter, wherein a host cache record table is configured in the probe filter, (¶0031; In an embodiment, communication fabric 120 maintains probe filter 113. In various embodiments, probe filter 113 is implemented as a directory with multiple entries) the host cache record table is used for recording a status of cache data of a host in a host cache and a peripheral sharing identifier corresponding to the cache data, the peripheral sharing identifier is used for indicating whether the cache data is shared by a peripheral device, (¶0031; The entries of probe filter 113 contain information indicating the existence of cached copies of data. In some embodiments, each entry stores a valid bit, a tag of a cache line, an indication that specifies a cache coherency state of the cache line, a node ownership identifier (ID), one or more node IDs of remote nodes with remote clients storing a cached copy of data in local system memory, a clean/dirty state, and so forth. In some embodiments, the cache coherency states are modified, owned, exclusive, shared, and invalid). Tsien discloses a probe filter recording the status of data stored in the cache but does not specifically disclose: and the cache status recording apparatus is configured to perform the cache status recording method according to claim 1, wherein the cache status recording apparatus comprises: an identifier updating module configured to: when the peripheral device shares the cache data in the host cache, update the peripheral sharing identifier such that the corresponding cache data indicated by the peripheral sharing identifier is shared by the peripheral device; and when a processor core exclusively owns the cache data, update the peripheral sharing identifier, such that the peripheral sharing identifier indicates that the corresponding cache data is not shared by the peripheral device. However, Mittal discloses: and the cache status recording apparatus is configured to perform the cache status recording method according to claim 1, wherein the cache status recording apparatus comprises: (the examiner notes the 112 rejection supra regarding the incorporation of claim 1 into claim 18) an identifier updating module configured to: when the peripheral device shares the cache data in the host cache, update the peripheral sharing identifier such that the corresponding cache data indicated by the peripheral sharing identifier is shared by the peripheral device; and when a processor core exclusively owns the cache data, update the peripheral sharing identifier, such that the peripheral sharing identifier indicates that the corresponding cache data is not shared by the peripheral device (fig. 2, ¶0022-0023; In another state, the CSA 135 functions as a local HA but in a shared state. In this state, the CSA 135 and the host HA 115 may share ownership of the data. That is, the CSA 135 and the host HA 115 may both track the data. An example of this state is where both the RA 110 in the host 105 and the RA 140 in the I/O device 130 have requested the data. In a third state, the CSA 135 owns the data as a local HA while the host HA 115 does not (referred to as an exclusive state). In one embodiment, the host HA 115 does not have any record that the data is owned by the CSA 135. Put differently, the host HA 115 may not track that it has transferred ownership data to the CSA 135.). The examiner notes that the new amendment of “when the peripheral device exclusively owns the caching data, deleting a status entry corresponding to the cache data in the host cache record table” from the peripheral device sharing the cache data. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires “updating the peripheral sharing identifier, when the caching data is shared” or “deleting a status entry in the host table, when the peripheral device exclusively owns the caching data.” If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. The broadest reasonable interpretation requires teaching at least one of the three contingent limitation two of which have been addressed. When analyzing the claimed method as a whole, the PTAB determined that giving the claim its broadest reasonable interpretation, "[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" Mittal discloses sharing the caching data and updating the sharing identifier. Claim 20 is the storage medium having executable instruction claim corresponding to the method claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1. Response to Arguments Applicant's arguments filed 2/6/26 have been fully considered but they are not persuasive. The applicant argues: The cited references, either alone or combined, do not teach or suggest at least the distinct features of "when the peripheral device exclusively owns the cache data, deleting a status entry corresponding to the cache data in the host cache record table" as recited in amended claim 1. The examiner notes that the new amendment of “when the peripheral device exclusively owns the caching data, deleting a status entry corresponding to the cache data in the host cache record table” from the peripheral device sharing the cache data. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires “updating the peripheral sharing identifier, when the caching data is shared” or “deleting a status entry in the host table, when the peripheral device exclusively owns the caching data.” If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. The broadest reasonable interpretation requires teaching at least one of the three contingent limitation two of which have been addressed. Mittal discloses sharing the caching data and updating the sharing identifier. When analyzing the claimed method as a whole, the PTAB determined that giving the claim its broadest reasonable interpretation, "[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" Remark Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim VO can be reached at 5712723642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BABOUCARR . FAAL Primary Examiner Art Unit 2138 /BABOUCARR FAAL/Primary Examiner, Art Unit 2138
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Prosecution Timeline

Mar 04, 2024
Application Filed
Dec 19, 2025
Non-Final Rejection mailed — §103
Feb 04, 2026
Response Filed
Jun 30, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
95%
With Interview (+14.5%)
2y 10m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 537 resolved cases by this examiner. Grant probability derived from career allowance rate.

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