DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on 3/26/2026. These drawings are accepted by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Balsara et al. (US 6,130,559).
In regards to claim 1, Balsara discloses of a logic gate circuit, comprising: a) a logic block (comprised of 700, 710, 720 in Fig 7A or 800, 810, 820 in Fig 8A) for performing logic operations between inputs of said logic block; and b) a restoration block (for example comprised of 740, 750, 760, 770 in Fig 7A or comprised of 840, 850, 860, 870 in Fig 8A), connected between the output of said logic block and the output of said logic gate (see Figs 7A, 8A), for compensating for voltage level losses when said output is in a high logic state, wherein said logic block discharges a voltage node that corresponds to said high logic state to ground, following logic operations that entail a low logic state, via an inherent current leakage path in the components implementing said logic block (see Figs 7A, 8A); wherein the logic block and the restoration block comprise transistors operable respectively at multiple threshold voltages (see Figs 7A, 8A, each showing different channel widths for the transistors of the logic blocks and restoration blocks, the different channel widths result in different/multiple threshold voltages for the transistors).
In regards to claim 2, Balsara discloses of a logic gate according to claim 1, further comprising a pull-down block (see 730, 780, 790 in Fig 7A, 830 in Fig 8A) connected between said logic block and the output of said logic gate (see Figs 7A, 8A), for further discharging the voltage that corresponds to said high logic state to ground, following logic operations that entail a low logic state, in addition to discharging via the inherent current leakage path (see Figs 7A, 8A).
In regards to claim 3, Balsara discloses of a logic gate according to claim 1, in which the restoration block consists of:- a standard CMOS inverter; - a standard CMOS buffer; - a combination thereof (see Figs 7A, 8A, illustrated two separate inverters comprised of 740, 750, 840, 850 and 760, 770, 860, 870, respectively in Figs 7A and 8A that may be combined to be a buffer).
In regards to claim 4, Balsara discloses of a logic gate according to claim 1, in which the pull-down block is a diode (see Figs 7A, 8A, 730, 780, 790 and 830 are all examples of diodes).
In regards to claim 5, Balsara discloses of a logic gate according to claim 1, comprising a pull-down block being implemented with an element selected from a group comprising: - a diode (e.g. a junction diode); - a transistor configured to operate as a diode; - a plurality of transistors configured to operate as a diode; - a combination of PMOS and NMOS transistors that acts as a diode (see Figs 7A, 8A, 730, 780, 790 and 830 all exhibit examples of the listed diodes).
In regards to claim 6, Balsara discloses of a logic gate according to claim 1, in which the logic block is a stack of connected transistors, implementing an AND, OR, NOR, NAND gate, or a parallel connection of transistors implementing an AND gate, or a combination thereof (see Fig 7A and Column 6 Lines 57-60, parallel connected transistors 700, 710, 720 implement a 2-input NAND gate) .
In regards to claim 7, Balsara discloses of a logic gate according to claim 6, further comprising: a) a voltage source (Vdd) being connected to the source or drain of a first transistor of the stack (see 700, 710, 720 in Fig 7A); and b) multiple voltage sources (Vin1, Vin2) being connected as inputs to the gates of the transistors of said stack (see Fig 7A).
In regards to claim 8, Balsara discloses of a logic gate according to claim 6, in which the logic block comprises one or more CMOS circuits (for example see CMOS inverter comprised of 740, 750) in combination with a stack of transistors (see Fig 7A).
In regards to claim 9, Balsara discloses of a logic gate according to claim 1, operating in combination with similar logic gates, thereby forming a logic circuit (see Figs 7A, 8A).
In regards to claim 10, Balsara discloses of a logic gate according to claim 1, implemented as an integrated circuit in combination with CMOS gates (see Figs 7A, 8A, see CMOS inverters comprised of 740, 750, 760, 770, 840, 850, 860, 870, also see Fig 6A).
In regards to claim 11, Balsara discloses of a logic gate according to claim 1, in which the body of one or more transistors implementing the logic block is connected to the ground (see Fig 1, exemplary NMOS transistor with a body 30 tied to ground Vss).
In regards to claim 12, Balsara discloses of a logic gate according to claim 1, in which multiple threshold voltages are applied to transistors implementing each block (see Figs 7A, 8A).
In regards to claim 13, Balsara discloses of a logic gate according to claim 1, in which multiple power supply voltages are used (see Figs 4A, 5A, 6A, 7A, 8A, multiple connections to Vdd shown) .
In regards to claim 14, Balsara discloses of a logic gate according to claim 1, in which the supply voltage (Vdd) is applied to the drain or source of at least one transistor implementing the logic block (see Figs 7A, 8A, applied to 700, 710, 720 and 800, 810, 820 in Figs 7A, 8A, respectively).
In regards to claim 15, Balsara discloses of a logic gate according to claim 7, in which the supply voltage is applied to the gate of at least one transistor implementing the logic block (see Figs 7A, 8A and Column 7 Lines 10-13, 49-52, on a logic high, the voltage on Vin1, V-in2 equal to the supply voltage Vdd value of 2 volts) .
In regards to claim 16, Balsara discloses of a logic gate according to claim 1, implementing a multiple-input AND gate with no load and no PMOS transistors (see Fig 7A, transistors 700, 710, 720 implement a 2-input AND gate).
In regards to claim 17, Balsara discloses of a logic gate according to claim 1, in which the parasitic leakage current at the source of one or more transistors in the logic block serves as a pull-down circuitry (see Figs 7A, 8A, the transistors have an internal parasitic leakage current at their sources).
In regards to claim 19, Balsara discloses of a logic gate according to claim 1, further comprising a circuit for sharing a pull-down diode circuit and/or a signal restoration CMOS buffer between several stacked-NMOS gates, or NMOS gates connected in parallel, or a combination thereof (see Figs 7A, 8A).
In regards to claim 20, Balsara discloses of a logic gate according to claim 1, further comprising several stacked-PMOS gates, or PMOS gates connected in parallel, or a combination thereof (see Fig 3, exemplary alternative of a logic gate with stacked PMOS gates).
In regards to claim 21, Balsara discloses of a logic gate according to claim 1, further comprising several stacked-NMOS and stacked-PMOS gates, or NMOS gates connected in parallel, PMOS gates connected in parallel, or a combination thereof (see Figs 7A, 8A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Balsara et al. (US 6,130,559) in view of Oh (US 2007/0075743).
In regards to claim 18, Balsara discloses of a logic gate according to claim 17 as found within the explanation above.
However, Balsara does not explicitly disclose of the logic gate further comprising a feedback path from the input or the output of the restoration block, to control the operation of the pull-down circuit.
Oh discloses of a logic gate circuit, comprising: a) a logic block (200, 210 see Figs 2A-B) for performing logic operations between inputs of said logic block; and b) a restoration block (204, 230), connected between the output of said logic block and the output of said logic gate (see Figs 2A-B), for compensating for voltage level losses when said output being in a high logic state, wherein said logic block discharges the voltage that corresponds to said high logic state to ground, following logic operations that entail a low logic state, via an inherent current leakage path in the components implementing said logic block (see Figs 2A-B); and wherein the logic gate further comprises a feedback path from the input or output of the restoration block (204, 230) to control operation of a pull-down circuit (202, see Fig 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have a feedback path from a restoration block to control a pull-down circuit of a logic gate as taught by Oh for providing a more efficient logic gate circuit with lower power consumption.
Response to Arguments
Applicant's arguments filed 3/26/2026 have been fully considered but they are not persuasive. The Applicant argues the prior art fails to disclose of the transistors of the logic and restoration blocks are operable at multiple threshold voltages, however, the Examiner respectfully disagrees. Figs 7A and 8A each show different channel widths for the respective transistors of the logic and restoration blocks, these different channel widths result in different/multiple threshold voltages for the transistors as now claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Fri 6:00am-3:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844
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