DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/03/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is being considered by the examiner.
Response to Amendments
This Office Action is in response to applicant's preliminary amendments filed on 03/06/2024. Examiner has acknowledged and reviewed applicant's cancellation of claims 21 – 26. Examiner has reviewed presently presented claims 1 - 20, and claims 1 - 20 do not constitute new matter issues.
Reasons for Allowance
The following is an examiner's statement of reasons for allowance.
The primary reason for allowance of claims 11 - 17 is the prior art made of record neither shows or discloses the claim language found in claim 11, for a pressure sensor, comprising:
a first base substrate;
a pressure sensing layer on the first base substrate.
Most notably, for a pressure sensor, further comprising:
a releasing via (Vertical Interconnect Access) extending through the pressure sensing layer;
a sealing layer on a side of the pressure sensing layer away from the first base substrate, the sealing layer sealing the releasing via; and
a pressure reference chamber between the first base substrate and the pressure sensing layer
in combination with all of the other claim limitations presented, in total.
The primary reason for allowance of claims 18 - 20 is the prior art made of record neither shows or discloses the claim language found in claim 18, for a method of forming a pressure sensor, comprising forming a pressure sensing layer on a first base substrate.
Most notably, for a method of forming a pressure sensor, further comprising:
forming a releasing via (Vertical Interconnect Access) extending through the pressure sensing layer;
forming a sealing layer on a side of the pressure sensing layer away from the first base substrate, the sealing layer sealing the releasing via; and
forming a pressure reference chamber between the first base substrate and the pressure sensing layer,
in combination with all of the other claim limitations presented, in total.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 - 4, 6 – 9, 12, 13 of copending Application No. 18/699,668 (reference application), in view of Ahles et al. (US 9082831 B2), hereafter referred to as “Ahles”. Although the claims at issue are not identical, they are not patentably distinct from each other because the table below presents a comparison between the claim limitations of the instant application with corresponding claim limitations of the reference U. S. application. The bold-faced type identifies claim limitation language which is common to both the instant application and the reference U. S. application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Application No. 18/699,668
Instant Claim
A sensor chip, comprising:
a first base substrate;
a piezoresistor on the first base substrate;
a second base substrate on a side of the piezoresistor away from the first base substrate;
a metal wire bond extending through the second base substrate; and
a pressure reference chamber between the first base substrate and the second base substrate;
wherein the first base substrate and the second base substrate encapsulate at least a portion of the piezoresistor inside the pressure reference chamber.
1. (Original) A sensor chip, comprising:
a first base substrate;
a piezoresistor and a resistor lead on the first base substrate;
a second base substrate on a side of the piezoresistor and the resistor lead away from the first base substrate;
a metal wire bond extending through the second base substrate and connected to the resistor lead;
a redistribution layer on a side of the second base substrate away from the first base substrate; and
a pressure reference chamber between the first base substrate and the second base substrate;
wherein the first base substrate and the second base substrate encapsulate at least a portion of the piezoresistor inside the pressure reference chamber;
the metal wire bond is connected to the resistor lead, and is connected to the redistribution layer; and
the resistor lead is connected to the piezoresistor.
The sensor chip of claim 1, further comprising a redistribution layer on a side of the second base substrate away from the first base substrate;
wherein the redistribution layer is connected to the metal wire bond.
1. (Original) A sensor chip, comprising:
a first base substrate;
a piezoresistor and a resistor lead on the first base substrate;
a second base substrate on a side of the piezoresistor and the resistor lead away from the first base substrate;
a metal wire bond extending through the second base substrate and connected to the resistor lead;
a redistribution layer on a side of the second base substrate away from the first base substrate; and
a pressure reference chamber between the first base substrate and the second base substrate;
wherein the first base substrate and the second base substrate encapsulate at least a portion of the piezoresistor inside the pressure reference chamber;
the metal wire bond is connected to the resistor lead, and is connected to the redistribution layer; and
the resistor lead is connected to the piezoresistor.
The sensor chip of claim 1, further comprising a resistor lead on the first base substrate;
wherein the resistor lead is connected to the piezoresistor, and is connected to the metal wire bond.
1. (Original) A sensor chip, comprising:
a first base substrate;
a piezoresistor and a resistor lead on the first base substrate;
a second base substrate on a side of the piezoresistor and the resistor lead away from the first base substrate;
a metal wire bond extending through the second base substrate and connected to the resistor lead;
a redistribution layer on a side of the second base substrate away from the first base substrate; and
a pressure reference chamber between the first base substrate and the second base substrate;
wherein the first base substrate and the second base substrate encapsulate at least a portion of the piezoresistor inside the pressure reference chamber;
the metal wire bond is connected to the resistor lead, and is connected to the redistribution layer; and
the resistor lead is connected to the piezoresistor.
4. The sensor chip of claim 1, further comprising an under bump metallization on a side of the second base substrate away from the first base substrate; and
a solder on a side of the under bump metallization away from the second base substrate and connected to the under bump metallization.
2. (Original) The sensor chip of claim 1, further comprising an under bump metallization on a side of the second base substrate away from the first base substrate; and
a solder on a side of the under bump metallization away from the second base substrate and connected to the under bump metallization.
6. The sensor chip of claim 5, wherein the via has a trapezoidal shape with an included angle between a top side and a lateral side; and
the included angle is in a range of 80 degrees to 90 degrees.
3. (Original) The sensor chip of claim 1, comprising a via extending through the second base substrate;
wherein the metal wire bond is at least partially in the via;
the via has a trapezoidal shape with an included angle between a top side and a lateral side; and
the included angle is in a range of 80 degrees to 90 degrees.
7. The sensor chip of claim 1, comprising a pressure sensing layer configured to convert a pressure signal into a deformation signal;
wherein the pressure sensing layer comprises a portion of the first base substrate between the two piezoresistors; and
the piezoresistor is configured to convert the deformation signal into an electrical signal.
4. (Currently Amended) The sensor chip of claim 1, comprising a pressure sensing layer configured to convert a pressure signal into a deformation signal;
wherein the pressure sensing layer comprises a portion of the first base substrate between the two piezoresistors; and
the piezoresistor is configured to convert the deformation signal into an electrical signal.
8. The sensor chip of claim 7, wherein a surface of the portion of the first base substrate between the two piezoresistors is exposed to the pressure reference chamber.
5. (Original) The sensor chip of claim 4, wherein a surface of the portion of the first base substrate between the two piezoresistors is exposed to the pressure reference chamber.
9. The sensor chip of claim 1, further comprising an insulating layer on the first base substrate;
wherein the piezoresistor is on a side of the insulating layer away from the first base substrate;
the pressure reference chamber is between the insulating layer and the second base substrate; and
the insulating layer and the second base substrate encapsulate at least a portion of the piezoresistor inside the pressure reference chamber.
6. (Currently Amended) The sensor chip of claim1, further comprising an insulating layer on the first base substrate;
wherein the piezoresistor and the resistor lead are on a side of the insulating layer away from the first base substrate;
the pressure reference chamber is between the insulating layer and the second base substrate; and
the insulating layer and the second base substrate encapsulate at least a portion of the piezoresistor inside the pressure reference chamber.
7. The sensor chip of claim 1, comprising a pressure sensing layer configured to convert a pressure signal into a deformation signal;
wherein the pressure sensing layer comprises a portion of the first base substrate between the two piezoresistors; and
the piezoresistor is configured to convert the deformation signal into an electrical signal.
7. (Original) The sensor chip of claim 6, comprising a pressure sensing layer configured to convert a pressure signal into a deformation signal;
wherein the pressure sensing layer comprises a portion of the first base substrate and a portion of the insulating layer between two piezoresistors; and
the piezoresistor is configured to convert the deformation signal into an electrical signal.
8. The sensor chip of claim 7, wherein a surface of the portion of the first base substrate between the two piezoresistors is exposed to the pressure reference chamber.
8. (Original) The sensor chip of claim 7, wherein a surface of the portion of the insulating layer between the two piezoresistors is exposed to the pressure reference chamber.
12. The sensor chip of claim 1, further comprising a thermistor on a side of the second base substrate away from the first base substrate.
9. (Currently Amended) The sensor chip of claim 1, further comprising a thermistor on a side of the second base substrate away from the first base substrate.
13. The sensor chip of claim 1, further comprising a hygrometer on a side of the second base substrate away from the first base substrate.
10. (Currently Amended) The sensor chip of claim 1, further comprising a hygrometer on a side of the second base substrate away from the first base substrate.
Regarding to claim 1, reference application Wang et al. (US 20250237566 A1) application no.18/699,6680 do not disclose a sensor chip comprising:
a metal wire bond extending through the second base substrate and connected to the resistor lead;
a redistribution layer on a side of the second base substrate away from the first base substrate;
the metal wire bond is connected to the resistor lead, and is connected to the redistribution layer; and
the resistor lead is connected to the piezoresistor.
However, regarding claim 1, Ahles teach an insulation layer between two
component layers, and a via (Vertical Interconnect Access) (column 1, lines 9 – 16) that provides an electrical conduction path between the two component layers (column 1, lines 42 - 60); and a bond wire connecting with a via (column 7 lines 62 – 6,7 and column 8 lines 1 - 4).
It would have been obvious to one of ordinary skill in the art at the time the applicant filed for the invention, that a sensor chip comprising a combination of features as disclosed by Wang et al. (as presented in claim 1), for the Wang et al. sensor chip can be modified to implement vias and a bond wire as taught by Ahles (as presented in paragraph 13, above), to enhance structural integrity of an electronic component circuit board.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WARREN K FENWICK whose telephone number is (571)270-3040. The examiner can normally be reached 10:30 AM to 7:00 PM, Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Walter L. Lindsay, Jr. can be reached at 571-272-1674. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WALTER L LINDSAY JR/Supervisory Patent Examiner, Art Unit 2852
WKF
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