DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202111040191, filed on 09/06/2021.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 03/06/2024 and 06/18/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Examiner Note
Claim 1 details a master test structure and a test structure consisting of a first MOS device and a second MOS device. Examiner suggests for the first use of the acronym MOS to fully specify it’s meaning as a Metal-Oxide-Semiconductor. Examiner suggests further formatting Claim 1 as the multiple MOS devices are detailed consisting of similar structural features (gate, drain, source, body), so that it is clear when reference to a specific structure that both devices has, it is clear and concise the that the structure is associated with the specific device. Examiner details the following as an example of the formatting of Claim 1 with the above suggestions and spacing:
A measurement system for a radio frequency MOS (Metal-Oxide-Semiconductor) device modeling, comprising: a master test structure and a slave test structure;
wherein the master test structure and the slave test structure use two ports for testing;
wherein the master test structure comprises:
a first MOS device, wherein a gate of the first MOS device and a drain of the first MOS device are respectively connected to the two test ports of the master test structure, and a source of the first MOS device and a body of the first MOS device are short circuited and grounded;
wherein the slave test structure comprises:
a second MOS device, wherein a source of the second MOS device and a drain of the second MOS device are respectively connected to test ports of the slave test structure, a gate of the second MOS device is independently connected out to facilitate setting a corresponding bias voltage, and a body of the second MOS device is grounded.
Examiner notes the following prior art not utilized in in the 35 U.S.C. 103 rejection is of interest to the invention:
Liu (CN111914505A) details a modeling method of an MOS device, and the method comprises the following steps: S01, constructing a model circuit of the MOS device, wherein the model circuit comprises an intrinsic transistor, a substrate parasitic resistor, a parasitic capacitor, a parasitic diode, a grid parasitic resistor inductance network, a source parasitic resistor inductance network and a drain parasitic resistor inductance network; S02, determining models and size parameters of an intrinsic transistor and a parasitic diode in the model circuit; S03, respectively determining parasitic element values of the source parasitic resistance inductance network and the drain parasitic resistance inductance network by adopting an electromagnetic simulation method; S04, determining parasitic element values of the substrate parasitic resistance, parasitic capacitance and grid parasitic resistance inductance network based on the test data; and S05, substituting the calculated parasitic element value into the model circuit.
Chen (CN104750922A) details a SOI four-port network and model topology structure.
Wu (Wu, Shih-Dao et. al., “RF MOSFET Characteriszation by Four-Port Measurement”, IEICE TRANS. ELECTRON., Volume E88-C, May 5, 2005; https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.5.851/_pdf) details an RF MOSFET with a four port test structure.
Claim Interpretation
Examiner notes that the claims are interpreted under broadest reasonable interpretation. The claims detail a “master test structure” and a “slave test structure”. From the usage of these terms, the interpretation of “master” and “slave” in the application is not towards a control meaning as the “master test structure” does not perform any control type actions of the “slave test structure”, but rather towards a meaning of “primary” (i.e. first) and “secondary” (i.e. second) test structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Peng (US20150168468) in view of Chen (Chen, C.H., et. al., “High Frequency Noise of MOSFETS I Modeling”, Solid State Electronics, Volume 42, Issue 11, November 1998, Pages 2069-2081) and Shen (Shen, John, et. al, “Extraction of Parasitic Inductances of SiC MOSFET Power Modules Based on Two-Port S-Parameters Measurement”, 2017, IEEE, https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8096914).
In regards to Claim 1, Peng teaches “a master test structure and a slave test structure,
both the master test structure and the slave test structure use two ports for test (Figure 2 illustrates a measurement tool 200 with connection to MOSFET 102, i.e. slave test structure, and to MOSFET 106, i.e. master test structure, with the test control device 204 with two contacts to MOSFET 102 and two contacts to MOSFET 106 – [0017]);
wherein the master test structure comprises a first MOS device, a gate and a drain of the first MOS device are respectively connected to test ports of the master test structure, a source is grounded (MOSFET 106 with the source connected to ground 114, gate 108 connected to the test control device by 212, and drain connected to the test control device 210 – [0017]);
the slave test structure comprises a second MOS device, a gate is independently connected out to facilitate setting a corresponding bias voltage (MOSFET 102 with test control device connected to gate with output line 208 to the gate 104 and output line 206 to the drain/output note 110 – [0017]).”
Peng is silent with regards to the language of “a first MOS device, a gate and a drain of the first MOS device are respectively connected to test ports of the master test structure, a source and a body are short circuited and grounded.”
Chen teaches “a first MOS device, a gate and a drain of the first MOS device are respectively connected to test ports of the master test structure, a source and a body are short circuited and grounded (“The probe pads designed in our transistor test structures were laid out in a 2-port ground-signal-ground (GSG) configuration with the source connected to ground as shown in Fig. 3. Note that the substrate is also connected to ground via metal 1 to the source. Port 1 connected to the gate of the transistor (input port) and port 2 is connected to the drain (output port). This configuration and the distance between the center of the signal pad and that of the ground pad depend on the microwave probes employed.” – Page 2074, Section 3.1).”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng to incorporate the teaching of Chen to utilize the transistor test structure with the two port configuration with the source and body to be short circuited and grounded. By utilizing a MOSFET with the test ports to the gate and drain and having the source and body being short circuited and grounded, this is an improvement that yields predictable results in the modelling and evaluation of MOSFET parameters.
Peng in view of Chen is silent with regards to the language of “a second MOS device, a source and a drain of the second MOS device are respectively connected to test ports of the slave test structure, a body of the second MOS device is grounded”
Shen teaches “a second MOS device, a source and a drain of the second MOS device are respectively connected to test ports of the slave test structure, a body of the second MOS device is grounded (Section III details a MOSFET power module with a two-port network is shown in Figure 3 where the S-G is connected as port 1 and D-G as port 2 , where Figure 3 shows gate, source, and drain contacts – Page 5476; Page 5478 details the combinations of ports and ground terminals)”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng in view of Chen to incorporate the teaching of Shen to utilize the transistor test structure with the two port configuration with ports to the source and drain. By utilizing a MOSFET with the test ports to the source and drain, this is an improvement that yields predictable results in the modelling and evaluation of MOSFET parameters.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Chen and Shen as applied to claim 1 above, and further in view of Cheng (CN107895089).
In regards to Claim 2, Peng in view of Chen and Shen discloses the claimed invention as detailed above. Peng in view of Chen and Shen are silent with regards to the language of “a first de-embedding structure and a second de-embedding structure, the first de-embedding structure corresponds to the master test structure, and the second de-embedding structure corresponds to the slave test structure.”
Cheng teaches “a first de-embedding structure and a second de-embedding structure, the first de-embedding structure corresponds to the master test structure, and the second de-embedding structure corresponds to the slave test structure (The designed integrated circuit schematic needs to be simulated to confirm that the circuit output meets the design requirements. In order to ensure that the simulation results are as consistent as possible with the actual measurement results, an accurate MOSFET transistor model must be established.
When directly measuring the IV characteristics and S parameters of a device on a wafer, the MOSFET devices on the chip are too small to be directly contacted. Therefore, a test structure must be designed to allow the measurement of its RF characteristics using a coplanar probe.
The test structure typically consists of a probe pad, a metal interconnecting line, and a device under test (DUT). The probe pad connects the test probe to the wafer under test, and the metal interconnecting line connects the DUT to the pad, as shown in Figure 1.
During measurement, the test probe contacts the pads. The electrical performance of the device under test can be measured through the probe pads and interconnects. However, the parasitic effects originating from the pads and metal interconnects can affect the test results of the device under test. Therefore, the test data obtained must be stripped of the influence of the test structure in order to obtain the true test data of the transistor. In order to eliminate the effects of parasitic effects, researchers have proposed several methods. This process of removing the parasitic effects from the pads and interconnects is called de-embedding. Currently, the most commonly used methods are open-circuit de-embedding and open-circuit short-circuit de-embedding. When using these two methods, separate open-circuit test structures and short-circuit test structures must be fabricated on the same chip next to the test device, as shown in Figures 2 and 3. This structure is exactly the same as the structure in Figure 1, except that there is no device under test or interconnect - [0004]).”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng in view of Chen and Shen to incorporate the teaching of Cheng to utilize an open test circuit and short circuit test circuit for the model to perform de-embedding to determine the S-parameter of the MOSFET. By utilizing an open test circuit and short circuit test circuit this is an improvement that yields predictable results in the determination of the S-parameter and thus determining the parasitic capacitances, resistances, and inductances.
In regards to Claim 3, Peng in view of Chen, Shen, and Cheng discloses the claimed invention as detailed above. Peng is silent with regards to the language of “wherein both the first de-embedding structure and the second de-embedding structure comprise an open circuit test substructure and a short circuit test substructure.”
Cheng further teaches “wherein both the first de-embedding structure and the second de-embedding structure comprise an open circuit test substructure and a short circuit test substructure (The designed integrated circuit schematic needs to be simulated to confirm that the circuit output meets the design requirements. In order to ensure that the simulation results are as consistent as possible with the actual measurement results, an accurate MOSFET transistor model must be established.
When directly measuring the IV characteristics and S parameters of a device on a wafer, the MOSFET devices on the chip are too small to be directly contacted. Therefore, a test structure must be designed to allow the measurement of its RF characteristics using a coplanar probe.
The test structure typically consists of a probe pad, a metal interconnecting line, and a device under test (DUT). The probe pad connects the test probe to the wafer under test, and the metal interconnecting line connects the DUT to the pad, as shown in Figure 1.
During measurement, the test probe contacts the pads. The electrical performance of the device under test can be measured through the probe pads and interconnects. However, the parasitic effects originating from the pads and metal interconnects can affect the test results of the device under test. Therefore, the test data obtained must be stripped of the influence of the test structure in order to obtain the true test data of the transistor. In order to eliminate the effects of parasitic effects, researchers have proposed several methods. This process of removing the parasitic effects from the pads and interconnects is called de-embedding. Currently, the most commonly used methods are open-circuit de-embedding and open-circuit short-circuit de-embedding. When using these two methods, separate open-circuit test structures and short-circuit test structures must be fabricated on the same chip next to the test device, as shown in Figures 2 and 3. This structure is exactly the same as the structure in Figure 1, except that there is no device under test or interconnect - [0004]).”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng in view of Chen and Shen to incorporate the teaching of Cheng to utilize an open test circuit and short circuit test circuit for the model to perform de-embedding to determine the S-parameter of the MOSFET. By utilizing an open test circuit and short circuit test circuit this is an improvement that yields predictable results in the determination of the S-parameter and thus determining the parasitic capacitances, resistances, and inductances.
Allowable Subject Matter
Claims 4-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to Claim 4, Peng in view of Chen and Shen discloses the claimed invention as detailed above.
Shen further teaches “constructing a subcircuit model, wherein the subcircuit model comprises an intrinsic MOS device and multiple parasitic elements, the intrinsic MOS device has four electrodes, which are a source, a drain, a gate and a body, respectively, and the multiple parasitic elements comprise multiple parasitic capacitances (S-parameters measured with the vector network analyzer and the Z-parameters converted according, while the parasitics can be extracted, where the MOSFET model has 9 parasitic inductances and 6 capacitances – Page 5477); performing tests and de-embedding processing on the master test structure and the slave test structure respectively, so as to obtain a de-embedded S-parameter and current- voltage data of the master test structure (two-port S-parameter measurement technique applied to MOSFETS – page 5475; vector network analyzer is a test system that enables the measurement in terms of S-parameters – page 5477).”
Peng in view of Chen and Shen are silent with regards to the language of “performing tests and de-embedding processing on the master test structure and the slave test structure respectively, so as to obtain a de-embedded S-parameter and current- voltage data of the master test structure and a de-embedded S-parameter of the slave test structure; setting an initial value of each parasitic element; using the de-embedded S-parameter of the slave test structure to correct at least part of the initial values of the multiple parasitic elements; and setting multiple parasitic parameter values of the multiple parasitic elements.”
Claims 5-15 are dependent on Claim 4.
Conclusion
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/YOSSEF KORANG-BEHESHTI/Examiner, Art Unit 2857
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