DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-11, 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Srivastava et al. (US 2008/0074148).
Claim 1, Srivastava discloses a voltage conversion circuit (Fig. 8), comprising
a first PMOS transistor (P1), a second PMOS transistor (P2), a third PMOS transistor (P3), a fourth PMOS transistor (P4), a first NMOS transistor (N1), a second NMOS transistor (N2), a third NMOS transistor (N3), a fourth NMOS transistor (N4) and a phase inverter (INV), wherein
a source of the first PMOS transistor (P1) is connected to an I/O power supply (VDDE), a drain of the first PMOS transistor is connected with a first node (OUTA), and a gate of the first PMOS transistor is connected with a second node (OUTB),
a drain of the first NMOS transistor (N1) is connected with the first node (OUTA), a source of the first NMOS transistor is grounded (GNDE), and a gate of first NUOS transistor is connected to an input signal (INA),
a source of the second PMOS transistor (P2) is connected to the I/O power supply (VDDE), a drain of the second PMOS transistor is connected with the second node (OUTB), and a gate of the second PMOS transistor is connected with the first node (OUTA),
a drain of the second NMOS transistor (N2) is connected with the second node (OUTB), a source of the second NMOS transistor is grounded (GNDE), a gate of the second NMOS transistor is connected with an output terminal (INB) of the phase inverter (INV), and an input terminal of the phase inverter is connected to the input signal (INA),
a source of the third PMOS transistor (P3) is connected to an external power supply (VDD), a drain of the third PMOS transistor is connected with a third node (A1), and a gate of the third PMOS transistor is connected to the input signal (INA),
a drain of the third NMOS transistor (N3) is connected with the third node (A1), a source of the third NMOS transistor is connected with the first node (OUTA), and a gate of the third NMOS transistor is connected with the second node (OUTB),
a source of the fourth PMOS transistor (P4) is connected to the external power supply (VDD), a drain of the fourth NMOS transistor (N4) is connected with a fourth node (A2), and a gate of the fourth NMOS transistor is connected with the output terminal of the phase inverter (INB),
a drain of the fourth NMOS transistor is connected with the fourth node (A2), a source of the fourth NMOS transistor is connected with the second node (OUTB), and a gate of the fourth NMOS transistor is connected with the first node (OUTA);
when the input signal is at a high level, a reverse signal is at a low level of 0, the drain of the first NMOS transistor is turned on, the drain of the second NMOS transistor is turned off, the drain of the first NMOS transistor pulls down the first node to a low potential of 0, and turns on the source of the second PMOS transistor, and the source of the second PMOS transistor pulls up the second node to a high potential (Fig. 8 of Srivastava is identical structure to applicant’s Fig. 3, according to MPEP 2112.01, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent);
when the input signal is flipped to the low level of 0, the drain of the first NMOS transistor is turned off and the drain of the second NMOS transistor is turned on, at the flip moment, the source of the second PMOS transistor has not been turned off, and the source of the second PMOS transistor and the drain of the second NMOS transistor are turned on at the same time to form a direct path between VDDIO and a ground (Fig. 8 of Srivastava is identical structure to applicant’s Fig. 3, according to MPEP 2112.01, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent);
wherein the second node is not pulled down to the low potential immediately while the source of the third PMOS transistor has been turned on and the third node is charged by the external power supply with a voltage VDDC due to a contention between the source of the second PMOS transistor and the drain of the second NMOS transistor, a temporary high potential of the second node keeps the source of the third NMOS transistor on, and begins to charge the first node, raising a gate voltage of the source of the second PMOS transistor when the source of the second PMOS transistor fails the contention with the drain of the second NMOS transistor, the second node is quickly pulled down to the low potential, and the source of the third NMOS transistor is turned off and stops charging the first node (Fig. 8 of Srivastava is identical structure to applicant’s Fig. 3, according to MPEP 2112.01, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent);
wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are thick gate oxide MOS transistors (N1, N2, P1, P2, N3, and N4 are thick gate oxide) and wherein the third PMOS transistor and the fourth PMOS transistor are thin gate oxide MOS transistors (P3 and P4 are thin gate oxide, see P[0087]… the dynamic charge injection device has been implemented using a thin gate oxide P-channel transistor…).
Claim 2, Srivastava discloses the voltage conversion circuit according to claim 1, wherein a voltage of the I/O power supply is VDDIO, and a range of the VDDIO is 1.6V- 3.6V (see P[0087]...high voltage supply VDDE up to 2.7 V...).
Claim 3, Srivastava discloses the voltage conversion circuit according to claim 1, wherein the external power supply (VDD) is a core power supply of a core circuit (see P[0003]-[0004)).
Claim 4, Srivastava discloses the voltage conversion circuit according to claim 1, wherein a voltage of the external power supply is VDDC1 (VDD), and V- rated>VDDC1>|Vthp (inherent limitation because VDD has to be between V-rate and Vthp in order of turning on/off of the P3 and P4 transistors), wherein the V-rated is a rated working voltage of the third PMOS transistor and the fourth PMOS transistor, and the Vthp is a threshold voltage of the third PMOS transistor and the fourth PMOS transistor.
Claim 7, Srivastava discloses the voltage conversion circuit according to claim 1, wherein the first node or the second node is an output terminal (OUTA and OUTB) of the voltage conversion circuit.
Claim 8, Srivastava discloses a chip (see P[0003]... integrated circuit (IC)...), comprising a core circuit and the voltage conversion circuit (see P[0003]-[0004]), wherein the voltage conversion circuit (Fig. 8), comprises a first PMOS transistor (P1), a second PMOS transistor (P2), a third PMOS transistor (P3), a fourth PMOS transistor (P4), a first NMOS transistor (N1), a second NMOS transistor (N2), a third NMOS transistor (N3), a fourth NMOS transistor (N4) and a phase inverter (INV),
wherein a source of the first PMOS transistor (P1) is connected to an I/O power supply (VDDE), a drain of the first PMOS transistor is connected with a first node (OUTA), and a gate of the first PMOS transistor is connected with a second node (OUTB),
wherein a drain of the first NMOS transistor (N1) is connected with the first node (OUTA), a source of the first NMOS transistor is grounded (GNDE), and a gate of first NUOS transistor is connected to an input signal (INA),
wherein a source of the second PMOS transistor (P2) is connected to the I/O power supply (VDDE), a drain of the second PMOS transistor is connected with the second node (OUTB), and a gate of the second PMOS transistor is connected with the first node (OUTA),
wherein a drain of the second NMOS transistor (N2) is connected with the second node (OUTB), a source of the second NMOS transistor is grounded (GNDE), a gate of the second NMOS transistor is connected with an output terminal (INB) of the phase inverter (INV), and an input terminal of the phase inverter is connected to the input signal (INA),
wherein a source of the third PMOS transistor (P3) is connected to an external power supply (VDD), a drain of the third PMOS transistor is connected with a third node (A1), and a gate of the third PMOS transistor is connected to the input signal (INA),
wherein a drain of the third NMOS transistor (N3) is connected with the third node (A1), a source of the third NMOS transistor is connected with the first node (OUTA), and a gate of the third NMOS transistor is connected with the second node (OUTB),
wherein a source of the fourth PMOS transistor (P4) is connected to the external power supply (VDD), a drain of the fourth NMOS transistor (N4) is connected with a fourth node (A2), and a gate of the fourth NMOS transistor is connected with the output terminal of the phase inverter (INB),
wherein a drain of the fourth NMOS transistor is connected with the fourth node (A2), a source of the fourth NMOS transistor is connected with the second node (OUTB), and a gate of the fourth NMOS transistor is connected with the first node (OUTA);
when the input signal is at a high level, a reverse signal is at a low level of 0, the drain of the first NMOS transistor is turned on, the drain of the second NMOS transistor is turned off, the drain of the first NMOS transistor pulls down the first node to a low potential of 0, and turns on the source of the second PMOS transistor, and the source of the second PMOS transistor pulls up the second node to a high potential (Fig. 8 of Srivastava is identical structure to applicant’s Fig. 3, according to MPEP 2112.01, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent);
when the input signal is flipped to the low level of 0, the drain of the first NMOS transistor is turned off and the drain of the second NMOS transistor is turned on, at the flip moment, the source of the second PMOS transistor has not been turned off, and the source of the second PMOS transistor and the drain of the second NMOS transistor are turned on at the same time to form a direct path between VDDIO and a ground (Fig. 8 of Srivastava is identical structure to applicant’s Fig. 3, according to MPEP 2112.01, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent);
wherein the second node is not pulled down to the low potential immediately while the source of the third PMOS transistor has been turned on and the third node is charged by the external power supply with a voltage VDDC due to a contention between the source of the second PMOS transistor and the drain of the second NMOS transistor, a temporary high potential of the second node keeps the source of the third NMOS transistor on, and begins to charge the first node, raising a gate voltage of the source of the second PMOS transistor when the source of the second PMOS transistor fails the contention with the drain of the second NMOS transistor, the second node is quickly pulled down to the low potential, and the source of the third NMOS transistor is turned off and stops charging the first node (Fig. 8 of Srivastava is identical structure to applicant’s Fig. 3, according to MPEP 2112.01, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent);
wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are thick gate oxide MOS transistors (N1, N2, P1, P2, N3, and N4 are thick gate oxide) and wherein the third PMOS transistor and the fourth PMOS transistor are thin gate oxide MOS transistors (P3 and P4 are thin gate oxide, see P[0087]… the dynamic charge injection device has been implemented using a thin gate oxide P-channel transistor…);
wherein an output terminal of the core circuit (core circuit output) is connected with an input terminal (INA terminal, Fig. 8) of the voltage conversion circuit (see P[0003]-[0004]).
Claims 9-11, and 14 are rejected as above claims 2-4, and 7 since the elements and limitations are similar.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANH Q TRAN/Primary Examiner, Art Unit 2844 11/29/25
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