DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 5 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lee et al (US 2020/0389286).
Regarding claim 1, Lee et al teach an RF receiver (see figure 2 and 3) comprising: a phase detector (see figure 2, component 216,) configured to detect a phase of a down-converted received signal using a clock signal (see figure 2, component 202, and 204); and a phase synchronization device configured to adjust a phase of the clock signal based on the detected phase (see figure 2, component 210 and 208).
Regarding claim 2, which inherits the limitations of claim 1, Lee et al further teach wherein the phase synchronization device comprises: a loop filter configured to determine a phase control value based on an output signal of the phase detector (see figure 2, component 210 “Loop Filter”); and a phase adjuster configured to adjust the phase of the clock signal based on the determined phase control value (see figure 2, component 208).
Regarding claim 5, which inherits the limitations of claim 2, Lee et al further teach wherein: the loop filter is an analog loop filter (see figure 2, component 210), and the phase adjuster is configured to adjust the phase of the clock signal in an analog domain (see figure 2, component 208 VCO).
Claim(s) 10, 11, and 19 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lee et al ( “Future of high-speed short-reach interconnects using clad-dielectric waveguide”, Optical Interconnects XVII. ed. / Ray T. Chen; Henning Schroder. SPIE, 2017. 1010903 (Proceedings of SPIE -The International Society for Optical Engineering; Vol. 10109).) (Lee ref1 hereafter).
Regarding claim 10, Lee ref 1 teach an RF communication system (see figure 1 and 3) comprising: an RF transmitter configured to up-convert a transmission signal to a carrier frequency and transmit the transmission signal (see figure 1, 3, 5, E-Tube TX); an RF receiver configured to down-convert a received signal received on the carrier frequency and receive the received signal (see figure 1, 3, 5, E-Tube RX); a bi-directional (see figure 3, bidirectional E tubes between port 1 and port 2) plastic waveguide device (section 2.1 “E tube” and “the E-TUBE is fabricated using polyethylene tube”) configured to provide a channel for transmission of the transmission signal and a channel for reception of the received signal (see figure 1, 3, 5, and 7) ; and a microstrip-to-waveguide transition (MWT) configured to transfer a signal between the RF transmitter or the RF receiver and the bi-directional plastic waveguide device (see figure 1 MWT), wherein the RF receiver (see figure 5 and 7) comprises: a phase detector configured to detect a phase of the down-converted received signal using a clock signal (see figure 7, phase detector in CDR DLF and section 3.2); and a phase synchronization device configured to adjust a phase of the clock signal based on the detected phase (see figure 7, clock recovery circuits and section 3.2).
Regarding claim 11, which inherits the limitations of claim 10, Lee ref1 further teach wherein the phase synchronization device comprises: a loop filter configured to determine a phase control value based on an output signal of the phase detector (see figure 7, CDR DLP “digital loop filter” and section 3.2); and a phase adjuster configured to adjust the phase of the clock signal based on the determined phase control value (see figure 7, clock recovery circuits, phase interpolator and section 3.2).
Regarding claim 19, which inherits the limitations of claim 10, Lee ref1 further teach wherein: the bi-directional plastic waveguide device (see figure 1) further comprises a first plastic waveguide unit (see figure 1, first E-TUBE) and a second plastic waveguide unit (see figure 1, second E-Tube) each comprising a plastic waveguide (see figure 1 and 2, “Dieletric” section 2.1 “E tube” and “the E-TUBE is fabricated using polyethylene tube”) and metal cladding that surrounds the plastic waveguide (see figure 2, “metal cladding”), and the MWT comprises: a first MWT unit for transferring the transmission signal from the RF transmitter to the first plastic waveguide unit (see figure 1 and 5 “MWT”); and a second MWT unit for transferring the received signal from the second plastic waveguide unit to the RF receiver (see figure 1, 5, and 7 “MWT”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0389286) in view of Cho et al (US 11,271,710).
Regarding claim 6, which inherits the limitations of claim 2, Lee et al does not expressly disclose a multi-phase filter generate a in phase and quadrature clock signals. However, in analogous art, Cho et al teach a multi-phase (polyphase) filter, and the multi-phase filter is configured to generate an in-phase (I) clock signal and a quadrature phase (Q) clock signal from a signal of a clock source and to provide the in-phase (I) clock signal and the quadrature phase (Q) clock signal to the phase adjuster (see figure 1, component 20 and figure 2). Therefore, it would have been obvious to an ordinary skilled in the art at the time the invention was filed to use multi-phase filter to generate quadrature signals. The motivation or suggestion to do so is to have a reduced complexity circuit to generate quadrature signals.
Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2020/0389286) in view of Cho et al (US 11,271,710) and further in view of Crain et al (US 2021/0207259).
Regarding claim 7, which inherits the limitations of claim 6, Lee et al in view of Cho et al further teach wherein the RF receiver further comprises: an in-phase (I) down converter mixer (see Lee et al, figure 2, component 202) and a quadrature phase (Q) down converter mixer (see Lee et al, figure 2, component 204); and wherein the in-phase (I) down converter mixer is configured to down-convert the received signal using the in-phase (I) clock signal which is phase-adjusted by the phase adjuster and converted into a carrier frequency (see Lee et al, figure 2, component 202), and the quadrature phase (Q) down converter mixer is configured to down-convert the received signal using the quadrature phase (Q) clock signal which is phase-adjusted by the phase adjuster and converted into a carrier frequency (see Lee et al, figure 2, component 202). Lee et al in view of Cho et al does not expressly disclose having a multiplier. However, using frequency multiplier to generate desired frequency clock is having a multiplier (see figure 10 and 11, Divider). Therefore, it would have been obvious to an ordinary skilled in the art at the time the invention was filed to use a frequency multiplier. The motivation or suggestion to do so is to achieve the desired frequency clock signal.
Regarding claim 9, which inherits the limitations of claim 7, Lee et al in view of Cho et al and Crains et al further teach wherein the multiplier is disposed between the in-phase (I) down converter mixer and the quadrature phase (Q) down converter mixer, and the phase synchronization device (see figure 11), or is disposed between the clock source and the phase synchronization device (see figure 10).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, et al ( “Future of high-speed short-reach interconnects using clad-dielectric waveguide”, Optical Interconnects XVII. ed. / Ray T. Chen; Henning Schroder. SPIE, 2017. 1010903 (Proceedings of SPIE -The International Society for Optical Engineering; Vol. 10109).) (Lee ref1 hereafter) in view of Lee et al (US 2020/0389286).
Regarding claim 14, which inherits the limitations of claim 11, Lee ref1 does not expressly disclose analog loop filter and processing the phase in analog domain. However, compensating the phase error in analog domain in well known in the art. Further, Lee et al teach a RF receiver comprising wherein: the loop filter is an analog loop filter (see figure 2, component 210), and the phase adjuster is configured to adjust the phase of the clock signal in an analog domain (see figure 2, component 208 VCO). Therefore, it would have been obvious to an ordinary skilled in the art at the time the invention was filed to process the signal in analog domain. The motivation or suggestion to do so is to reduce the signal processing latency in the compensation circuits.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, et al ( “Future of high-speed short-reach interconnects using clad-dielectric waveguide”, Optical Interconnects XVII. ed. / Ray T. Chen; Henning Schroder. SPIE, 2017. 1010903 (Proceedings of SPIE -The International Society for Optical Engineering; Vol. 10109).) (Lee ref1 hereafter) in view of Cho et al (US 11,271,710).
Regarding claim 15, which inherits the limitations of claim 11, Lee Ref 1 does not expressly disclose a multi-phase filter generate a in phase and quadrature clock signals. However, in analogous art, Cho et al teach a multi-phase (polyphase) filter, and the multi-phase filter is configured to generate an in-phase (I) clock signal and a quadrature phase (Q) clock signal from a signal of a clock source and to provide the in-phase (I) clock signal and the quadrature phase (Q) clock signal to the phase adjuster (see figure 1, component 20 and figure 2). Therefore, it would have been obvious to an ordinary skilled in the art at the time the invention was filed to use multi-phase filter to generate quadrature signals. The motivation or suggestion to do so is to have a reduced complexity circuit to generate quadrature signals.
Claim(s) 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, et al ( “Future of high-speed short-reach interconnects using clad-dielectric waveguide”, Optical Interconnects XVII. ed. / Ray T. Chen; Henning Schroder. SPIE, 2017. 1010903 (Proceedings of SPIE -The International Society for Optical Engineering; Vol. 10109).) (Lee ref1 hereafter) in view of Cho et al (US 11,271,710) and further in view of Crain et al (US 2021/0207259).
Regarding claim 16, which inherits the limitations of claim 15, Lee et al in view of Cho et al further teach wherein the RF receiver further comprises: an in-phase (I) down converter mixer (see Lee et al, figure 2, component 202) and a quadrature phase (Q) down converter mixer (see Lee et al, figure 2, component 204); and wherein the in-phase (I) down converter mixer is configured to down-convert the received signal using the in-phase (I) clock signal which is phase-adjusted by the phase adjuster and converted into a carrier frequency (see Lee et al, figure 2, component 202), and the quadrature phase (Q) down converter mixer is configured to down-convert the received signal using the quadrature phase (Q) clock signal which is phase-adjusted by the phase adjuster and converted into a carrier frequency (see Lee et al, figure 2, component 202). Lee et al in view of Cho et al does not expressly disclose having a multiplier. However, using frequency multiplier to generate desired frequency clock is having a multiplier (see figure 10 and 11, Divider). Therefore, it would have been obvious to an ordinary skilled in the art at the time the invention was filed to use a frequency multiplier. The motivation or suggestion to do so is to achieve the desired frequency clock signal.
Regarding claim 18, which inherits the limitations of claim 16, Lee et al in view of Cho et al and Crains et al further teach wherein the multiplier is disposed between the in-phase (I) down converter mixer and the quadrature phase (Q) down converter mixer, and the phase synchronization device (see figure 11), or is disposed between the clock source and the phase synchronization device (see figure 10).
Allowable Subject Matter
Claim 3, 4, 8, 12, 13, 17, and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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JAISON . JOSEPH
Primary Examiner
Art Unit 2633
/JAISON JOSEPH/ Primary Examiner, Art Unit 2633