DETAILED ACTION
This action is in response to the communications filed 3/7/2023, claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/7/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on 6/25/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on 6/24/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, and 8-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hariharan et al, US Publication No. 2019/0005974 A1.
Regarding Claim 1, Hariharan et al teaches, an audio codec (Title/Abstract, Paragraph 40, FIG. 2, System 200, FIG. 3, System 300, FIG. 4, System 400.) comprising: an inter-IC sound (I2S) agent (FIG. 3, IC devices 302 and 332, FIG. 4, IC devices 402 and 442, Paragraphs 45, 48, 60, and 62); a digital-to-analog converter (DAC) (FIG. 3, DACs 310 and 338, FIG. 4, DACs 410 and 448, Paragraphs 51, 53, 68, and 71.); and an I2S word-select (WS) detector (FIG. 2, Falling edge 222, Rising Edge 226, Paragraphs 42, 82, and 83, FIG. 5), the I2S WS detector configured to enable the I2S agent and the DAC, such that the DAC and the I2S agent begin processing data simultaneously (FIG. 5, Paragraph 43, “In the timing diagram 220, the edges 222, 226 in WS 214 are depicted as being coincident with the boundaries 224, 228 between consecutively transmitted words 230, 232, 234. In some instances, I2S transmitters 202 and/or receivers 204 devices may include buffers, registers, flip-flops and/or other circuits that delay serial transmit data and receive data with respect to WS 214.”).
Regarding Claim 2, Hariharan et al teaches all the limitations of claim 1, and further teaches, wherein the I2S agent is configured to receive a clock signal, a WS signal, and the data from a wireless system, where the data includes one or more digital audio samples (FIG. 2, SCK 212 (Serial Clock Signal), WS 214 (Word Select Signal), SD 216 (audio data transmitted in the serial data signal). Paragraph 36, specifies wireless communication methods utilized.).
Regarding Claim 3, Hariharan et al teaches all the limitations of claim 2, and further teaches, wherein the I2S agent includes an internal buffer, and the I2S agent is configured to temporarily store the one or more digital audio samples in the internal buffer of the I2S agent (Paragraph 43, “In some instances, I2S transmitters 202 and/or receivers 204 devices may include buffers, registers, flip-flops and/or other circuits that delay serial transmit data and receive data with respect to WS 214.”).
Regarding Claim 8, Hariharan et al teaches all the limitations of claim 2, and further teaches, further comprising a processor (Paragraph 64, “In the illustrated example, both IC devices 402, 442 may operate as audio Codecs. The primary IC device 402 hosts a processing entity that may include a microcontroller (MCU 404) and/or other type of processor or processing circuit.”).
Regarding Claim 9, Hariharan et al teaches all the limitations of claim 8, and further teaches, wherein the processor is configured to initialize the I2S agent and the DAC (Paragraph 70, “One or more signals 414 provided by the clock source 412 may be configured to control timing of respective serial clock and word select signals, and/or to configure or set sampling rates. Reset and/or enable signals 424, 426 may be provided by the MCU 404 or by another processor to synchronize and initialize the primary I2S interface device 406 and the shadow I2S interface device 416, in some instances, the reset and/or enable signals 424, 426 may be tied together.”, Paragraph 71, Paragraph 51, “The primary IC device 302 may include one or more ADC, including the left ADC 308, and one or more DAC, including the left DAC 310.”).
Regarding Claim 10, Hariharan et al teaches all the limitations of claim 9, and further teaches, wherein the processor is further configured to, after initializing the 12S agent and the DAC, initialize the 12S WS detector (Paragraph 76, “In some instances, the I2S interface devices 406, 416, 444 may pipeline transmit and receive data. In one example, a pipeline in the transmitter of an I2S interface device 406, 416, 444 may have a depth of one or two words such that data arriving at the TxR and TxL inputs of the I2S interface devices 406 416, 444 may be queued in a pipeline and may be appear ta the Tx output of the I2S interface devices 406, 416, 444 after a one or two-word delay. In some instances, the output of serialization may be buffered or delayed such that edges in I2S WS 436 may occur in advance of the serialized words.”).
Regarding Claim 11, Hariharan et al teaches all the limitations of claim 10, and further teaches, wherein the 12S WS detector is configured to: after initialization, monitor the WS signal for a rising edge (Paragraphs 82 and 83, FIG. 5, teaches a change in a WS signal and how it is monitored for highs and lows.).
Regarding Claim 12, Hariharan et al teaches all the limitations of claim 11, and further teaches, wherein the I2S WS detector is further configured to: after detecting the rising edge on the WS signal, send an enable command to the I2S agent and the DAC immediately before a subsequent rising edge of the WS signal (FIG. 4, Reset/Enable Signals 424, 426, MCU 404, Primary/Shadow I2S 406 416, Paragraph 70.).
Regarding Claim 13, Hariharan et al teaches all the limitations of claim 11, and further teaches, wherein the I2S WS detector is further configured to: after detecting the rising edge on the WS signal, wait a first predetermined period of time (Paragraph 76, “a pipeline in the transmitter of an I2S interface device 406, 416, 444 may have a depth of one or two words such that data arriving at the TxR and TxL inputs of the I2S interface devices 406 416, 444 may be queued in a pipeline and may be appear ta the Tx output of the I2S interface devices 406, 416, 444 after a one or two-word delay.”); and send an enable command to the I2S agent after the first predetermined period of time (Paragraphs 76-78, “In some instances, the output of serialization may be buffered or delayed such that edges in I2S WS 436 may occur in advance of the serialized words. Data received from the I2S bus 432 may be further delayed before appearing at the RxR and/or RxL outputs of an I2S interface device 406, 416, 444. The primary IC device 402 and/or the secondary IC device 442 may include circuits that align or optimize timing of various signals.”).
Regarding Claim 14, Hariharan et al teaches all the limitations of claim 13, and further teaches, wherein the I2S WS detector is further configured to: after detecting the rising edge on the WS signal, wait a second predetermined period of time; and send an enable command to the DAC after the second predetermined period of time (Paragraphs 76-78, “Data received from the I2S bus 432 may be further delayed before appearing at the RxR and/or RxL outputs of an I2S interface device 406, 416, 444. The primary IC device 402 and/or the secondary IC device 442 may include circuits that align or optimize timing of various signals.”, “delayed version of I2S WS 436 to meet timing tolerances for the shadow I2S interface device 416, the multiplexer 420, and/or other circuits. In some instances, the delayed version of I2S WS 436 may account for the impact of buffering and/or pipelines on timing of signals used in the transmitter and/or receiver of one or more I2S interface devices 406, 416, 444.”).
Regarding Claim 15, Hariharan et al teaches a method for controlling an audio codec (Title/Abstract, Paragraph 40, FIG. 2, System 200, FIG. 3, System 300, FIG. 4, System 400.) including an inter- IC sound (12S) agent (FIG. 3, IC devices 302 and 332, FIG. 4, IC devices 402 and 442, Paragraphs 45, 48, 60, and 62), a digital-to-analog converter (DAC) (FIG. 3, DACs 310 and 338, FIG. 4, DACs 410 and 448, Paragraphs 51, 53, 68, and 71.), and an I2S word-select (WS) detector (FIG. 2, Falling edge 222, Rising Edge 226, Paragraphs 42, 82, and 83, FIG. 5), the method comprising: initializing the 12S agent, the DAC, and the 12S WS detector (Paragraph 70, FIG. 4, reset/enable signals 424, 426); receiving, by the I2S agent, a clock signal and a WS signal from a wireless system (FIG. 2, SCK 212 (Serial Clock Signal), WS 214 (Word Select Signal), SD 216 (audio data transmitted in the serial data signal).); monitoring, by the I2S WS detector, after initialization, the WS signal for a rising edge (Paragraph 42, FIG. 2, Falling edge 222, rising edge 226, paragraphs 82 and 83, FIG. 5.); and after detecting the rising edge, transmitting, by the 12S WS detector, an enable command to the DAC and an enable command to the 12S agent prior to a subsequent rising edge on the WS signal (Paragraph 43, “versions of WS 214 may be generated to control the operation of logic circuits in the transmitter 202 or receiver 204.”).
Regarding Claim 16, Hariharan et al teaches all the limitations of claim 15, and further teaches, waiting, by the I2S WS detector, a first predetermined period of time after detecting the rising edge on the WS signal (Paragraph 76, “a pipeline in the transmitter of an I2S interface device 406, 416, 444 may have a depth of one or two words such that data arriving at the TxR and TxL inputs of the I2S interface devices 406 416, 444 may be queued in a pipeline and may be appear ta the Tx output of the I2S interface devices 406, 416, 444 after a one or two-word delay.”); and sending by the I2S WS detector, the enable command to the I2S agent after the first predetermined period of time (Paragraphs 76-78, “In some instances, the output of serialization may be buffered or delayed such that edges in I2S WS 436 may occur in advance of the serialized words. Data received from the I2S bus 432 may be further delayed before appearing at the RxR and/or RxL outputs of an I2S interface device 406, 416, 444. The primary IC device 402 and/or the secondary IC device 442 may include circuits that align or optimize timing of various signals.”).
Regarding Claim 17, Hariharan et al teaches all the limitations of claim 16, and further teaches, waiting, by the 12S WS detector, a second predetermined period of time after detecting the rising edge on the WS signal; and sending by the 12S WS detector, the enable command to the DAC after the second predetermined period of time (Paragraphs 76-78, “Data received from the I2S bus 432 may be further delayed before appearing at the RxR and/or RxL outputs of an I2S interface device 406, 416, 444. The primary IC device 402 and/or the secondary IC device 442 may include circuits that align or optimize timing of various signals.”, “delayed version of I2S WS 436 to meet timing tolerances for the shadow I2S interface device 416, the multiplexer 420, and/or other circuits. In some instances, the delayed version of I2S WS 436 may account for the impact of buffering and/or pipelines on timing of signals used in the transmitter and/or receiver of one or more I2S interface devices 406, 416, 444.”).
Regarding Claim 18, Hariharan et al teaches all the limitations of claim 16, and further teaches, receiving, by the I2S agent one or more digital audio samples from the wireless system (Paragraphs 40-41, FIG. 2, SD 216 (Audio Data transmitted in the serial data signal). Paragraph 36 specifies wireless communications utilized.).
Regarding Claim 19, Hariharan et al teaches all the limitations of claim 18, and further teaches, converting, by the DAC, the one or more digital audio samples received by 12S agent into analog signals for playback (Paragraph 51, “The primary IC device 302 may include one or more ADC, including the left ADC 308, and one or more DAC, including the left DAC 310. The primary IC device 302 may use the left ADC 308 to digitize audio signals obtained from a left-side microphone or other transducer, and may use the left DAC 310 to drive a left-side speaker. In some instances, a right-side microphone and right-side speaker may be handled by the secondary IC device 332. In one example, the primary IC device 302 may have insufficient ADCs and DACs to handle the right-side microphone and right-side speaker. In another example, the secondary IC device 332 may be configured to handle the right-side microphone and right-side speaker for reasons related to physical location, and/or application requirements.”).
Regarding Claim 20, Hariharan et al teaches all the limitations of claim 15, and further teaches, wherein the 12S WS detector is initialized after the DAC and the I2S agent (Paragraph 76, “In some instances, the I2S interface devices 406, 416, 444 may pipeline transmit and receive data. In one example, a pipeline in the transmitter of an I2S interface device 406, 416, 444 may have a depth of one or two words such that data arriving at the TxR and TxL inputs of the I2S interface devices 406 416, 444 may be queued in a pipeline and may be appear ta the Tx output of the I2S interface devices 406, 416, 444 after a one or two-word delay. In some instances, the output of serialization may be buffered or delayed such that edges in I2S WS 436 may occur in advance of the serialized words.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hariharan et al, US Publication No. 2019/0005974 A1, in view of Berreth, US Publication No. 2006/0074637 A1.
Regarding Claim 4, Hariharan et al teaches all the limitations of claim 3, but does not further teach, a memory buffer, wherein the I2S agent is configured to transmit the one or more digital audio samples in the internal buffer of the I2S agent to the memory buffer
However, Berreth, in a similar invention in the same field of endeavor teaches, a memory buffer, wherein the I2S agent is configured to transmit the one or more digital audio samples in the internal buffer of the I2S agent to the memory buffer (FIG. 2, FIG. 3, Data (write to buffer), Data (read from buffer), Cyclic Buffer 122, FIFO buffer 308.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of a memory buffer, the I2S agent transmitting audio samples from the internal buffer of the I2S agent to said memory buffer, as taught by Berreth, with the system as taught by Hariharan et al. The motivation being to allow for a more refined control of the signal transference between components, and ensuring proper syncing of the resultant signals.
Regarding Claim 5, Hariharan et al in view of Berreth teaches all the limitations of claim 4, and Berreth further teaches, wherein the memory buffer is a circular buffer (FIG. 3, Cyclic Buffer 122.).
Regarding Claim 6, Hariharan et al in view of Berreth teaches all the limitations of claim 4, and Berreth further teaches, wherein the DAC includes an internal buffer, and wherein, the DAC is configured to: receive or retrieve one or more of the digital audio samples from the memory buffer (FIG. 2, FIG. 3, Audio Device 124, DAC 310, Position Register 312); and store the one or more of the digital audio samples into the internal buffer of the DAC (FIG. 2, FIG. 3, Paragraph 50, Paragraph 281.).
Regarding Claim 7, Hariharan et al in view of Berreth teaches all the limitations of claim 6, and Hariharan et al further teaches, wherein the DAC is configured to: convert the one or more of the digital audio samples into analog signals; and output the analog signals to a speaker for playback (Paragraph 51, “The primary IC device 302 may include one or more ADC, including the left ADC 308, and one or more DAC, including the left DAC 310. The primary IC device 302 may use the left ADC 308 to digitize audio signals obtained from a left-side microphone or other transducer, and may use the left DAC 310 to drive a left-side speaker. In some instances, a right-side microphone and right-side speaker may be handled by the secondary IC device 332. In one example, the primary IC device 302 may have insufficient ADCs and DACs to handle the right-side microphone and right-side speaker. In another example, the secondary IC device 332 may be configured to handle the right-side microphone and right-side speaker for reasons related to physical location, and/or application requirements.”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DYLAN M NEECE whose telephone number is (703)756-1941. The examiner can normally be reached 10am - 7pm.
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/DYLAN MAGUIRE NEECE/Examiner, Art Unit 2692
/CAROLYN R EDWARDS/Supervisory Patent Examiner, Art Unit 2692