Prosecution Insights
Last updated: October 02, 2026
Application No. 18/690,232

METHOD, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND DEVICE OF VIRTUAL MACHINE RESOURCE ALLOCATION

Non-Final OA §102§103
Filed
Mar 07, 2024
Priority
Oct 20, 2021 — CN 202111222020.X +1 more
Examiner
SWIFT, CHARLES M
Art Unit
Tech Center
Assignee
Beijing Bytedance Network Technology Co., Ltd.
OA Round
2 (Non-Final)
81%
Grant Probability
Favorable
2-3
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
726 granted / 900 resolved
+20.7% vs TC avg
Strong +23% interview lift
Without
With
+22.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
38 currently pending
Career history
939
Total Applications
across all art units

Statute-Specific Performance

§101
11.1%
-28.9% vs TC avg
§103
57.2%
+17.2% vs TC avg
§102
16.3%
-23.7% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 900 resolved cases

Office Action

§102 §103
DETAILED ACTION This office action is in response to amendments filed on 8/14/2026. Claims 11, 17, 19 and 27 are amended. Claims 16, 24 and 30 are cancelled. Claims 11 – 15, 17 – 23 and 25 – 29 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 11, 19, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Day II et al (US 20110072428, hereinafter Day), in view of Moriki et al (US 20170277632m hereinafter Moriki). As per claim 11, Day discloses: A method of virtual machine resource allocation, comprising: allocating corresponding bare-metal machines to virtual machines when the virtual machines are created in a physical machine, wherein the bare-metal machines are obtained by segmenting physical resources of the physical machine, and the virtual machines are in one-to-one correspondence with the bare-metal machines; (Day figure 1, [0020]: “The functions of the primary VMM 30 include establishing the primary VM 32, which provides a first-level virtualization environment to which a portion of the hardware resources of the physical machine 4 are allocated (e.g., CPU time slices and memory addresses). The assigned hardware resources may be referred to generally as virtual resources, and because they are assigned to the primary VM 32, they may be referred to specifically as primary virtual resources, as shown by reference numeral 32A in FIG. 1. A guest running on the primary VM 32, in this case the secondary VMM 34, will see the primary virtual resources 32A as if they represented a dedicated physical machine, and will operate accordingly.”; [0021]: “The functions of the secondary VMM 34 include establishing the secondary VM 36, which provides a second-level virtualization environment to which a portion of the primary virtual resources 32A of the primary VM 32 are allocated (e.g., CPU time slices and memory addresses). The assigned hardware resources may be referred to generally as virtual resources, and because they are assigned to the secondary VM 36, they may be referred to specifically as secondary virtual resources”. Examiner note claimed bare-metal machine are mapped to the portioned hardware resources allocated by the VMM 300.) configuring an operation mode of the bare-metal machines to a non-root mode; (Day [0023]: “Guests running within the primary VM 32, including the secondary VMM 34, operate in the CPU's non-root mode.”) and switching an operation mode of a CPU of the physical machine to the non-root mode so as to start the virtual machines in the bare-metal machines; (Day [0024]: “During operation of the physical machine 4, the execution state will periodically shift between the real root mode and the real non-root mode. Initially, the CPU 10 may run in real root mode in which the primary VMM 30 performs its virtual machine monitor functions. Thereafter, the primary VMM 30 may cause the physical machine 4 to leave the real root mode and enter the real non-root mode in order to execute the primary VM 32. This may be referred to as a VM-entry.”) Day did not explicitly disclose: wherein configuring the operation mode of the bare-metal machine to the non-root mode comprises: determining a physical address corresponding to a memory allocated for the bare-metal machine in the physical machine; and configuring the physical address to be a guest physical address of the bare-metal machine, and disabling an extended page table virtualization mode, so that the bare-metal machine accesses the memory based on the guest physical address. However, Moriki teaches: wherein configuring the operation mode of the bare-metal machine to the non-root mode comprises: determining a physical address corresponding to a memory allocated for the bare-metal machine in the physical machine; and configuring the physical address to be a guest physical address of the bare-metal machine, and disabling an extended page table virtualization mode, so that the bare-metal machine accesses the memory based on the guest physical address. (Moriki [0020]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Moriki into that of Day in order to have the configuring the operation mode of the bare-metal machine to the non-root mode comprises: determining a physical address corresponding to a memory allocated for the bare-metal machine in the physical machine; and configuring the physical address to be a guest physical address of the bare-metal machine, and disabling an extended page table virtualization mode, so that the bare-metal machine accesses the memory based on the guest physical address. Moriki has shown the claimed limitations are merely commonly known and used in nested virtualization, and applicants therefore has merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103. As per claim 19, it is the device variant of claim 11 and is therefore rejected under the same rationale. As per claim 27, it is the non-transitory computer-readable storage medium variant of claim 11 and is therefore rejected under the same rationale. Claim(s) 12 – 14, 20 – 22, 28 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Day and Moriki, in view of Mahallingam et al (US 20080294825, hereinafter Mahallingam). As per claim 12, the combination of Day and Moriki did not teach: The method according to claim 11, wherein configuring the operation mode of the bare-metal machine to the non-root mode comprises: configuring an interrupt control register in the physical machine to be in a pass-through non-root mode, so that an operating system of the virtual machine sends inter-processor interrupts through the interrupt control register; and configuring a maskable interrupt of the CPU of the physical machine to be in the pass- through non-root mode and a non-maskable interrupt of the CPU to be in a non-pass-through mode, so that an interrupt of an operating system of the virtual machine is the maskable interrupt and an interrupt of a host operating system of the physical machine is the non-maskable interrupt. However, Mahallingam teaches: The method according to claim 11, wherein configuring the operation mode of the bare-metal machine to the non-root mode comprises: configuring an interrupt control register in the physical machine to be in a pass-through non-root mode, so that an operating system of the virtual machine sends inter-processor interrupts through the interrupt control register; and configuring a maskable interrupt of the CPU of the physical machine to be in the pass- through non-root mode and a non-maskable interrupt of the CPU to be in a non-pass-through mode, so that an interrupt of an operating system of the virtual machine is the maskable interrupt and an interrupt of a host operating system of the physical machine is the non-maskable interrupt. (Mahallingam figure 6 and [0085]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Mahallingam into that of Day and Moriki in order to have the configuring the operation mode of the bare-metal machine to the non-root mode comprises: configuring an interrupt control register in the physical machine to be in a pass-through non-root mode, so that an operating system of the virtual machine sends inter-processor interrupts through the interrupt control register; and configuring a maskable interrupt of the CPU of the physical machine to be in the pass- through non-root mode and a non-maskable interrupt of the CPU to be in a non-pass-through mode, so that an interrupt of an operating system of the virtual machine is the maskable interrupt and an interrupt of a host operating system of the physical machine is the non-maskable interrupt. Mahallingam has shown the claimed limitations are merely commonly known steps for interrupts in a virtualized computing system and applicants have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103. As per claim 13, the combination of Day, Moriki and Mahallingam further teach: The method according to claim 12, further comprising: exiting the non-root mode in terms of the operation mode of the CPU if a target non-maskable interrupt is received from the host operating system; and sending a maskable interrupt, which corresponds to an interrupt vector number of the non-maskable interrupt, to the host operating system itself, so as to enter an interrupt handler of the host operating system for interrupt handling. (Day [0027]) As per claim 14, the combination of Day, Moriki and Mahallingam further teach: The method according to claim 12, wherein configuring the operation mode of the bare-metal machine to the non-root mode further comprises: configuring a performance monitor unit register in the physical machine to be in the pass-through non-root mode, so that the bare-metal machine accesses a performance monitor unit; configuring a local advanced programmable interrupt controller to be in an x2APIC mode; and configuring a model-specific register corresponding to a clock source of the local advanced programmable interrupt controller to be in the pass-through non-root mode. (Mahallingam [0085]) As per claim 20, it is the device variant of claim 12 and is therefore rejected under the same rationale. As per claim 21, it is the device variant of claim 13 and is therefore rejected under the same rationale. As per claim 22, it is the device variant of claim 14 and is therefore rejected under the same rationale. As per claim 28, it is the non-transitory computer-readable storage medium variant of claim 13 (including limitations from parent claim 12) and is therefore rejected under the same rationale. As per claim 29, it is the non-transitory computer-readable storage medium variant of claim 14 and is therefore rejected under the same rationale. Claim(s) 15 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Day, Moriki and Mahallingam, and further in view of Niesser et al (US 20130125118, hereinafter Niesser). As per claim 15, the combination of Day, Moriki and Mahallingam did not explicitly teach: The method according to claim 14, further comprising: configuring a high-precision event timer as a clock source of the host operating system of the physical machine. However, Niesser teaches: The method according to claim 14, further comprising: configuring a high-precision event timer as a clock source of the host operating system of the physical machine. (Niesser [0023]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Niesser into that of Day, Moriki and Mahallingam in order to configure a high-precision event timer as a clock source of the host operating system of the physical machine. Niesser has shown the claimed limitations are merely commonly known components in virtualized computing to keep precise time and the applicants have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103. As per claim 23, it is the device variant of claim 15 and is therefore rejected under the same rationale. Claim(s) 17 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Day and Moriki, in view of Tsirkin et al (US 20160350236, hereinafter Tsirkin). As per claim 17, the combination of Day and Moriki did not teach: The method according to claim 16, wherein configuring the operation mode of the bare-metal machine to the non-root mode further comprises: configuring a memory management unit to disable an IOMMU page table, so that the bare-metal machine performs memory management based on a direct memory access mode. However, Tsirkin teaches: The method according to claim 16, wherein configuring the operation mode of the bare-metal machine to the non-root mode further comprises: configuring a memory management unit to disable an IOMMU page table, so that the bare-metal machine performs memory management based on a direct memory access mode. (Tsirkin [0034]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Tsirkin into that of Day and Moriki in order to configure a memory management unit to disable an IOMMU page table, so that the bare-metal machine performs memory management based on a direct memory access mode. Tsirkin has shown the claimed limitations are merely commonly known components for implementing privilege (root mode) processing and the applicants have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103. As per claim 25, it is the device variant of claim 17 and is therefore rejected under the same rationale. Claim(s) 18 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Day and Moriki, in view of Birke et al (US 20140215464, hereinafter Birke). As per claim 17, the combination of Day and Moriki did not teach: The method according to claim 11, wherein the bare-metal machines are obtained by segmenting the physical resources of the physical machine in the following manners: acquiring bare-metal machine configuration information through a user-mode virtualization component after the host operating system of the physical machine is started; and segmenting the physical resources of the physical machine according to the bare-metal machine configuration information to obtain the bare-metal machines, wherein the physical resources comprise CPUs, memories and IO devices. However, Birke teaches: The method according to claim 11, wherein the bare-metal machines are obtained by segmenting the physical resources of the physical machine in the following manners: acquiring bare-metal machine configuration information through a user-mode virtualization component after the host operating system of the physical machine is started; and segmenting the physical resources of the physical machine according to the bare-metal machine configuration information to obtain the bare-metal machines, wherein the physical resources comprise CPUs, memories and IO devices. (Birke [0058])It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Birke into that of Day and Moriki in order to acquire bare-metal machine configuration information through a user-mode virtualization component after the host operating system of the physical machine is started; and segmenting the physical resources of the physical machine according to the bare-metal machine configuration information to obtain the bare-metal machines, wherein the physical resources comprise CPUs, memories and IO devices. Birke has shown the claimed limitations are merely commonly known steps for allocating resources to provisioning the VM and applicants have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103. As per claim 26, it is the device variant of claim 18 and is therefore rejected under the same rationale. Response to Arguments Applicant’s arguments, see arguments, filed 8/14/2026, with respect to the rejection(s) of claim(s) 6, 24 and 30 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 USC 103, see appropriate sections above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at 5712701014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHARLES M SWIFT/Primary Examiner, Art Unit 2196
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Prosecution Timeline

Mar 07, 2024
Application Filed
May 14, 2026
Non-Final Rejection mailed — §102, §103
Aug 14, 2026
Response Filed
Sep 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

2-3
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+22.6%)
3y 0m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 900 resolved cases by this examiner. Grant probability derived from career allowance rate.

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