Prosecution Insights
Last updated: April 19, 2026
Application No. 18/690,466

DM-RS TYPES WITH TIME-DOMAIN RESOURCE ALLOCATION

Non-Final OA §103
Filed
Mar 08, 2024
Examiner
NOORISTANY, SULAIMAN
Art Unit
2415
Tech Center
2400 — Computer Networks
Assignee
LENOVO (SINGAPORE) PTE. LTD.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
3y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
703 granted / 911 resolved
+19.2% vs TC avg
Strong +24% interview lift
Without
With
+24.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
33 currently pending
Career history
944
Total Applications
across all art units

Statute-Specific Performance

§101
6.1%
-33.9% vs TC avg
§103
51.5%
+11.5% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
14.0%
-26.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 911 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung US 20210321442 in view of Xiong WO 2020146638 1. A user equipment (“UE”) apparatus, comprising: a transceiver: and a processor coupled to the transceiver, the processor configured to cause the apparatus to: receive a demodulation reference signal (“DM-RS”) configuration from a network (Jung: [0373] UE may receive at least one configuration information “e.g., DMRS port configuration”), the DM-RS configuration comprising a time domain occasion of a DM-RS sequence within a block duration of [[a single carrier waveform]], a time domain pattern of the DM-RS sequence, and a sequence length of the DM-RS sequence (Jung: [0168, 0171, 0200] DMRS sequence); receive a DM-RS sequence within the block duration of the single carrier waveform according to the received DM-RS configuration (Jung: [0375] the UE receives the first PDCCH or the second PDCCH in a specific CORESET based on the configuration information from the base station); receive a data sequence that is quasi-collocated with an associated DM-RS resource: and demodulate the received data sequence using the DM-RS sequence (Jung: [0376-0379] the UE may receive data via the first PDSCH or the second PDSCH corresponding to the first PDCCH or the second PDCCH based on at least one of the identified information in operation 15-10 and the result of determination in operation 15-20 and The UE may perform decoding on the received data). Jung merely discloses term “a single carrier waveform” Xiong further teaches a time domain occasion of a DM-RS sequence within a block duration of a single carrier waveform (Xiong: fig. 4 [0061-0067] DM-RS sequence in a frequency domain or a time domain for a single carrier with a frequency domain equalizer (SC-FDE) based waveform) Thus, it would have been obvious to one skill in the art before the effective filing date of the claim invention to include the above recited limitation into Jung’s invention in order to reduce the receiver complexity, as taught by Xiong. 2. The apparatus of claim 1, wherein DM-RS blocks of guard interval length are inserted periodically in the time domain occasion of a block of fast Fourier transform (“FFT”) length data (Xiong: fig. 4 [0050-0055] sequence (guard interval (GI)). 3. The apparatus of claim 2, wherein a combination of the DM-RS used as a guard interval inside an N-FFT block and DM-RS employed as a whole block length with a random guard interval are configured simultaneously (Jung: fig. 4-5 [0089]; Xiong: fig. 4 [0050-0055] sequence (guard interval (GI)). Claim(s) 4-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung US 20210321442 in view of Xiong WO 2020146638 further in view of YOSHIMURA US 20200163060 4. The apparatus of claim 1, wherein lengths of one or more additional DM-RS blocks are cyclically extended within an N-fast Fourier transform (“FFT”) block (YOSHIMURA: [0023] fig. 7 additional DM-RS blocks). Thus, it would have been obvious to one skill in the art before the effective filing date of the claim invention to include the above recited limitation into Jung’s invention in order to determine a value of a cyclic shift applied to the DMRS, as taught by YOSHIMURA. 5. The apparatus of claim 3, wherein the length of the one or more additional DM-RS blocks is the same as a length of a first DM-RS block (Jung: [0168, 0171, 0200]; Xiong: fig. 4-5 [0050-0055]; YOSHIMURA: [0023] fig. 7 additional DM-RS blocks). 6. The apparatus of claim 3, wherein the length of the one or more additional DM-RS blocks is variable such that the length is increased by a factor of a length of a first DM-RS block (Jung: fig. 4-5 [0089]; Xiong: fig. 4-5 [0050-0055]; YOSHIMURA: [0023] fig. 7 additional DM-RS blocks). 7. The apparatus of claim 3, wherein the one or more additional DM-RS blocks are inserted at specified block numbers (Jung: [0168, 0171, 0200]; Xiong: fig. 4-5 [0050-0055]; YOSHIMURA: [0023] fig. 7 additional DM-RS blocks). 8. The apparatus of claim 7, wherein at least a partial DM-RS block length extension is indicated using at least two variables in downlink control information (“DCI”) (Jung: [0118-0119]; Xiong: fig. 4-5 [0050-0055]). 9. The apparatus of claim 3, wherein the length of the one or more additional DM-RS blocks and a location of the one or more additional DM-RS blocks is fixed for different N-FFT block sizes and wherein various mapping types for the one or more DM-RS blocks are predefined in the DM-RS configuration (Jung: fig. 4-5 [0089]; Xiong: fig. 4-5 [0050-0055]; YOSHIMURA: [0023] fig. 7 additional DM-RS blocks). 10. The apparatus of claim 3, wherein the one or more additional DM-RS blocks are used to accommodate multi-port DM-RS (Jung: [0092] QCL configuration may associate two different antenna ports). 11. The apparatus of claim 1, wherein at least one complete time domain block length is dedicated for DM-RS, variable DM-RS densities configured inside the time domain block length to accommodate multi-port DM-RS (Jung: fig. 4-5 [0089]; Xiong: fig. 4-5 [0050-0055]; YOSHIMURA: [0023] fig. 7 - DM-RS blocks). 12. The apparatus of claim 1, wherein, in response to DM-RS not being part of a guard interval, a cyclic prefix is inserted in each DM-RS block to fulfill a cyclic convolutional property (Jung: [0070]; Xiong: fig. 4-5 [0050-0055]; YOSHIMURA: [0023] CyclicPrefixLength). 13. The apparatus of claim 1, wherein the processor is configured to cause the apparatus to trigger a modification in the DM-RS parameters, including a DM-RS duration, a DM-RS type, a DM-RS power, or some combination thereof (Jung: [0168, 0171, 0200] dmrs-type). Regarding claims 14-15, the independent claim and each dependent claim are related to the same limitation set for hereinabove in claims 1-3, where the difference used is a “UE” with a processor and a memory (Jung: Referring to FIG. 22, the wireless device includes a processor 21-05 & transceiver 21-10) and the wordings of the claims were interchanged within the claim itself or some of the claims were presented as a combination of two or more previously presented limitations. This change does not affect the limitation of the above treated claims. Adding these phrases to the claims arid interchanging the wording did not introduce new limitations to these claims. Therefore, these claims were rejected for similar reasons as stated above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sulaiman Nooristany whose telephone number is (571) 270-1929. The examiner can normally be reached on M-F from 9 to 5. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeffrey Rutkowski, can be reached on (571) 270-1215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /SULAIMAN NOORISTANY/Primary Examiner, Art Unit 2415
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Prosecution Timeline

Mar 08, 2024
Application Filed
Feb 12, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+24.4%)
3y 6m
Median Time to Grant
Low
PTA Risk
Based on 911 resolved cases by this examiner. Grant probability derived from career allow rate.

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