DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to Applicant’s preliminary amendment filed on 03/08/2026.
Claims 1-15 are currently pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Soltani et al. (US 2023/0036387 A1; hereafter SOLTANI).
With respect to claim 1, SOLTANI discloses an apparatus (120, UE of FIG. 6) comprising:
a transceiver (258, 264, 280, 282 of FIG. 2); and
a processor (258, 264, 280, 282 of FIG. 2) coupled to the transceiver (258, 264, 280, 282 of FIG. 2), the processor configured to cause the apparatus to:
receive a single-carrier Synchronization Signal Block (“SC-SSB”) structure (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS) from a radio access network, wherein the SC-SSB structure comprises:
a Primary Synchronization Signal (“PSS”) portion comprising a PSS block mapped to a first set of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS):
a Secondary Synchronization Signal (“SSS”) portion comprising a SSS block mapped to a second set of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS); and
a Physical Broadcast Channel (“PBCH”) portion comprising a plurality of PBCH blocks mapped to a third set of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS); and
access a cell using a single-carrier waveform based on the received SC-SSB structure (615 of FIG. 6).
With respect to claim 2, SOLTANI further discloses the apparatus of claim 1, wherein the SC-SSB structure comprises a guard interval inserted between the second and third sets of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS).
With respect to claim 3, SOLTANI further discloses the apparatus of claim 2, wherein the guard interval comprises a random block-wise guard interval (paragraph [0059]).
With respect to claim 4, SOLTANI further discloses the apparatus of claim 2, wherein the guard interval comprises a known demodulation reference signal (“DM-RS”) (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS).
With respect to claim 5, SOLTANI further discloses the apparatus of claim 2, wherein the third set of time-domain symbols comprises a plurality of time-domain blocks, wherein the SC-SSB structure comprises the guard interval inserted between each of the plurality of time-domain blocks (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS).
With respect to claim 6, SOLTANI further discloses the apparatus of claim 2, wherein the SC-SSB structure comprises respective guard intervals inserted at a beginning of each of the first and second sets of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS).
With respect to claim 7, SOLTANI further discloses the apparatus of claim 1, wherein the PSS block comprises a 127 element PSS sequence and the SSS block comprises a 127 element SSS sequence, wherein the PSS block is mapped to a first set of 128 time-domain symbols and the SSS block is mapped to a second set of 128 time-domain symbols (FIG. 7; FIG. 8; paragraphs [0083] and [0092]).
With respect to claim 8, SOLTANI further discloses the apparatus of claim 1, wherein the PSS block comprises a 127 element PSS sequence and the SSS block comprises a 127 element SSS sequence, wherein the PSS block is mapped to a first set of 256 time-domain symbols and the SSS block is mapped to a second set of 256 time-domain symbols (FIG. 7; FIG. 8; paragraphs [0083] and [0092]).
With respect to claim 9, SOLTANI further discloses the apparatus of claim 1, wherein the PSS block is mapped to a first set of 128 time-domain symbols, wherein the SSS block is mapped to a second set of 128 time-domain symbols, and wherein the plurality of PBCH blocks are mapped to multiple sets of 128 time-domain symbols (FIG. 7; FIG. 8; paragraphs [0083] and [0092]).
With respect to claim 10, SOLTANI further discloses the apparatus of claim 1, wherein the PSS block is mapped to a first set of 128 time-domain symbols, wherein the SSS block is mapped to a second set of 128 time-domain symbols, and wherein the plurality of PBCH blocks are mapped to multiple sets of 256 time-domain symbols (FIG. 7; FIG. 8; paragraphs [0083] and [0092]).
With respect to claim 11, SOLTANI further discloses the apparatus of claim 1, wherein the PSS block and the SSS block are mapped to a common time-domain block (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS).
With respect to claim 12, SOLTANI further discloses the apparatus of claim 11, wherein the PSS block and/or the SSS block comprises a demodulation reference signal (“DM-RS”) (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS).
With respect to claim 13, SOLTANI further discloses the apparatus of claim 1, wherein the processor is further configured to cause the apparatus to receive a master information block (“MIB”) comprising parameters restricted to the time domain (paragraph [0078]).
With respect to claim 14, SOLTANI discloses a method (Title; Abstract) of a User Equipment (“UE”) (120, UE of FIG. 6), the method comprising:
receiving a single-carrier Synchronization Signal Block (“SC-SSB”) structure (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS) from a radio access network, wherein the SC-SSB structure comprises:
a Primary Synchronization Signal (“PSS”) portion comprising a PSS block mapped to a first set of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS):
a Secondary Synchronization Signal (“SSS”) portion comprising a SSS block mapped to a second set of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS); and
a Physical Broadcast Channel (“PBCH”) portion comprising a plurality of PBCH blocks mapped to a third set of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS); and
accessing a cell using a single-carrier waveform based on the received SC-SSB structure (615 of FIG. 6).
With respect to claim 15, SOLTANI discloses an apparatus (110, base station of FIG. 6) comprising:
a transceiver (238, 220, 240, 242 of FIG. 2); and
a processor (238, 220, 240, 242 of FIG. 2) coupled to the transceiver (238, 220, 240, 242 of FIG. 2), the processor configured to cause the apparatus to:
transmit a single-carrier Synchronization Signal Block (“SC-SSB”) structure, wherein the SC-SSB structure (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS) comprises:
a Primary Synchronization Signal (“PSS”) portion comprising a PSS block mapped to a first set of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS);
a Secondary Synchronization Signal (“SSS”) portion comprising a SSS block mapped to a second set of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS); and
a Physical Broadcast Channel (“PBCH”) portion comprising a plurality of PBCH blocks mapped to a third set of time-domain symbols (605, SSB by SC-QAM waveform; 610, PSS, SSS, PBCH, DMRS); and
receive a connection request (615 of FIG. 6) from a User Equipment (“UE”) (120, UE of FIG. 6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian T O'Connor whose telephone number is (571)270-1081. The examiner can normally be reached Mon-Fri Flex 10am-6:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Gary Mui can be reached at 571-270-1420. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRIAN T O CONNOR/Primary Examiner, Art Unit 2465 April 1, 2026
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