DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed June 26, 2024, fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. References A4-A5, A7, and A9 have been placed in the application file, but the information referred to therein has not been considered.
The term counterpart foreign patent application means that a claim for priority has been made in either the U.S. application or a foreign application based on the other, or that the disclosures of the U.S. and foreign patent applications are substantively identical (e.g., an application filed in the European Patent Office claiming the same U.K. priority as claimed in the U.S. application). Note that an international application filed under the Patent Cooperation Treaty, which designates the U.S., is not a counterpart foreign application. See MPEP 609.04(b)(V).
JP 2018-42089, listed in the specification but not on an IDS, has not been considered by the examiner. See MPEP § 609.04(a).
Applicant is advised that the date of any resubmission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Drawings
The drawings were received on March 11, 2024. These drawings are acceptable.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-8 are objected to because of the following informalities:
Claim 1 recites, “an electronic component is mounted… at least two component mounting parts on which the electronic component is mounted”.
It is unclear how “an electronic component” may be mounted on two separate substrates.
A review of the specification provides “electronic components” mounted on the substrates.
It is suggested the claim be amended to recite, “a plurality of electronic components” (or similar language).
Claim 1 line 4 sets forth “at least two component mounting parts”. Lines 6-7 recite, “adjacent two of the component mounting parts”.
To avoid ambiguity:
Claim 1 lines 8 and 9 should each recite, “each of the adjacent two component mounting parts”.
Claim 1 lines 10-11 should recite, “one of the adjacent component mounting parts”.
Claim 1 line 13 and claims 2 and 3 should each recite, “the two adjacent component mounting parts”.
Claim 2 recites, “the power source positive electrode wirings of one layer” and “the signal wirings of another layer” but these limitations lack express antecedent bases.
Claim 4 recites, “ two control circuit ground wirings” but claim 3 only sets forth “a control circuit ground wiring’.
It is suggested claim 4 be amended set forth an additional control circuit ground wiring, as claims 5-7 each recite, “the control circuit ground wiring”.
The remaining claims are objected to by reason of their dependency.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication 2020/0321839 to Tateyama et al. (hereinafter Tateyama) in view of US Publication 2017/0149111 to Yosui et al. (hereinafter Yosui).
Claim 1
Tateyama (FIG. 3, 8-9) discloses an electronic device comprising a multilayer circuit substrate on which an electronic component is mounted,
wherein the circuit substrate (3, paragraph 23-24) includes:
at least two component mounting parts (11-12, paragraph 25) on which the electronic component (paragraph 25) is mounted;
a flexible part (13, paragraph 25) positioned between adjacent two of the component mounting parts (11-12) and formed to be thinner (paragraph 29) than a thickness of a substrates of each of the component mounting parts (11-12) so as to have higher flexibility than that of each of the component mounting parts (11-12);
a power source input terminal (40, paragraph 41) provided on one of the component mounting parts (11), as recited in claim 1.
Tateyama does not expressly disclose at least two power source positive electrode wirings extending between the two component mounting parts in the flexible part to supply power to one of the component mounting parts to which the power source input terminal is not provided, provided to respective layers different from each other, and arranged at respective positions at which they are at least partially superimposed on each other when being projected in a lamination direction of the circuit substrate, as recited in claim 1.
Yosui (FIG. 3-4) teaches at least two power source positive electrode wirings (41-43, paragraph 62) extending in a flexible part (1, paragraph 52) to supply power, provided to respective layers (12-14) different from each other, and arranged at respective positions at which they are at least partially superimposed (FIG. 3-4) on each other when being projected in a lamination direction of the circuit substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Yosui with Tateyama to incorporate a multilayer flexible conductor arrangement as taught by Yosui in the structure taught by Tateyama and thereby utilize the multilayer teachings of Yosui in the flexible part of Tateyama, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for the combined transmission of power and signals with an increased number of power transmission conductor patterns to reduce conductor loss (Yosui paragraph 11-12) while maintaining a narrower flexible part.
Claim 2
Tateyama with Yosui teaches the electronic device according to claim 1, wherein the flexible part (Tateyama 13) further includes a plurality of signal wirings (FIG. 8: 51) extending between the two component mounting parts (11-12), and
wherein the power source positive electrode wirings (Yosui 41-43) of one layer and the signal wirings of another layer (Yosui FIG. 4: signal pattern 32, paragraph 62) are positioned so as not to be superimposed on each other (as shown in Yosui FIG. 4).
Claim 3
Tateyama with Yosui teaches the electronic device according to claim 1, wherein the flexible part (Tateyama 13) further includes a voltage signal wiring (FIG. 8: 51, paragraph 54), a high voltage gate signal wiring (52, paragraph 55), a control circuit ground wiring (FIG. 9: 54, paragraph 56) and an inverter circuit ground wiring (56) extending between the two component mounting parts (11-12), and
wherein, in a same layer, the power source positive electrode wirings (Yosui 41-43) are not adjacent to the low voltage signal wiring (Yosui FIG. 4: signal pattern 32, paragraph 62).
Claim 8
Tateyama with Yosui teaches the electronic device according to claim 1, wherein the circuit substrate (3) includes at least two control systems (Tateyama paragraph 58),
wherein the power source positive electrode wirings are provided to each of the control systems (Yosui 41-43), and
wherein each of the power source positive electrode wirings (41-43) of the control systems includes at least two power source positive electrode wirings (41-43) superimposed on each other in the lamination direction in the flexible part (Yosui FIG. 15).
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Tateyama with Yosui in view of CN Publication 205385652 to Dai (hereinafter Dai; see also provided machine translation).
Claim 4
Tateyama with Yosui teaches the electronic device according to claim 3, as shown above.
Tateyama does not expressly disclose wherein, in a same layer, the power source positive electrode wirings are each positioned between two control circuit ground wirings, as recited in claim 4.
Dai (FIG. 3-5, 7) teaches power wirings (1215) are positioned between ground wirings (1214) in a same layer (see also FIG. 7: 145 positioned between 144).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Dai with Tateyama with Yosui to incorporate power wirings between two ground wirings on a same layer as taught by Dai in the structure taught by Tateyama with Yosui, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for better isolation of noise from the power source positive electrode wirings to signal wirings.
Claim 5
Tateyama with Yosui teaches the electronic device according to claim 3, as shown above.
Tateyama does not expressly disclose wherein, in a same layer, the power source positive electrode wirings are each positioned between the high voltage gate signal wiring and the control circuit ground wiring, as recited in claim 5.
Dai (FIG. 3-5, 7) teaches power wirings (1215) are positioned between ground wirings (1214) and signal wirings (1211-1212)(see also FIG. 7: 145 positioned between 144 and 141).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Dai with Tateyama with Yosui to incorporate power wirings between ground and signal wirings on a same layer as taught by Dai in the structure taught by Tateyama with Yosui, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for better isolation of noise from one pair of signal lines to a different pair of signal lines.
Claim 6
Tateyama with Yosui teaches the electronic device according to claim 3, as shown above.
Tateyama does not expressly disclose wherein, in a same layer, the power source positive electrode wirings are each positioned between the control circuit ground wiring and the inverter circuit ground wiring, as recited in claim 6.
Dai (FIG. 3-5, 7) teaches power wirings (1215) are positioned between ground wirings (1214) in a same layer (see also FIG. 7: 145 positioned between 144).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Dai with Tateyama with Yosui to incorporate power wirings between ground wirings on a same layer as taught by Dai in the structure taught by Tateyama with Yosui, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for better isolation of noise from the power source positive electrode wirings to signal wirings.
Claim 7
Tateyama with Yosui teaches the electronic device according to claim 3, as shown above.
Tateyama does not expressly disclose wherein, when the flexible part is projected along the lamination direction of the circuit substrate, in a positional relationship in a width direction of the flexible part, the high voltage gate signal wiring and the inverter circuit ground wiring are positioned on inner sides of the power source positive electrode wirings, and the low voltage signal wiring and the control circuit ground wiring are positioned on inner sides of the high voltage gate signal wiring and the inverter circuit ground wiring, as recited in claim 7.
Such an arrangement, however, would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in view of the teachings of Dai (FIG. 3-5, 7) to utilize ground, power, and signal wirings, in pairs to reduce noise and isolate the signal wirings from different grounds. Additionally, such a rearrangement of parts would not modify the operation of the device and are an obvious matter of design choice. See MPEP 2144. VI.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN MILAKOVICH whose telephone number is (571) 270-3087. The examiner can normally be reached Monday - Friday 9:00 AM - 5:00 PM EST.
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/NATHAN MILAKOVICH/Primary Examiner, Art Unit 2848