CTNF 18/691,872 CTNF 100358 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending and have been examined. Claim Rejections - 35 USC § 102 The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action: (a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless— 07-08-aia AIA (1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention; Notes : when present, hyphen separated fields within the hyphens (- -) represent, for example, as ( 30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document. The following is a quotation of 35 U.S.C. 102(a)(2) that forms the basis for the rejection set forth in this Office action: (a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless— 07-12-aia AIA (2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Notes : when present, hyphen separated fields within the hyphens (- -) represent, for example, as ( 30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document. Claims 1-3, 6-7, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leng (CN 108598142 A – hereinafter Leng). Regarding independent claim 1 , Leng teaches: (Original) A display panel ([0002] – “This invention relates to the field of display technology, and more particularly to a flexible display substrate, a flexible display panel, and a flexible display device” – hereinafter ‘FDP’) comprising: a display region (31 – Fig. 5 – [0068] – “display area 31”) and a peripheral region (32 – Fig. 5 – [0053] – “a non-display area 32”) located at a side of the display region (31) , wherein the peripheral region (32) comprises a bending region (321 – Fig. 5 – [0061] – “bending area 321”) and a fan-out region (322 – Fig. 5 – [0061] – “fan-out area 222”) ; the fan-out region (322) is located at a side of the bending region (321) away from the display region (31) ; the display panel (FDP) comprises: a base substrate (30 – Fig. 5 – [0060] – “substrate 30”) , circuit units (P – Fig. 2 – [0052] – “multiple sub-pixels P include multiple pixel rows”) arranged in an array (Fig. 2 shows an array of P) and provided on the base substrate (30) , a plurality of data signal lines (Data – Fig. 2 – [0052] – “multiple data lines Data”) extending along a first direction (Y – Fig. 2 – [0052] – “extension direction of the data lines Data is the column direction Y”) , and a plurality of data fan-out lines (2220 – Fig. 2 – [0053] – “fan-out area 222 includes multiple metal lines 2220” – these connect to Data lines as shown) located in the fan-out region (222 – Fig. 2 – [0053] – “fan-out area 222”) ; the data signal lines (Data) extend from the display region (21 – Fig. 2 – [0052] – “Display area 21”) to at least the bending region (221 – Fig. 2 – [0053] – “bending area 221”) , and are electrically connected with the circuit units (P) and the data fan-out lines (2220 – {[0056]- “the data line Data directly enters the bending area 221 from the display area 21 and is connected to the bending line 2210 in the bending area 221”}, {0053] – “metal lines 2220 are electrically connected to at least a portion of the bending lines 2210”} – Fig. 2 shows this) , respectively. Regarding claim 2 , Leng teaches claim 1 from which claim 2 depends. Leng further teaches (Original) The display panel according to claim 1, further comprising: a plurality of high-voltage power supply lines (PVDD – Fig. 5 – [0086] – “the high-level power supply line PVDD that transmits the high-level signal is the first power supply line”) extending along the first direction (F – Fig. 5 – [0061] – “first direction F”) , wherein at least one high-voltage power supply line (PVDD) extends from the display region (31 – Fig. 5 – [0060] – “display area 31”) to the fan-out region (322 – Fig. 5 – [0061] – “fan-out area 322”) ; a plurality of circuit units (P) extending along the first direction (F) are a column of circuit units ([0061] – “”column of pixels) , one high-voltage power supply line (PVDD) is electrically connected with a column of circuit units ([0088] – “the high-level power line PVDD, which is led out from the display area and connected to multiple columns of pixels”) , and the at least one high-voltage power supply line (PVDD) is electrically connected with a plurality of columns of circuit units ([0088] – “the high-level power line PVDD, which is led out from the display area and connected to multiple columns of pixels”) . Regarding claim 3 , Leng teaches claim 2 from which claim 3 depends. Leng further teaches (Original) The display panel according to claim 2, further comprising: a plurality of light emitting devices (OLED – [0065] – “OLED device”) and a plurality of low-voltage power supply lines (PVEE – Fig. 5 – {[0070] – “the second power line PVEE of the display area is a line led out from the entire OLED cathode and is located on the same layer as the OLED cathode”}, {[0061] – “second metal wire 3242 is used to connect multiple second power lines together”}, {[0061] – “second power line is any metal line that provides and transmits low-level signal PVEE to the cathode”}) extending along the first direction (F) , wherein the low-voltage power supply lines (PVEE) extend from the display region (31) to the fan-out region (322 – Fig. 5 shows this) , and the circuit unit ([0065] – “the control circuit of the OLED device”) are electrically connected to the light emitting devices (OLED – [0070] – “the second power line PVEE of the display area is a line led out from the entire OLED cathode and is located on the same layer as the OLED cathode” – this is interpreted as electrically connected) ; the plurality of low-voltage power supply lines (PVEE) are electrically connected with cathodes ([0086] – “the electrical connection between the second metal composite line 3242, which transmits the low-level power supply voltage PVEE, and the cathode is achieved through the fifth crossover line 3248”) of the light emitting devices (OLED) connected to a plurality of columns of circuit units (PVEE is connected to each OLED cathode that are in each circuit unit that are in a column) . Regarding claim 6 , Leng teaches claim 3 from which claim 6 depends. Leng further teaches (Currently amended) The display panel according to claim 3 any one of claims 3 to 5 , further comprising: a high-voltage signal line (3241 – Fig. 4 – [0061] – “first metal wire 3241 is used to electrically connect multiple first power lines together”) located in the fan-out region (322) and extending along a second direction (S – Fig. 4 – [0061] – “second direction S”) , wherein the first direction (F) intersects with the second direction (S – [0061] – “second direction S is perpendicular to the first direction F” – Fig. 5 shows this) ; the high-voltage signal line (3241) is electrically connected with at least one high-voltage power supply line (PVDD – [0061] – “first metal wire 3241 is used to electrically connect multiple first power lines together” – PVDD is the first metal wire) extending to the fan-out region (322) , and an orthographic projection of the high-voltage signal line (3241) on the base substrate (30) is overlapped with orthographic projections of the data fan-out lines (3244 – Fig. 4 – [0062] – “One end of each third bend line 3213 is electrically connected to a data line or display area scan line of a column of sub-pixels, and the other end is electrically connected to a metal line of the fan-out area 322 via a second crossover line 3244” – this is an extension of the Data line) on the base substrate (30 – Fig. 4 shows this) ; a length of the high-voltage signal line (3241) along the first direction (F) is greater than lengths of the high-voltage power supply lines (3211 – Fig. 4 – [0062] – “one end of each first bending line 3211 is electrically connected to the high level power line PVDD located in the display area 31 of a column of sub-pixels, and the other end is electrically connected to the first metal composite line 3241” – this is an extension of PVDD) along the second direction (S – Fig. 4 shows this) . Regarding claim 7 , Leng teaches claim 6 from which claim 7 depends. Leng further teaches (Original) The display panel according to claim 6, further comprising: a low-voltage signal line (3242 – Fig. 4 – [0061] – “second metal wire 3242 is used to connect multiple second power lines together”) located in the fan-out region (322) and extending along the second direction (S – [0061] – “second metal wire 3242 that extend along the second direction S”) ; the low-voltage signal line (3242) is electrically connected with a plurality of low-voltage power supply lines (PVEE – [0061] – “second metal wire 3242 is used to connect multiple second power lines together” – PVEE is the second power line) , and an orthographic projection of the low-voltage signal line (3242) on the base substrate (30) is overlapped with the orthographic projections of the data fan-out lines (3244 – Fig. 4 – [0062] – “One end of each third bend line 3213 is electrically connected to a data line or display area scan line of a column of sub-pixels, and the other end is electrically connected to a metal line of the fan-out area 322 via a second crossover line 3244” – this is an extension of the Data line) on the base substrate (30 – Fig. 4 shows this) ; a length of the low-voltage signal line (3242) along the first direction (F) is greater than lengths of the low-voltage power supply lines (PVEE) along the second direction (S – Fig. 4 shows this) . Regarding claim 17 , Leng teaches claim 1 from which claim 17 depends. Leng further teaches (Currently amended) A display apparatus, comprising: the display panel ([0002] – “This invention relates to the field of display technology, and more particularly to a flexible display substrate, a flexible display panel” – hereinafter ‘DP’) according to claim 1 any one of claims 1 to 16 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Notes : when present, hyphen separated fields within the hyphens (- -) represent, for example, as ( 30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document. 07-21-aia AIA Claim s 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Leng in view of Park et al. (US 20200365077 A1 – hereinafter Park) . Regarding claim 4 , Leng teaches claim 3 from which claim 7 depends. Leng does not expressly disclose the limitations of claim 4. However, in an analogous art, Park teaches (Original) The display panel according to claim 3, wherein a number of high-voltage power supply lines (172 – Fig. 1 – [0059] – “driving voltage line 172” – this corresponds to a high-voltage line) extending to the fan-out region (Fig. 1 annotated, see below, shows this – hereinafter ‘FOR’) and a number of low-voltage power supply lines (173 – Fig. 1 – [0059] – “initialization voltage line 173” – this corresponds to a low-voltage line) extending to the fan-out region (FOR) are equal to a number of data signal lines (171 – Fig. 1 – [0059] – “data line 171”) , respectively; an i-th high-voltage power supply line (172) and an i-th low-voltage power supply line (173) are located at opposite sides of an i-th data signal line (171 – Fig. 1 annotated, see below, shows this) , respectively, wherein 1≤i≤N and N is a number of data signal lines (171) . PNG media_image1.png 730 1167 media_image1.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the number of lines as taught by Park into Leng. An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of [0027] – “it may be possible to reduce the resistance of the wires, for example of the power voltage line such as the driving voltage line and the common voltage line, and the voltage drop of the power voltage transferred through the power voltage line. The display quality may be improved, and a margin of the power voltage may be reduced, thereby reducing the power consumption. It may also be possible to reduce a delay of signals such as data signals.” Regarding claim 18 , Leng, as modified by Park, teaches claim 4 from which claim 18 depends. Leng further teaches (New) The display panel according to claim 4, further comprising: a high-voltage signal line (3241 – Fig. 4 – [0061] – “first metal wire 3241 is used to electrically connect multiple first power lines together”) located in the fan-out region (322) and extending along a second direction (S) , wherein the first direction (F) intersects with the second direction (S – [0061] – “second direction S is perpendicular to the first direction F” – Fig. 5 shows this) ; the high-voltage signal line (3241) is electrically connected with at least one high-voltage power supply line (PVDD – [0061] – “first metal wire 3241 is used to electrically connect multiple first power lines together” – PVDD is the first metal wire) extending to the fan-out region (322) , and an orthographic projection of the high-voltage signal line (3241) on the base substrate (30) is overlapped with orthographic projections of the data fan-out lines (3244 – Fig. 4 – [0062] – “One end of each third bend line 3213 is electrically connected to a data line or display area scan line of a column of sub-pixels, and the other end is electrically connected to a metal line of the fan-out area 322 via a second crossover line 3244” – this is an extension of the Data line) on the base substrate (30 – Fig. 4 shows this) a length of the high-voltage signal line (3241) along the first direction (F) is greater than lengths of the high-voltage power supply lines (3211 – Fig. 4 – [0062] – “one end of each first bending line 3211 is electrically connected to the high level power line PVDD located in the display area 31 of a column of sub-pixels, and the other end is electrically connected to the first metal composite line 3241” – this is an extension of PVDD) along the second direction (S – Fig. 4 shows this) . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Leng in view of Lee et al. (US 20240096277 A1 – hereinafter Lee) . Regarding claim 8 , Leng teaches claim 7 from which claim 8 depends. Leng further teaches in the fan-out region (322) , the low-voltage signal line (3242) is located at a side of the high-voltage signal line (3241) away from the bending region (321 – Fig. 5 shows this) . Leng does not expressly disclose the other limitations of claim 8. However, in an analogous art, Lee teaches (Original) The display panel according to claim 7, wherein the low-voltage signal line (14c – Fig. 2A – [0011] – “ground line 14c” – this corresponds to the low-voltage signal line) and the high-voltage signal line (14a – Fig. 2A – [0011] – “driving voltage line 14a” – this corresponds to the high-voltage signal line) are arranged in different layers ([0016] – “the power lines 14a-14c and the signal lines GSL, DSL are formed on different layers, in order to prevent short-circuiting when the wires cross each other” – Fig. 2A shows this) ; in the fan-out region, the low-voltage signal line is located at a side of the high-voltage signal line away from the bending region. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the voltage signal line structure as taught by Lee into Leng. An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result (0016] – “in order to prevent short-circuiting when the wires cross each other.” 07-21-aia AIA Claim s 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Leng in view of Lee, Kim et al. (US 20190074332 A1 – hereinafter Kim), and Kwon et al. (US 20180083072 A1 – hereinafter Kwon) . Regarding claim 9 , Leng, as modified by Lee, teaches claim 7 from which claim 8 depends. Leng and Lee do not expressly disclose the limitations of claim 9. However, in an analogous art, Kim teaches (Original) The display panel according to claim 8, wherein the peripheral region (ZA – Fig. 1 – [0052] – “bezel area ZA” – this corresponds to the peripheral region) further comprises: a bending transition region (LA – Fig. 1 – [0052] – “link area LA” – this corresponds to a bending transition regio) located between the display region (AA – Fig. 1 – [0052] – “active area AA” – this corresponds to the display region) and the bending region (BA – Fig. 1 – [0052] – “bending area BA”). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the transition region structure as taught by Kim into Leng and Lee. An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0055] – “an area where link lines transmitting signals to wiring lines disposed in the active area AA can be disposed and various link lines can be disposed therein” thus providing space between the bending area and the display area. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc. , 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. Leng, Lee, and Kim do not expressly disclose the other limitations of claim 9. However, in an analogous art, Kwon teaches the data signal lines (DL2 – Fig. 11 – [0198] – “data line DL2”) comprise: a first data signal line (DL2a – Fig. 11 – [0198] – “data line DL2a is on the third insulating layer INS3 in the display area DA”) located at least in the display region (DA – Fig. 11 – [0198] – “display area DA”) , a second data signal line (DL2b – Fig. 11 – [0198] – “fan-out line DL2b is on the first insulating layer INS1 in the fan-out area FTA”) located at least in the bending transition region (FTA – Fig. 11 – [0198] – “fan-out area FTA” – this corresponds to the transition area) and a third data signal line (DL2c – Fig. 11 – [0198] – “link line DL2c is on the bent-part insulating layer INS_B in the bent area BA”) located at least in the bending region (BA – Fig. 11 – [0194] – “bent area BA”) ; the second data signal line (DL2b – Fig. 11 – [0198] – “fan-out line DL2b is on the first insulating layer INS1”) is arranged in a layer different from the first data signal line (DL2a – Fig. 11 – [0198] – “data line DL2a is on the third insulating layer INS3”) and the third data signal line (DL2c – Fig. 11 – [0198] – “link line DL2c is on the bent-part insulating layer INS_B”) , respectively, the third data signal line (DL2c – Fig. 11 – [0198] – “link line DL2c is on the bent-part insulating layer INS_B”) and a data fan-out line (BR – Fig. 11 – [0198] – “bridge pattern BR is on the third insulation layer INS3 in the fan-out area FTA”) are arranged in different layers, an orthographic projection of the second data signal line (DL2b) on the base substrate (SUB – Fig. 12B – [0034] – “substrate SUB”) is partially overlapped (Fig. 12B shows this) with an orthographic projection of the first data signal line (DL2a) and an orthographic projection of the third data signal line (DL22) on the base substrate (SUB – Fig. 12B shows this) , respectively, the orthographic projection of the third data signal line (DL2c) on the base substrate (SUB) is partially overlapped (Fig. 12B shows this) with the orthographic projection of the data fan-out line (BR) on the base substrate (SUB) , the second data signal line (DL2b) is electrically connected with the first data signal line (DL2a) and the third data signal line (DL2c) , respectively, the first data signal line (DL2a) is electrically connected with the circuit units ({[0131] – “data line DL2 coupled to the second pixel column”}, {[0116] – “data lines DL2 may include second pixel-unit data lines DL2a in the display area DA”) , and the third data signal line (DL2c) is electrically connected with the data fan-out line (BR – Fig. 12B shows this) . Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the data signal line structure as taught by Kwon into Leng, Lee, and Kim. An ordinary artisan would have been motivated to use the known technique of Kwon in the manner set forth above to produce the predictable result of [0075] – “the substrate SUB may be made of material having flexibility so as to be bendable or foldable, and have a single layer or multilayer structure.” Regarding claim 10 , Leng, as modified by Lee, Kim, and Kwon, teaches claim 9 from which claim 10 depends. Leng further teaches (Original) The display panel according to claim 9, wherein the high- voltage power supply lines (PVDD) comprise: a first high-voltage power supply line (Fig 5. annotated, see below – hereinafter ‘PVDD1’”) located at least in the display region (31) , a second high-voltage power supply line (3214 – Fig. 5 – {[0069] – “bending line 3214 is electrically connected to a third metal composite line 3247”}, {[0068] – “metal bonding line 3247 is used to electrically connect the power lines of the high-level signal PVDD”) located at least in the bending transition region (Fig. 5 annotated, see below – [0069] – “third metal bonding line 3247 is located between the bending area 321 and the display area 31” – this corresponds to the transition region, hereinafter ‘3247TR’) , and a third high-voltage power supply line (Fig. 5 annotated, see below – [0069] – “bending line 3214 is electrically connected to a third metal composite line 3247, and the other end is electrically connected to a first metal composite line 3241” – hereinafter ‘63’) located at least in the bending region (321) and the fan-out region ; the second high-voltage power supply line is arranged in a layer different from the first high-voltage power supply line and the third high-voltage power supply line, respectively, the third high-voltage power supply line is arranged in a same layer with the high-voltage signal line, an orthographic projection of the second high-voltage power supply line on the base substrate is partially overlapped with an orthographic projection of the first high-voltage power supply line on the base substrate and an orthographic projection of the third high-voltage power supply line on the base substrate, respectively, the second high-voltage power supply line is electrically connected with the first high-voltage power supply line and the third high-voltage power supply line, respectively, the first high-voltage power supply line is electrically connected with the circuit units, and the third high-voltage power supply line is electrically connected with the high-voltage signal line. PNG media_image2.png 782 628 media_image2.png Greyscale Leng, Lee, and Kim do not expressly disclose the other limitations of claim 10. However, in an analogous art, Kwon teaches the technique describing the limitations of the instant application for a data line. This know technique can be applied to the high-voltage power line in same way. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the high-voltage power supply line structure as taught by Kwon into Leng, Lee, and Kim. An ordinary artisan would have been motivated to use the known technique of Kwon in the manner set forth above to produce the predictable result of [0075] – “the substrate SUB may be made of material having flexibility so as to be bendable or foldable, and have a single layer or multilayer structure.” To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc. , 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. Regarding claim 11 , Leng, as modified by Lee, Kim, and Kwon, teaches claim 10 from which claim 11 depends. Leng further teaches (Original) The display panel according to claim 10, wherein the low- voltage power supply lines (PVEE) comprise: a first low-voltage power supply line (3215 – Fig. 5 – [0069] – “bending line 3215”) located at least in the display region (31) and the bending transition region (BTR) and a second low-voltage power supply line (3245) located at least in the bending region (321) and the fan-out region; the first low-voltage power supply line and the second low-voltage power supply line are arranged in different layers, the second low-voltage power supply line and the low-voltage signal line are arranged in a same layer, an orthographic projection of the first low-voltage power supply line on the base substrate is partially overlapped with orthographic projections of cathodes of the light emitting devices on the base substrate and an orthographic projection of the second low-voltage power supply line on the base substrate, respectively, the first low-voltage power supply line is electrically connected with the cathodes of the light emitting devices and the second low-voltage power supply line, respectively, and the second low-voltage power supply line is electrically connected with the low-voltage signal line. Leng, Lee, and Kim do not expressly disclose the other limitations of claim 11. However, in an analogous art, Kwon teaches the technique describing the limitations of the instant application for a data line. This know technique can be applied to the low-voltage power line in same way. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the low-voltage power supply line structure as taught by Kwon into Leng, Lee, and Kim. An ordinary artisan would have been motivated to use the known technique of Kwon in the manner set forth above to produce the predictable result of [0075] – “the substrate SUB may be made of material having flexibility so as to be bendable or foldable, and have a single layer or multilayer structure.” To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc. , 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D . 07-21-aia AIA Claim s 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Leng in view of Lee, Kim, Kwon, and Kim (US 20230299120 A1 – hereinafter Kim-120) . Regarding claim 12 , Leng, as modified by Lee, Kim, and Kwon, teaches claim 11 from which claim 12 depends. Leng further teaches a high-voltage signal line (3241) and a low-voltage signal line (3242). Leng, Lee, and Kim do not expressly disclose the other limitations of claim 12. However, in an analogous art, Kwon teaches (Original) The display panel according to claim 11, further comprising: a drive circuit layer (Fig. 5 annotated, see below – hereinafter ‘DCL’) and a light emitting structure layer ([0101] – “organic light-emitting layer OL may be provided on the pixel (PXL) region enclosed by the pixel defining layer PDL” – this is part of the light emitting structure, hereinafter ‘OLED’ – Fig. 5 shows this) arranged on the base substrate (SUB) , wherein the drive circuit layer (DCL) is provided with a circuit unit (PXL – Fig. 5 – [0057] – “each pixel PXL may include one thin transistor and one capacitor, or three or more thin film transistors and two or more capacitors”) , a data signal line (DL2 – [0116] – “second data lines DL2 may include second pixel-unit data lines DL2a in the display area DA, second fan-out lines DL2b in the fan-out area FTA, and second link lines DL2c in the bent area BA” – Fig. 4 shows this) , a data fan-out line (DL2b – Fig. 4 – [0116] – “fan-out lines”) , a high-voltage power supply line (ELVDD – {[0059] – “first power line ELVDD”}, {[0089] – “data lines DL or first power lines may be in the same layer as that of the source electrode SE and the drain electrode DE and formed of the same material as them. The data lines DL or the first power lines may be directly or indirectly coupled to a portion (e.g., the source electrode SE and/or the drain electrode DE) of the transistor in each pixel PXL”}) , a low-voltage power supply line (ELVSS – {[0060] – “second power line ELVSS”) , a high-voltage signal line and a low-voltage signal line , the light emitting structure layer (OLED) is provided with a light emitting device (OL – Fig. 5 – [0101] – “organic light-emitting layer OL may be provided on the pixel (PXL) region enclosed by the pixel defining layer PDL”) , and the drive circuit layer comprises a first conductive, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially stacked on the base substrate; the first data signal line (DL2a) is located in the third conductive layer and/or the fourth conductive layer (Fig. 12B shows DL2a in the third conductive layer) , the second data signal line (DL2b) is located in the first conductive layer or the second conductive layer (Fig. 12B shows DL2b in the second conductive layer) , the third data signal line (DL2c) is located in the third conductive layer or the fourth conductive layer (Fig. 12B shows DL2c in the fourth conductive layer) , and the data fan-out line (BR) is located in the first conductive layer or the second conductive layer. PNG media_image3.png 445 824 media_image3.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the drive circuit layer and signal line structure as taught by Kwon into Leng, Lee, and Kim. An ordinary artisan would have been motivated to use the known technique of Kwon in the manner set forth above to produce the predictable result of [0075] – “the substrate SUB may be made of material having flexibility so as to be bendable or foldable, and have a single layer or multilayer structure.” Kwon does not expressly disclose the location of the data fan-out line being in a conductive layer below the data signal line. However, using the know technique of the other location of the other lines, it would have been obvious to place it in the lower location to obtain the know predictable result as stated above. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc. , 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. Leng, Lee, Kim, and Kwon do not expressly disclose the other limitations of claim 12. However, in an analogous art, Kim-120 teaches the drive circuit layer (Fig. 10M annotated, see below – hereinafter ‘DCL’) comprises a first conductive layer (CL1 – Fig. 10M – [0138] – “first conductive layer CL1”) , a second conductive layer (CL2 – Fig. 10M – [0138] – “second conductive layer CL2”) , a third conductive layer (CL3 – Fig. 10M – [0138] – “third conductive layer CL3”) and a fourth conductive layer (CL4 – Fig. 10M – [0138] – “fourth conductive layer CL4”) which are sequentially stacked on the base substrate (SUB – Fig. 10M – [0137] – “First to fourth conductive layers CL1 to CL4 sequentially stacked on each other may be provided and/or formed on the substrate SUB”) . PNG media_image4.png 765 1100 media_image4.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the drive circuit layer structure as taught by Kim-120 into Leng, Lee, Kim, and Kwon. An ordinary artisan would have been motivated to use the known technique of Kim-120 in the manner set forth above to produce the predictable result of [0022] – “components included in a pixel circuit part and components included in a display element part may be formed through the same process, thereby simplifying a manufacturing process of a display device.” Regarding claim 13 , Leng, as modified by Lee, Kim, Kwon, and Kim-120, teaches claim 12 from which claim 13 depends. Leng, Lee, Kim, and Kim-120 do not expressly disclose the limitations of claim 12. However, in an analogous art, Kwon teaches the technique describing the limitations of the instant application for a data line. This know technique can be applied to the high-voltage power line in same way. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the high-voltage power supply line structure as taught by Kwon into Leng, Lee, and Kim. An ordinary artisan would have been motivated to use the known technique of Kwon in the manner set forth above to produce the predictable result of [0075] – “the substrate SUB may be made of material having flexibility so as to be bendable or foldable, and have a single layer or multilayer structure.” To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc. , 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. Regarding claim 15 , Leng, as modified by Lee, Kim, Kwon, and Kim-120, teaches claim 13 from which claim 15 depends. Leng further teaches (Currently amended) The display panel according to claim 13 or 14 , wherein the peripheral region (32) further comprises: a drive chip bonding region (323 – fig. 5 – [0088] – “multiple metal lines in the fan-out area 322 are then connected to the control chip (IC) or control circuit board (PCB) in the bonding area 323”) located at a side of the fan-out region (322) away from the display region (31 – Fig. 5 shows this) , the drive chip bonding region (323) comprises: a control chip (IC – [0088] – “the control chip (IC)”). Leng, Kim, Kwon, and Kim-120 do not expressly disclose the other limitations of claim 14. However, in an analogous art, Lee teaches and the display panel (100 – Fig. 4 – [0065] – “flexible OLED display device 100”) further comprises: at least one high-voltage connection line (146b – Fig. 4 – [0073] – “driving voltage lines 146a, 146b may be formed in the lower end non-active area (N/A), and may output a driving voltage (VDD) provided from the data driving portion 230 to the pixel (P) in the active area (A/A)” – this is the section of 146b in the display area A/A, hereinafter ‘146bCL’) extending along the first direction ([Claim 1] – “first power supply voltage lines including at least a first portion extending in a first direction” – hereinafter ‘FD’) and at least one low-voltage connection line (145b – Fig. 4 – [0077] – “ground lines 145a, 145b may be formed in the lower end non-active area (N/A), and may output a ground voltage (GND) provided from the data driving portion 230 to the pixel (P) in the active area (A/A)” – this is the section of 145b in the display area A/A, hereinafter ‘145bCL’)) extending along the first direction (FD) ; the high-voltage connection line (146bCL) is electrically connected with the high-voltage signal line (146b – Fig. 4 – [0073] – “driving voltage lines 146a, 146b may be formed in the lower end non-active area (N/A), and may output a driving voltage (VDD) provided from the data driving portion 230 to the pixel (P) in the active area (A/A)” – this is the section of 146b in the display area A/A, hereinafter ‘146bSL’) and the control chip ([0067] – “The data driving portion 230 may be mounted at the non-active area (N/A) below the active area (A/A), in the form of a chip” – Fig. 4 shows this, hereinafter ‘IC’) , respectively, and the low-voltage connection line (145bCL) is electrically connected with the low-voltage signal line (145b – Fig. 4 – [0077] – “ground lines 145a, 145b may be formed in the lower end non-active area (N/A), and may output a ground voltage (GND) provided from the data driving portion 230 to the pixel (P) in the active area (A/A)” – this is the section of 145b in the display area A/A, hereinafter ‘145bSL’)) and the control chip (IC – Fig. 4 shows this) , respectively. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the voltage signal line structure as taught by Lee into Leng, Kim, Kwon, and Kim-120. An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result (0016] – “in order to prevent short-circuiting when the wires cross each other.” Regarding claim 16 , Leng, as modified by Lee, Kim, Kwon, and Kim-120, teaches claim 15 from which claim 16 depends. Leng, Kim, Kwon, and Kim-120 do not expressly disclose the limitations of claim 15. However, in an analogous art, Lee teaches (Original) The display panel according to claim 15, wherein the high-voltage connection line (146a) and the high-voltage signal line (146bCL) are arranged in a same layer ([0074] – “driving voltage line 146b may be connected to the first driving voltage line 146a and formed as a bar” – this describes the same layer) , and the low-voltage connection line (145a – Fig. 4 – [0078] – “first ground line 145a”) and the low-voltage signal line (145b – Fig. 4 – [0078] – “second ground line 145b”) are arranged in a same layer ([0078] – “second ground line 145b may be connected to the first ground line 145a, and formed as a bar” – this describes the same layer) . Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the voltage signal line structure as taught by Lee into Leng, Kim, Kwon, and Kim-120. An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result as stated above in claim 15 . 07-21-aia AIA Claim s 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Leng in view of Lee, Kim, Kwon, Kim-120, and Park et al. (US 20170358641 A1 – hereinafter Park-641) . Regarding claim 14 , Leng, as modified by Lee, Kim, Kwon, and Kim-120, teaches claim 12 from which claim 14 depends. Leng, Lee, Kim, Kwon, and Kim-120 do not expressly disclose the limitations of claim 14. However, in an analogous art, Park-641 teaches (Original) The display panel according to claim 12, wherein the first low- voltage power supply line (61a – Fig. 4 – {[0053] – “first connection line 60a includes a first portion 61a, a second portion 62a, and a third portion 63a”)}, {[0041] – “The first signal line 10 of the first group 510a may include, for example, a signal line transmitting a common voltage ELVSS, a signal line transmitting a gate low voltage VGL”}, {[0051] – “FIG. 2 shows the parts of the signal lines disposed in the first and second contact regions CA1 and CA2 of the upper side and the lower side of the bending region BA, and the bending region BA. These signal lines may be the data signal lines 60 shown in FIG. 1 and may be the first to fifth signal lines 10, 20, 30, 40, and 50. The part of the signal line disposed at the bending region BA and the contact regions CA1 and CA2 is referred to as a connection line”} – Fig. 2 shows connection lines 60a and 60b that apply to all signal lines, including low-voltage power line 10) is located in the first conductive layer or the second conductive layer; and the second low-voltage power supply line (621a – Fig. 4 – [0097] – “first layers 621a and 621b of second portions 62a and 62b of the first and second connection lines 60a and 60b disposed in the bending region BA and the first contact region CA1”) is located in the third conductive layer or the fourth conductive layer (Fig. 4 shows these elements in different layers) . Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the low-voltage power supply line structure as taught by Park-641 into Leng, Lee, Kim, Kwon, and Kim-120. An ordinary artisan would have been motivated to use the known technique of Park-641 in the manner set forth above to produce the predictable result of [0004] – “a display panel using a flexible substrate has been developed. The flexible substrates are more resilient to impact and can be effectively bent or otherwise deformed.” Regarding claim 20 , Leng, as modified by Lee, Kim, Kwon, Kim-120, and Park-641, teaches claim 14 from which claim 20 depends. Leng further teaches (New) The display panel according to claim 14, wherein the peripheral region (32) further comprises: a drive chip bonding region (323 – fig. 5 – [0088] – “multiple metal lines in the fan-out area 322 are then connected to the control chip (IC) or control circuit board (PCB) in the bonding area 323”) located at a side of the fan-out region (322) away from the display region (31 – Fig. 5 shows this) , the drive chip bonding region (323) comprises: a control chip (IC – [0088] – “the control chip (IC)”). Leng, Kim, Kwon, Kim-120, and Park-641 do not expressly disclose the other limitations of claim 20. However, in an analogous art, Lee teaches and the display panel (100 – Fig. 4 – [0065] – “flexible OLED display device 100”) further comprises: at least one high-voltage connection line (146b – Fig. 4 – [0073] – “driving voltage lines 146a, 146b may be formed in the lower end non-active area (N/A), and may output a driving voltage (VDD) provided from the data driving portion 230 to the pixel (P) in the active area (A/A)” – this is the section of 146b in the display area A/A, hereinafter ‘146bCL’) extending along the first direction ([Claim 1] – “first power supply voltage lines including at least a first portion extending in a first direction” – hereinafter ‘FD’) and at least one low-voltage connection line (145b – Fig. 4 – [0077] – “ground lines 145a, 145b may be formed in the lower end non-active area (N/A), and may output a ground voltage (GND) provided from the data driving portion 230 to the pixel (P) in the active area (A/A)” – this is the section of 145b in the display area A/A, hereinafter ‘145bCL’)) extending along the first direction (FD) ; the high-voltage connection line (146bCL) is electrically connected with the high-voltage signal line (146b – Fig. 4 – [0073] – “driving voltage lines 146a, 146b may be formed in the lower end non-active area (N/A), and may output a driving voltage (VDD) provided from the data driving portion 230 to the pixel (P) in the active area (A/A)” – this is the section of 146b in the display area A/A, hereinafter ‘146bSL’) and the control chip ([0067] – “The data driving portion 230 may be mounted at the non-active area (N/A) below the active area (A/A), in the form of a chip” – Fig. 4 shows this, hereinafter ‘IC’) , respectively, and the low-voltage connection line (145bCL) is electrically connected with the low-voltage signal line (145b – Fig. 4 – [0077] – “ground lines 145a, 145b may be formed in the lower end non-active area (N/A), and may output a ground voltage (GND) provided from the data driving portion 230 to the pixel (P) in the active area (A/A)” – this is the section of 145b in the display area A/A, hereinafter ‘145bSL’)) and the control chip (IC – Fig. 4 shows this) , respectively. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the voltage signal line structure as taught by Lee into Leng, Kim, Kwon, Kim-120, and Park-641. An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable result as stated above in claim 15 . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 5 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 5, prior art of record fails to teach or suggest a sum of a number of high-voltage power supply lines extending to the fan-out region and a number of low-voltage power supply lines extending to the fan-out region is equal to a number of data signal lines; an m-th high-voltage power supply line extending to the fan-out region is connected to a (2m-1)-th column of circuit units, the m-th high-voltage power supply line extending to the fan-out region is located between a (2m-1)-th data signal line and a (2m)-th data signal line, an n-th low-voltage power supply line is located between a (2n)-th data signal line and a (2n+1)-th data signal line, or the m-th high-voltage power supply line extending to the fan-out region is connected to a (2m)-th column of circuit units, the m-th high-voltage power supply line extending to the fan-out region is located between a (2m)-th data signal line and a (2m+1)-th data signal line, the n-th low-voltage power supply line is located between a (2n-1)-th data signal line and the (2n)-th data signal line, wherein 1≤m≤N1, 1≤n≤N2, N1 is a number of high-voltage power supply lines extending to the fan-out region, and N2 is a number of low-voltage power supply lines. Claim 19 depends on claim 5 and is therefore allowable if claim 5 is rewritten in independent form. Pertinent Art For the benefits of the Applicant, US 20240013715 A1 and US 20210376040 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the sequencing of layers in the bending region. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and ttps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GRA/ Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 18/691,872 Page 2 Art Unit: 2897 Application/Control Number: 18/691,872 Page 3 Art Unit: 2897 Application/Control Number: 18/691,872 Page 4 Art Unit: 2897 Application/Control Number: 18/691,872 Page 5 Art Unit: 2897 Application/Control Number: 18/691,872 Page 6 Art Unit: 2897 Application/Control Number: 18/691,872 Page 7 Art Unit: 2897 Application/Control Number: 18/691,872 Page 8 Art Unit: 2897 Application/Control Number: 18/691,872 Page 9 Art Unit: 2897 Application/Control Number: 18/691,872 Page 10 Art Unit: 2897 Application/Control Number: 18/691,872 Page 11 Art Unit: 2897 Application/Control Number: 18/691,872 Page 12 Art Unit: 2897 Application/Control Number: 18/691,872 Page 13 Art Unit: 2897 Application/Control Number: 18/691,872 Page 14 Art Unit: 2897 Application/Control Number: 18/691,872 Page 15 Art Unit: 2897 Application/Control Number: 18/691,872 Page 16 Art Unit: 2897 Application/Control Number: 18/691,872 Page 17 Art Unit: 2897 Application/Control Number: 18/691,872 Page 18 Art Unit: 2897 Application/Control Number: 18/691,872 Page 19 Art Unit: 2897 Application/Control Number: 18/691,872 Page 20 Art Unit: 2897 Application/Control Number: 18/691,872 Page 21 Art Unit: 2897 Application/Control Number: 18/691,872 Page 22 Art Unit: 2897 Application/Control Number: 18/691,872 Page 23 Art Unit: 2897 Application/Control Number: 18/691,872 Page 24 Art Unit: 2897 Application/Control Number: 18/691,872 Page 25 Art Unit: 2897 Application/Control Number: 18/691,872 Page 26 Art Unit: 2897 Application/Control Number: 18/691,872 Page 27 Art Unit: 2897 Application/Control Number: 18/691,872 Page 28 Art Unit: 2897 Application/Control Number: 18/691,872 Page 29 Art Unit: 2897
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