DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of priority to international application PCT/CN2022/121069 filed on September 23rd, 2022, and a claim of foreign priority to Chinese application filed on May 17th, 2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) filed on March 20th, 2024 and April 17th, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Group I (Claims 1-14) in the reply filed on is acknowledged. The traversal is on the ground(s) that Sato et al. discloses a planar structure and not a three-dimensional structure as described in the applicants claims. This is not found persuasive because figures 4-6 of Sato et al. disclose a third embodiment of a memory cell array (e.g. Fig. 4 ref 210) which has a “three-dimensional structure” composed of stacked memory cells (e.g. Fig. 5-6, Description [0153]-[0155]).
The requirement is still deemed proper and is therefore made FINAL, and all non-elected claims (i.e. claims 15-18) are withdrawn from consideration at this time.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,3,5,6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20220005809 A1).
Regarding claim 1;
Kim et al. teaches A memory (e.g. ) comprising: a substrate (e.g. ref LS); a plurality of memory cell columns distributed in a first direction perpendicular to the substrate, each of the memory cell columns comprising a plurality of memory cells disposed and stacked along the first direction, different memory cell columns being arranged on the substrate along a second direction and a third direction to form an array (e.g. Fig. 11); the second direction and the third direction being intersected and the formed plane being parallel to a main plane of the substrate (e.g. Description [0029] “The second direction D2 may intersect the first direction D1, and a third direction D3 may intersect the first direction D1 and the second direction D2. The second direction D2 may be perpendicular to the first direction D1 which is vertically oriented, and a third direction D3 may be perpendicular to the plane formed by the first direction D1 and the second direction D2.”); the memory cell comprising a transistor (e.g. Fig. 2 ref TR) and a capacitor (e.g. Fig.2 ref CAP) disposed in sequence along the second direction, the transistor comprising a semiconductor layer and a gate (e.g. Fig. 2 ref WL), the semiconductor layer extending as a strip structure along the second direction, the strip structure having sidewalls and both ends, and the sidewall in the second direction comprising a source region (e.g. Fig. 2 ref SD1), a channel region (e.g. Fig. 2 ref CH) and a drain region (e.g. Fig. 2 ref SD2), the source region and the drain region being adjacent to two ends of the semiconductor layer, respectively, the channel region being located between the source region and the drain region, the semiconductor layer comprising a first semiconductor layer and a cylindrical second semiconductor layer disposed on sidewalls of the first semiconductor layer, and the gate encircling sidewalls of the second semiconductor layer in the channel region (e.g. Description [0029]-[0030]); an electrode and a dielectric layer of the capacitor encircling the sidewall of the second semiconductor layer in the drain region (Fig. 2 ref CAP; Description [0032]).
PNG
media_image1.png
680
708
media_image1.png
Greyscale
PNG
media_image2.png
468
422
media_image2.png
Greyscale
Regarding claim 3;
Kim et al. further teaches a memory further comprising: a plurality of word lines extending along the third direction and arranged at intervals in the first direction (e.g. Fig. 11 ref WL), wherein the substrate is provided with one memory cell column in the third direction, and each word line is formed by connecting gates in transistors of one memory cell of one memory cell column arranged along the third direction (e.g. Description [0046] “The word line WL may surround a portion of the active layer ACT. The word line WL may include a gate all-around (GAA) structure.”; Fig. 10-11 ref WL).
PNG
media_image3.png
680
708
media_image3.png
Greyscale
Regarding claim 5;
Kim et al. further teaches a memory wherein, a material for the word line comprises at least one of indium and tin (e.g. Description [0046] “The word line WL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.”) (under BRI Indium and Tin are interpreted to be within the reference’s “metal” material comprising the word line).
Regarding claim 6;
Kim et al. further teaches a memory wherein a material for the first semiconductor layer is selected from any one or more of Group IVA semiconductor materials (e.g. Description [0045] “The active layer ACT may include a semiconductor material. The active layer ACT may include a silicon layer, for example, doped polysilicon, undoped polysilicon, or amorphous silicon. The active layer ACT may include polysilicon nano-wire.”).
Regarding claim 8;
Kim et al. further teaches a memory wherein a material for the second semiconductor layer is a metal oxide semiconductor material, and metals in the metal oxide comprise at least one of indium, zinc, tungsten, tin, titanium, zirconium, hafnium and gallium (e.g. Description [0045] “The active layer ACT may include a compound of a transition metal and a chalcogen. The active layer ACT may include InGaZnOx (IGZO), InSnZnOx, ZnSnOx, MoS2, WS2, or MoSe2.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220005809 A1) for the following reasons:
Regarding claim 2;
Kim et al. teaches an embodiment of a memory in figure 10 further comprising: a plurality of bit lines extending along the first direction, two adjacent memory cells along the second direction being in a mirror image distribution (e.g. Fig. 10).
Kim et al. is silent to the afore mentioned embodiment having source regions of adjacent memory cells being connected to one common bit line as claimed.
PNG
media_image4.png
408
418
media_image4.png
Greyscale
However, Kim et al. teaches another embodiment of a memory in figure 11 where the source regions of two adjacent memory cells are connected to a shared bit line.
PNG
media_image5.png
404
420
media_image5.png
Greyscale
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to form the memory according to the embodiment taught in figure 11 of Kim et al., since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (5809) (US 20220005809 A1) in view of Kim et al. (8988) (US 20220108988 A1) for the following reasons:
Regarding claim 4;
Kim et al. (5809) is silent to the plurality of word lines in the memory being arranges in a staircase shape as claimed.
However, Kim et al. (8988) teaches a memory wherein the plurality of word lines arranged at intervals in the first direction have different lengths and form a staircase shape (e.g. Fig. 6A-C; Description [0017] “Various embodiments of the present disclosure can provide multi-direction conductive lines and can allow connection to those conductive lines through a tiered (e.g., staircase) structure… the conductive lines may be access lines (i.e., world lines) coupled to one or more circuitry components…”).
PNG
media_image6.png
641
446
media_image6.png
Greyscale
PNG
media_image7.png
631
393
media_image7.png
Greyscale
PNG
media_image8.png
648
410
media_image8.png
Greyscale
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to form the word lines taught in Kim et al. (5809) to have different lengths and form a staircase structure as taught in Kim et al. (8988) because such connection architecture provides a greater density of connections between conductive elements in the device area (e.g. Description [0017]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220005809 A1) in view of Sekar et al. (US 20220130905 A1) for the following reasons:
Regarding claim 7;
Kim et al. teaches a memory wherein the material for the first semiconductor layer is silicon (e.g. Description [0045] “The active layer ACT may include a semiconductor material. The active layer ACT may include a silicon layer…”).
Kim et al. is silent to the silicon layer being monocrystalline as claimed.
However, Sekar et al. teaches a single-crystal transistor channel (e.g. Description [0026] “…a 3D semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal channel…”).
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to form the silicon layer taught in Kim et al. in a monocrystalline form as taught in Sekar et al. because single-crystal/monocrystalline materials have a lower density of defects, leading to an improved performance in transistor applications (e.g. Background [0015]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220005809 A1) in view of Shin et al (US 20220085023 A1) for the following reasons:
Regarding claim 9;
Kim et al. is silent to an isolation layer disposed between the gates of two transistors in a memory cell column as claimed.
However, Shin et al. teaches a gap-filling material which is disposed between two gate electrodes of adjacent transistors in a memory cell column (e.g. Fig. 2; Description [0036] “A gap-fill insulating layer 142 may be between a first gate electrode 130A1 on a sidewall of one semiconductor pattern AP and a second gate electrode 130A2 on a sidewall of another semiconductor pattern AP adjacent to the one semiconductor pattern AP. A space between the first gate electrode 130A1 and the second gate electrode 130A2 adjacent to each other may be filled with the gap-fill insulating layer 142.”).
PNG
media_image9.png
700
698
media_image9.png
Greyscale
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to incorporate the gap-filling material taught in Shin et al. into the memory array taught by Kim et al. because it realizes a memory cell with improved properties (e.g. electrically isolated elements reduce the leakage current and parasitic capacitances a memory cell might experience due to field effects).
Claim 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220005809 A1) in view of Harter et al. (US 20060076602 A1) for the following reasons:
Regarding claim 10;
Kim et al. is silent to a memory further comprising further comprising one or more memory cell isolation pillars extending along the first direction, and one memory cell isolation pillar being provided every two memory cell columns in the second direction as claimed.
However, Harter et al. teaches in figure 1 an isolation structure (e.g. ref 16) which extends in the first direction between two memory cells in the second direction (e.g. Description [0095] “The cell rows 15, which are equidistant from one another, are isolated from one another by trench isolator structures 16.”).
PNG
media_image10.png
755
498
media_image10.png
Greyscale
At the effective time of filing, it would have been obvious to someone having ordinary
skill in the art to incorporate the isolation structure taught in Harter et al. into a memory taught in Kim et al. because it realizes a memory cell with improved properties (e.g. electrically isolated memory columns reduce the improper read/write function a device might experience due to leakage current and parasitic capacitive effects).
Regarding claim 11;
Harter et al. is silent to the material of the memory cell isolation pillar being silicon oxide as claimed.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the memory cell isolation pillar using Silicon Oxide, since it has been held to be within the general skill of worker in the art to select a known material on the basis of its suitability for the intended use (e.g. acting in the claimed invention as an electrical insulator/isolation structure) as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Allowable Subject Matter
Claims 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights