Prosecution Insights
Last updated: October 02, 2026
Application No. 18/692,226

METHOD FOR PRODUCING A GROWTH SUBSTRATE, GROWTH SUBSTRATE, AND METHOD FOR PRODUCING A PLURALITY OF OPTOELECTRONIC SEMICONDUCTOR CHIPS

Non-Final OA §102§103
Filed
Mar 14, 2024
Priority
Sep 21, 2021 — DE 10 2021 124 366.1 +1 more
Examiner
ANYA, IGWE U
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ams-osram AG
OA Round
2 (Non-Final)
85%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
817 granted / 961 resolved
+17.0% vs TC avg
Minimal -4% lift
Without
With
+-3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
26 currently pending
Career history
970
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
36.6%
-3.4% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 961 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter The indicated allowability of claim 23 is withdrawn in view of the newly discovered reference(s) to Lee et al. Rejections based on the newly cited reference(s) follow. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 16 – 17, 19 and 21 – 26 are rejected under 35 U.S.C. 102(1)(1) as being anticipated by Lee et al. (Self-Assembly Semipolar AlN Nanopyramids Grown on Powder-Compressed AlN Substrates). (Claim 16) Lee et al. teach a method for producing a growth substrate, the method comprising: providing a polycrystalline substrate comprising a nitride compound semiconductor material (fig. 2A, poly-AlN substrate); applying at least one surface layer (fig. 2A, AlN sputtered) onto a main surface of the polycrystalline substrate by sputtering or atomic layer deposition (pages 1 – 2), wherein the at least one surface layer comprises a nitride compound semiconductor material, wherein the at least one surface layer is configured for epitaxial growth of an epitaxial semiconductor layer sequence (see, heading 2. Experimental, “to improve crystallinity”); and a high-temperature annealing of the polycrystalline substrate with the at least one surface layer applied thereto (see, heading 2. Experimental). (Claim 17) Lee et al. teach wherein the polycrystalline substrate comprises aluminum nitride, and wherein the at least one surface layer comprises aluminum nitride or indium gallium nitride (page 1). (Claim 19) Lee et al. teach the method, further comprising applying a further surface layer by metal-organic chemical vapor deposition or by sputtering before the high-temperature annealing (page 1, layers are formed until a desired thickness is reached). (Claim 21) Lee et al. teach the method, further comprising epitaxially growing a buffer layer on the surface layer after the high-temperature annealing (page 2, from last paragraph to page 3). (Claim 22) Lee et al. teach wherein the buffer layer comprises aluminum nitride or indium gallium nitride (pages 3 – 4). (Claim 23) Lee et al. teach a growth substrate comprising: a polycrystalline substrate comprising a nitride compound semiconductor material and having a main surface (fig. 2A); and at least one surface layer comprising a nitride compound semiconductor material and arranged on the main surface of the polycrystalline substrate (pages 1 – 4), wherein the surface layer is configured for epitaxial growth of an epitaxial semiconductor layer sequence, and wherein the at least one surface layer comprises columnar crystallites ( pages 1 – 4, nanopyramids). (Claim 24) Lee et al. teach wherein the polycrystalline substrate comprises aluminum nitride (fig. 2A). (Claim 25) Lee et al. teach wherein the at least one surface layer comprises aluminum nitride or indium gallium nitride (fig. 2A). (Claim 26) Lee et al. teach wherein the at least one surface layer has a thickness between 10 nanometers and 5000 nanometers, inclusive (fig. 2A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 20 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Self-Assembly Semipolar AlN Nanopyramids Grown on Powder-Compressed AlN Substrates) in view of Miyashita et al. (US 2013/0157445). (Claim 20) Lee et al. lack the method, further comprising planarizing the at least one surface layer by a chemical-mechanical polishing process after the high- temperature annealing. However, Miyashita et al. teach planarizing the at least one surface layer by a chemical-mechanical polishing process for the benefit of obtaining a flat face for improved crystal growth (paragraph 32). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of obtaining a flat face for improved crystal growth. (Claim 27) Lee et al. lack wherein the polycrystalline substrate has a diameter of at least 100 millimeters and a maximum thickness of 1000 micrometers. However, Miyashita et al. teach wherein the polycrystalline substrate has a diameter of at least 50 millimeters (paragraph 14) and a maximum thickness of 3000 micrometers (paragraph 15) for the benefit of regulating the thermal expansion (paragraph 35). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of regulating the thermal expansion. Claims 31 – 32 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Self-Assembly Semipolar AlN Nanopyramids Grown on Powder-Compressed AlN Substrates) in view of Lin et al. (CN 201347222). (Claim 31) Lee et al. teach a method for producing a growth substrate, the method comprising: providing a polycrystalline substrate comprising a nitride compound semiconductor material; applying at least one surface layer onto a main surface of the polycrystalline substrate, wherein the at least one surface layer comprises a nitride compound semiconductor material, and a high-temperature annealing of the polycrystalline substrate with the at least one surface layer applied thereto; and epitaxially growing a buffer layer on the surface layer after the high-temperature annealing (pages 1 – 5). Lee et al. lack wherein the at least one surface layer is configured for epitaxial growth of an epitaxial semiconductor layer sequence. However, Lin teaches wherein the at least one surface layer is configured for epitaxial growth of an epitaxial semiconductor layer sequence for the benefit of preventing abnormal operation of a light emitting device (figs. 3). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of forming a light emitting device. (Claim 32) Lee et al. teach wherein the buffer layer comprises aluminum nitride or indium gallium nitride (fig. 2A). Allowable Subject Matter Claims 28 – 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Claim 28) applying connecting contacts for the plurality of optoelectronic semiconductor chips on the epitaxial semiconductor layer sequence; applying a carrier substrate on the connecting contacts; detaching the growth substrate from the epitaxial semiconductor layer sequence; and singulating the optoelectronic semiconductor chips. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IGWE U ANYA/Primary Examiner, Art Unit 2891 September 19, 2026
Read full office action

Prosecution Timeline

Mar 14, 2024
Application Filed
May 12, 2026
Non-Final Rejection mailed — §102, §103
Jul 15, 2026
Response Filed
Sep 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
85%
Grant Probability
81%
With Interview (-3.7%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 961 resolved cases by this examiner. Grant probability derived from career allowance rate.

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