Prosecution Insights
Last updated: October 02, 2026
Application No. 18/692,698

OPTICAL SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Mar 15, 2024
Priority
Jan 27, 2022 — nonprovisional of PCTJP2022003098
Examiner
LEUNG, CHRISTINA Y
Art Unit
Tech Center
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
78%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
161 granted / 208 resolved
+17.4% vs TC avg
Minimal +1% lift
Without
With
+1.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
25 currently pending
Career history
221
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
24.2%
-15.8% vs TC avg
§102
13.7%
-26.3% vs TC avg
§112
27.5%
-12.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 208 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Summary of the Claims The present application (18/692,698) was filed on March 15, 2024 as a 371 of PCT/JP2022/003098 filed on January 27, 2022. Claims 1-9 are pending. Claims 1 and 4 are the independent claims. References and Documents Cited in this Action Higuichi (JP 2019134058 A; see English-language machine translation mailed with this action) Ueki (JP 2000277852 A; see English-language machine translation filed on March 15, 2024 by Applicant) Donovan (US 2021/0234342 A1) Kiyota (US 2016/0336719 A1) Summary of Rejections and Objections in this Action Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Higuchi. Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ueki in view of Donovan. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Higuchi in view of Kiyota. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ueki in view of Donovan and Kiyota. Claims 2-3 and 5 contain allowable subject matter. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Higuchi. Since Higuchi is in Japanese, all references to its disclosure in this action (including paragraph numbers) are made to the English-language machine translation mailed with this action. Regarding independent claim 1, Higuchi discloses an optical semiconductor device (Figures 1-3 and 13) comprising: a semiconductor substrate of a first conductive type (i.e., substrate 2 “made of, for example, n-type GaAs”; paragraph [0022]); active portions (i.e., ridges 10) and passive portions (i.e., embedding parts 38) alternately arranged along a first direction on the semiconductor substrate (Figure 2; Figure 13 shows multiple ridges 10; paragraphs [0076]-[0078]); and an electrode 5 provided on the active portion, wherein the active portion includes an active layer 33, a second conductive type cladding layer 35 (“made of, for example, p-type Al0.32Ga0.68 As”; paragraph [0026]), and a second conductive type contact layer 37 (“made of, for example, p-type GaAs”; paragraph [0032]) that are stacked in order on the semiconductor substrate, the active portion has a resonator structure sandwiched between a front end surface 3b and a rear end surface 3c in a second direction perpendicular to the first direction (paragraph [0023]), the second conductive type contact layer 37 in the active portion is in contact with the electrode 5, and the passive portion includes the second conductive type contact layer 37 and a first conductive type layer (portion 38 are “made of, for example, n-type In0.5Ga0.5P”; paragraph [0035]) provided on the second conductive type contact layer. PNG media_image1.png 330 601 media_image1.png Greyscale Regarding claim 7, Higuchi discloses that the first conductive type layer 38 has a thickness of 50 nm or more (i.e., layer 38 is made in the groove etched to stop layer 36 through layer 35b, which is 1.3μm thick and well above 50 nm; Figure 2; paragraph [0027]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ueki in view of Donovan. Since Ueki is in Japanese, all references to its disclosure in this action (including paragraph numbers) are made to the English-language machine translation filed on March 15, 2024 by Applicant. Regarding independent claim 4, Ueki discloses an optical semiconductor device (Figure 1) comprising: a semiconductor substrate of a first conductive type (i.e., “an n-type GaAs substrate 1; paragraph [0022]); an active portion provided on the semiconductor substrate in a planar view (i.e., region including opening 11); passive portions provided on the semiconductor substrate so as to surround four sides of each of the active portions in a planar view (i.e., regions surrounding opening 11, wherein opening 11 may be a circle, square, or other shape that is surrounded on all sides; paragraph [0034]); and an electrode 9 provided on the active portion (paragraphs [0035]-[0037]), wherein the active portion includes an active layer 4, a second conductive type cladding layer (i.e., “reflective film 6 made of…p-type Al0.9Ga0.1As”), and a second conductive type contact layer 7 (“made of a p-type Ga0.5In0.5P”) that are stacked in order on the semiconductor substrate (paragraph [0022]), the second conductive type contact layer 7 in the active portion is in contact with the electrode 9 (Figure 1), and the passive portion includes the second conductive type contact layer 7 and a first conductive type layer (i.e., current blocking layer 8, which is “an n-type GaAs layer”) provided on the second conductive type contact layer (Figure 1; paragraph [0029]). PNG media_image2.png 336 731 media_image2.png Greyscale Further regarding claim 4, Ueki generally discloses “a surface emitting semiconductor laser which can be easily formed into a two dimensional array” (paragraph [0002]) but does not specifically disclose a plurality of active portions provided in a matrix shape on the semiconductor substrate in a planar view. However, Donovan teaches an optical semiconductor device that is related to the one disclosed by Ueki including a substrate 252 and active and passive portions (i.e., active regions including laser apertures shown as circles and the surrounding passive portions in Figure 2A; Donovan, paragraphs [0026]-[0029]). Regarding claim 4, it would have been obvious to a person of ordinary skill in the art to provide a plurality of active portions provided in a matrix shape on the semiconductor substrate in a planar view as taught by Donovan in the optical semiconductor device disclosed by Ueki in order to advantageously output multiple laser outputs in an array. Again, Ueki already discloses “a surface emitting semiconductor laser which can be easily formed into a two dimensional array” (Ueki, paragraph [0002]). Regarding claim 9, in the optical semiconductor device taught by Ueki in view of Donovan, Ueki does not specifically disclose that the first conductive type layer has a thickness of 50 nm or more. However, Ueki discloses that thickness of the first conductive type layer 8 and electrode 9 combined “is equal to an integral multiple of a half wavelength of an oscillation wavelength λ of laser light emitted,” which may be 780 nm; paragraphs [0038]-[0043]). It would have been obvious to a person to provide a first conductive type layer of a thickness of 50 nm or more in the optical semiconductor device taught by Ueki in view of Donovan as an engineering design choice of a thickness value to meet Ueki’s objectives with a reasonable expectation of success, e.g., effectively controlling mirror loss difference and maximizing output of the device (Ueki, paragraph [0040]). Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Higuchi in view of Kiyota. Regarding claim 6, Higuchi discloses an optical semiconductor device as discussed above with regard to claim 1 but does not specifically disclose that the semiconductor substrate, the second conductive type cladding layer, and the first conductive type layer are made of InP, the second conductive type contact layer is made of InGaAs. However, Kiyota teaches an optical semiconductor device that is related to the one disclosed by Higuchi, including substrate, cladding, and contact layers and further teaches that various layers including substrate 21 and cladding 28a may be made of InP and a contact layer 35 may be made of InGaAs (Figure 2; paragraphs [0048]-[0050]). Regarding claim 6, it would have been obvious to a person of ordinary skill in the art to use Inp and InGaAs layer materials as taught by Kiyota in the optical semiconductor device disclosed by Higuchi as an engineering design choice of materials for effectively emitting laser output having predictable results with a reasonable expectation of success, particularly laser output in wavelengths suitable for optical communication (Kiyota, paragraph [0044]). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ueki in view of Donovan as applied to claim 4 above, and further in view of Kiyota. Regarding claim 8, Ueki in view of Donovan teaches an optical semiconductor device as discussed above with regard to claim 4 but does not specifically disclose that the semiconductor substrate, the second conductive type cladding layer, and the first conductive type layer are made of InP, the second conductive type contact layer is made of InGaAs. However, Kiyota teaches an optical semiconductor device that is related to the one taught by Ueki in view of Donovan, including substrate, cladding, and contact layers and further teaches that various layers including substrate 21 and cladding 28a may be made of InP and a contact layer 35 may be made of InGaAs (Figure 2; paragraphs [0048]-[0050]). Regarding claim 8, it would have been obvious to a person of ordinary skill in the art to use Inp and InGaAs layer materials as taught by Kiyota in the optical semiconductor device taught by Ueki in view of Donovan as an engineering design choice of materials for effectively emitting laser output having predictable results with a reasonable expectation of success, particularly laser output in wavelengths suitable for optical communication (Kiyota, paragraph [0044]). Allowable Subject Matter Claims 2, 3, and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not specifically disclose or fairly suggest an optical semiconductor device including the combination of all of the elements, steps, and limitations recited in claims 2, 3, and 5 (including all of the limitations of any respective parent claims), particularly wherein: a ridge structure extending in the second direction is provided by etching from the second conductive type cladding layer to below the active layer, a buried layer is provided so as to cover side surfaces of the ridge structure up to a position higher than the active layer, the second conductive type contact layer is provided on the ridge structure and the buried layer, and the passive portion includes the buried layer, the second conductive type contact layer, and the first conductive type layer that are stacked in order on the semiconductor substrate (e.g., claims 2 and 3); or a micropillar structure is provided by etching from the second conductive type cladding layer to below the active layer, a buried layer is provided so as to cover side surfaces of the micropillar structure up to a position higher than the active layer, the second conductive type contact layer is provided on the micropillar structure and the buried layer, and the passive portion includes the buried layer, the second conductive type contact layer, and the first conductive type layer that are stacked in order on the semiconductor substrate (e.g., claim 5). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina Leung at telephone number (571) 272-3023. If attempts to reach the examiner are unsuccessful, the examiner’s supervisor, Patricia Engle can be reached at (571) 272-6660. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patents/laws/interview-practice. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINA Y. LEUNG/ Primary Examiner, Art Unit 3991
Read full office action

Prosecution Timeline

Mar 15, 2024
Application Filed
Aug 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
78%
With Interview (+1.1%)
2y 8m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 208 resolved cases by this examiner. Grant probability derived from career allowance rate.

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