Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-9 in the reply filed on 6/11/2026 is acknowledged. The traversal is on the ground(s) that since claim 10 has been amended and now includes all the limitations of claim 1, Groups I (claims 1-9) and II (claims 10-12) share a common technical feature that is special over the prior art previously presented. This is not found persuasive because the traversal does not address the reason for the initial restriction made on the original claims. As originally presented, no argument has been made for the initial restriction.
The requirement is still deemed proper and is therefore made FINAL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 3/22/2024 and 8/22/2025 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Vertical Word Lines in .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation “further comprise a fifth insulation layer”, this limitation renders the claim indefinite because there is no mention of first through fourth insulation layers (in the prior claims) and it is unclear of their structural relations to the fifth insulation layer. For examination purposes, based on broadest reasonable interpretation, the examiner has interpreted this limitation as “further comprise an additional insulation layer covering outer side walls of the protective layers.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20220367479A1) in view of Li et al. (US20230389263A1).
Regarding Claim 1:
Lee discloses a three-dimensional (3D) stacked semiconductor device (Figs. 1A/B), comprising:
a plurality of transistors (Fig. 11B, paragraph 39-40) distributed in different layers and stacked along a direction perpendicular (Z-direction) to a base substrate (element 101);
a word line (element 170) extending along the direction perpendicular (Z-direction) to the base substrate (element 101) and penetrating through the transistors of the different layers (paragraph 23); and
a plurality of protective layers (element 130) respectively corresponding to the plurality of transistors (paragraph 22);
wherein each transistor comprises a semiconductor layer (element 140) surrounding a side wall of the word line (element 170), and a gate insulation layer (element 160) disposed between the side wall of the word line and the semiconductor layer (paragraph 24); wherein the semiconductor layer extends on the side wall of the word line to form an annular semiconductor layer extending along the direction perpendicular to the base substrate (Fig. 7A, paragraphs 29 and 75);
a plurality of semiconductor layers (elements 180/182/142/144/190/192) of the plurality of transistors are disposed at intervals (Fig. 11B) in a direction in which the word line extends (element 170; Z-direction); wherein the gate insulation layer (element 160) is exposed between two adjacent semiconductor layers disposed at intervals (Fig. 10B, paragraph 109);
However, Lee does not explicitly disclose where the plurality of protective layers surrounds and covers a corresponding semiconductor layer nor that two adjacent protective layers are disconnected.
Li discloses an analogous 3D stacked memory structure (Fig. 2T), comprising a word line (element 34), wherein each of the protective layers (Figs. 2M-T element 29) respectively surrounds and covers an outer side wall of word line (Figs. 2T(a) and (b), paragraph 44), and two adjacent protective layers are disconnected from each other to expose the gate insulation layer (Fig. 2O element 33).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Lee further in view of Li to explicitly where each of the protective layers surrounds and covers the outer side wall of the corresponding semiconductor layer. Furthermore, where two adjacent protective layers are disconnected from each other to expose the gate insulation layer because both are directed to analogous 3D stacked memory structures. Doing so improves the performance of the semiconductor device by mitigating unwanted parasitic interference (Li, paragraphs 4-5, 50, 67).
Regarding Claim 2:
The combination of Lee and Li disclose a 3D stacked semiconductor device according to claim 1, wherein Lee further discloses the plurality of stacked transistors (Fig. 11B) comprise:
insulation layers (element 110) and conductive layers (elements 180/182/142/144/190/192) alternately distributed in turn from bottom to top along the direction perpendicular (Z-direction) to the base substrate (element 101); and
a through hole (Fig. 10B element 170H) penetrating through each of the insulation layers and each of the conductive layers, wherein the word line (element 170), the gate insulation layers (element 160) surrounding the side wall of the word line (paragraph 24), the plurality of semiconductor layers (element 140) surrounding the gate insulation layers (Fig. 8B) are sequentially distributed within the through hole from inside to outside (Figs. 10),
wherein each insulation layer (element 110) is filled between two adjacent semiconductor layers (Fig. 11B, paragraph 46), and the insulation layer is in contact with the exposed gate insulation layer (paragraph 109); and
each conductive layer (elements 180/182/142/144/190/192) comprises a first electrode (elements 190/192/144) and a second electrode (elements 180/182/142) which are independent of each other (paragraph 31), one of the first electrode and the second electrode is a source of a transistor (paragraphs 33-34), and the other of the first electrode and the second electrode is a drain of the transistor (paragraphs 35-37).
However, Lee does not explicitly disclose where the protective layers surrounding the semiconductor layers are additionally distributed within the through hole and are in contact with the semiconductor layers.
Li discloses an analogous 3D stacked memory structure (Fig. 2T), wherein the protective layers (Fig. 2M element 29) are sequentially distributed within a through hole (element 32).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Lee further in view of Li to explicitly include where the protective layers surrounding the semiconductor layers are sequentially distributed – in addition to the word line, gate insulation layers, and semiconductor layers – and are in contact with the semiconductor layers because both are directed to analogous 3D stacked memory structures. Doing so improves the performance of the semiconductor device by mitigating unwanted parasitic interference (Li, paragraphs 4-5, 50, 67).
Regarding Claim 3:
The combination of Lee and Li disclose a 3D stacked semiconductor device according to claim 2, wherein Lee further discloses an aperture of the through hole (Fig. 10B element 170H) corresponding to a first region of the conductive layer (paragraphs 87-88) is equal (see annotated Fig. attached below) to an aperture of the through hole corresponding to a second region of the insulation layer (element 110);
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only a side wall of the conductive layer is exposed within the through hole (paragraphs 80-91), and only a side wall of the insulation layer is exposed within the through hole (Figs. 10-11); and a semiconductor layer (element 140) is distributed on the side wall of the conductive layer (paragraphs 33-35).
Regarding Claim 4:
The combination of Lee and Li disclose a 3D stacked semiconductor device according to claim 2, but Lee does not explicitly disclose where the protective layers are disconnected at upper and lower surfaces of the insulation layers.
Li, however, discloses an analogous 3D stacked memory structure (Fig. 2T), wherein the plurality of protective layers (element 29) extend along the direction perpendicular (D1) to the base substrate (element 20) and are disconnected at upper and lower surfaces of the insulation layers (Figs. 2N(b) and 2T(b) element 33).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Lee further in view of Li to explicitly include the plurality of protective layers disconnected at upper and lower surfaces of the insulation layers because both are directed to analogous 3D stacked memory structures. Doing so improves the performance of the semiconductor device by mitigating unwanted parasitic interference (Li, paragraphs 4-5, 50, 67).
Regarding Claim 5:
The combination of Lee and Li disclose a 3D stacked semiconductor device according to claim 2, but Lee does not explicitly disclose where the protective layer covers a region in a side wall of the semiconductor layer that is not in contact with the conductive layer.
Li, however, discloses an analogous 3D stacked memory structure (Fig. 2T), wherein each protective layer (element 29) is in contact with a corresponding transistor (paragraphs 17-18), and the protective layer covers a region in a side wall of the word line (element 34) that is not in contact with the conductive layer (Figs. 2 element 212/30).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Lee further in view of Li to explicitly include where each protective layer is in contact with a semiconductor layer and that said protective layer covers a region in a side wall of the semiconductor layer that is not in contact with the conductive layer, because both are directed to analogous 3D stacked memory structures. Doing so improves the performance of the semiconductor device by mitigating unwanted parasitic interference (Li, paragraphs 4-5, 50, 67).
Regarding Claim 6:
The combination of Lee and Li disclose a 3D stacked semiconductor device according to claim 2, but Lee does not explicitly disclose where the protective layers are further distributed on and in contact with the side walls of the conductive layer.
Li, however, discloses an analogous 3D stacked memory structure (Fig. 2T), wherein the protective layers (element 29) are further distributed on side walls of the conductive layer (Figs. 2 element 212/30) and are in contact with the side wall of the conductive layer (paragraphs 44-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Lee further in view of Li to explicitly include where the protective layers are further distributed on side walls of the conductive layer – and in contact with the side wall of said layer – because both are directed to analogous 3D stacked memory structures. Doing so improves the performance of the semiconductor device by mitigating unwanted parasitic interference (Li, paragraphs 4-5, 50, 67).
Regarding Claim 7:
The combination of Lee and Li disclose a 3D stacked semiconductor device according to claim 2, wherein Lee further discloses a material of the protective layers (Figs. 1A/B element 130) is different (paragraphs 21-22) from a material of the insulation layers (element 110).
Regarding Claim 9:
Lee discloses an electronic equipment (paragraph 39), comprising the 3D stacked semiconductor device (Fig 1A element 10) disclosed by the combination of Lee and Li according to claim 1.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20220367479A1) in view of Li et al. (US20230389263A1) as applied to claim 2 above, and further in view of Son et al. (US 20220262814A1).
Regarding Claim 8:
The combination of Lee and Li disclose a 3D stacked semiconductor device according to claim 2, but neither Lee nor Li explicitly discloses an additional insulation layer that covers the outer walls of the protective layers.
Son, however, discloses an analogous 3D semiconductor memory device (Fig. 3B-D), wherein a plurality of stacked transistors (Figs. 1, paragraphs 42-45) comprise an additional insulation layer (element 9) covering outer side walls of the protective layers (element 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Lee and Li further in view of Son to explicitly include an additional insulation layer covering the outer walls of the protective layers because both are directed to analogous 3D stacked memory structures. Doing so improves the performance of the semiconductor device while also allowing for an increase in integration (Son, paragraphs 3 and 81).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US 20220045094 A1), Harari et al. (US 20170148517 A1), Lai et al. (US 20170047377 A1), Joo et al. (US 20120231593 A1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/Chloë E Benton/Examiner, Art Unit 2899
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