Prosecution Insights
Last updated: October 01, 2026
Application No. 18/692,985

CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE COMPRISING SAME

Non-Final OA §102§103
Filed
Aug 22, 2024
Priority
Sep 16, 2021 — RE 10-2021-0124366 +1 more
Examiner
SAWYER, STEVEN T
Art Unit
Tech Center
Assignee
LG Innotek Co., Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
761 granted / 1050 resolved
+12.5% vs TC avg
Strong +30% interview lift
Without
With
+30.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
30 currently pending
Career history
1077
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
64.4%
+24.4% vs TC avg
§102
24.0%
-16.0% vs TC avg
§112
9.6%
-30.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1050 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species d (fig. 8) directed to claims 1-16 in the reply filed on 7/9/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 6, 9, 10 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. (US Patent 5837427). Regarding claim 1 – Hwang teaches a circuit board (figs. 3-4 [title] Hwang states, “multi-layer printed circuit board”) comprising: an insulating layer (110); a pad (112 [column 2 line 35] Hwang states, “the substrate 110 having the pattern 112”) disposed on the insulating layer (110); and a protective layer (combination of layers 114 & 116 [column 3 lines 28-29] Hwang states, “photosensitive insulating resin layers 114 and 116 are formed on the substrate”) disposed on the insulating layer (110) and including a recess portion (recess portion comprised of both openings 122 & 124) vertically overlapping with the pad (112), wherein the protective layer (114/116) includes: a first portion (114) including a first part (recessed portion shown at 122) of the recess portion (122/124); and a second portion (116) disposed on the first portion (114) and including a second part (recessed portion shown at 124) of the recess portion connected to the first portion (114), and wherein a width of the second part (recessed portion shown at 124 having width d2) of the recess portion is greater than a width of the first part (recessed portion shown at 122 having width d1) of the recess portion, and wherein the width (width shown at d1) of the first part of the recess portion is smaller than a width of the pad (112, claimed structure shown in figure 3). Regarding claim 2 – Hwang teaches the circuit board of claim 1, wherein the recess portion (fig. 3, recess portion comprised of both openings 122 & 124) includes at least one point among a point where a width changes, a point where an inclination of an inner wall changes (figure 3 shows the incline changing with a horizontal part therebetween and therefore appears to meet this claimed limitation), and a point where a curvature of the inner wall changes, and wherein the first part (recess at 122) and the second part (recess at 124) of the recess portion are divided based on the point (claimed structure shown in figure 3). Regarding claim 6 – Hwang teaches the circuit board of claim 1, wherein an entirety of a side surface of the pad (fig. 3, 112) and a portion of an upper surface of the pad (112) are covered by the protective layer (114/116; claimed structure shown in figure 3). Regarding claim 9 – Hwang teaches the circuit board of claim 1, wherein an inner wall (fig. 3, 122) of the first part (recessed portion shown at 122) of the recess portion has an inclination whose width gradually decreases towards the pad (112; claimed structure shown in figure 3). Regarding claim 10 – Hwang teaches the circuit board of claim 9, wherein a width of an upper portion of the first part (fig. 3, recessed portion shown at 122) of the recess portion and a width of a lower portion of the first part of the recess portion are smaller than the width of the pad (112; figure 3 shows the width of the pad 112 being greater than the first part of the recess portion within layer 114). Regarding claim 11 – Hwang teaches the circuit board of claim 3, wherein an inner wall of the second part (fig. 3, recessed portion shown at 124) of the recess portion has an inclination whose width gradually decreases towards the pad (112; claimed structure shown in figure 3). Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US PG. Pub. 2014/0037862). Regarding claim 1 – Lee teaches a circuit board (fig. 6, 100 [title] Lee states, “printed circuit board”) comprising: an insulating layer (110 [paragraph 0034] Lee states, “The base substrate 110 may be a printed circuit board on which a general insulating layer”); a pad (120 [paragraph 0061] Lee states, “exposed circuit layer 120”) disposed on the insulating layer (110); and a protective layer (130 [paragraph 0064] Lee states, “solder resist layer 130”) disposed on the insulating layer (110) and including a recess portion (recesses 134 & 132) vertically overlapping with the pad (120), wherein the protective layer (134/132) includes: a first portion (lower portion of 130) including a first part (134 [paragraph 0059] Lee states, “open part 134”) of the recess portion (134/132); and a second portion (upper portion of 130) disposed on the first portion and including a second part (132 [paragraph 0055] Lee states, “open part 132”) of the recess portion connected to the first portion (claimed structure shown in figure 6), and wherein a width of the second part (132) of the recess portion is greater than a width of the first part (132) of the recess portion, and wherein the width of the first part (134) of the recess portion is smaller than a width of the pad (120; claimed structure shown in figure 6). Regarding claim 2 – Lee teaches the circuit board of claim 1, wherein the recess portion (fig. 6, 134/132) includes at least one point (see point at interface between 134 & 132) among a point where a width changes (see width changing between recess parts 134 & 142), a point where an inclination of an inner wall changes, and a point where a curvature of the inner wall changes, and wherein the first part (134) and the second part (132) of the recess portion are divided based on the point (claimed structure shown in figure 6). Regarding claim 3 - Lee teaches the circuit board of claim 2, further comprising: a surface treatment layer (fig. 6, 160 [paragraph 0062] Lee states, “surface treating layer 160 is not particularly limited to if known to those skilled in the art and may be formed, for example, by electro gold plating”) disposed in the first part (134) of the recess portion (134/132). Regarding claim 4 – Lee teaches the circuit board of claim 3, wherein an upper surface of the surface treatment layer (fig. 6, 160) is located lower than an upper surface of the first portion (portion of protective layer 130 that has first part 134) of the protective layer (130; claimed structure shown in figure 6). Claim(s) 1, 7-8 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih (US PG. Pub. 2008/0176035). Regarding claim 1 – Shih teaches a circuit board (fig. 2I [title] Shih states, “circuit board structure”) comprising: an insulating layer (20 [paragraph 0030] Shih states, “carrier board 20”); a pad (210 [paragraph 0030] Shih states, “electrically connecting pads 210”) disposed on the insulating layer (20); and a protective layer (combination of layers 22 & 23) disposed on the insulating layer (20) and including a recess portion (combination of openings 220 & 230) vertically overlapping with the pad (210), wherein the protective layer (22/23) includes: a first portion (22 [paragraph 0031] Shih states, “first solder mask 22”) including a first part (220 [paragraph 0032] Shih states, “first openings 220”) of the recess portion (220/230); and a second portion (23 [paragraph 0033] Shih states, “second solder mask 23”) disposed on the first portion (22) and including a second part (230 [paragraph 0034] Shih states, “second openings 230”) of the recess portion (220/230) connected to the first portion (22), and wherein a width of the second part (230) of the recess portion (220/230) is greater than a width of the first part (220) of the recess portion (claimed structure shown in figure 2I), and wherein the width of the first part (220) of the recess portion is smaller than a width of the pad (210; claimed structure shown in figure 2I). Regarding claim 7 – Shih teaches the circuit board of claim 1, wherein the second part (fig. 2I, 230) of the recess portion (220/230) has a width greater than the width of the pad (210; claimed structure shown in figure 2I). Regarding claim 8 – Shih teaches the circuit board of claim 1, wherein the pad (fig. 2I, 210) includes a first pad (left pad) and a second pad (right pad) disposed adjacent to each other on the insulating layer (20), wherein the recess portion (220/230) includes: a first recess portion (left recess portion 220/230) vertically overlapping the first pad (left pad), and a second recess portion (right recess portion 220/230) vertically overlapping the second pad (right pad), wherein a spacing between the second part (230) of the first recess portion and the second part (230) of the second recess portion is smaller than a spacing between the first pad (left pad) and the second pad (right pad; claimed structure shown in annotated figure 2I below). PNG media_image1.png 478 910 media_image1.png Greyscale Regarding claim 12 – Shih teaches the circuit board of claim 1, wherein a width of an upper portion of the second part (fig. 2I, 230) of the recess portion (220/230) and a width of a lower portion of the second part (230) of the recess portion are greater than the width of the pad (210; figure 2I shows the entire second part having a greater width than that of the pad 210). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Ji et al. (US PG. Pub. 2022/0361324). Regarding claim 5 – Lee teaches the circuit board of claim 3 but fails to teach further comprising: a solder disposed on the surface treatment layer and disposed in the first part and the second part of the recess portion. Ji teaches a circuit board (fig. 6, 100A4 [paragraph 0065] Ji states, “printed circuit board 100A4”) further comprising: a solder (710 [paragraph 0068] Ji states, “connection metal 710 may be formed of tin (Sn), or an alloy containing tin (Sn), for example, a solder”) disposed on the surface treatment layer ([paragraph 0044] Ji states, “a surface treatment layer may be disposed in a region exposed by the third opening 530 of the first passivation layer 210 among the first and second circuit layers 121 and 122”) and disposed in the first part (530) and the second part (520) of the recess portion (see recess portion in 210 and 300). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board having a pad exposed by a recessed portion and a surface treatment layer on the exposed pad as taught by Lee with the inclusion of a solder on the surface treatment layer and disposed int eh first and second parts of the recess portion as taught by Ji because Ji states, “The first electrical connection metal 710 may physically and/or electrically connect a substrate having a printed circuit board 100A4 to an external entity.” [paragraph 0068]. Solder connections between elements provide a strong electrical & mechanical connection. Allowable Subject Matter Claims 13-16 are allowed. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. (US PG. Pub. 2023/0061167) discloses a pads with a stepped solder resist structure. Ishizuka (US PG. Pub. 2010/0319974) discloses a PWB with a stepped protective layer. Inagaki et al. (US PG. Pub. 2016/0081190) discloses a printed wiring board having a step feature. Saidou et al. (US PG. Pub. 2015/0382456) discloses a printed circuit board having a step feature Hara et al. (US Patent 9516753) discloses a wiring substrate with an upper and lower pad on outer insulating layers with exposed pads through a protective layer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN T SAWYER/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Aug 22, 2024
Application Filed
Sep 04, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+30.5%)
2y 5m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1050 resolved cases by this examiner. Grant probability derived from career allowance rate.

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