Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the application filed on 03/19/2024.
Claims 1-20 are currently pending.
Claims 1-20 are rejected.
Claims 3 and 15 are objected.
Claims 1 and 12 are independent claims.
- Claim Objection
6. Claim 3 is objected to because of the following informalities: “Contol” in line 4 should be “Control”, “correspoding” in line 6 should be “corresponding”. Appropriate correction is required.
7. Claim 15 is objected to because of the following informalities: “Contol” in line 4 should be “Control”, “correspoding” in line 6 should be “corresponding”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhanping Yin et al. (US 2011/0310855 A1), hereinafter Yin, in view of 3GPP(TSG RAN WG1 #107-e, e-Meeting, November 11th-19th, 2021,”Summary of [107-e-NR-7.1CRs-09] Issue#16 Discussion and clarification on maximum UCI size before UCI omission”), hereinafter 3GPP.
For claim 1, Yin teaches a method for providing a number of input bits for transmission of UCI (Uplink Control Information) from a UE (User Equipment), the method comprising:
computing a number of available bits for transmission and a transport block size TBS (Yin, Fig. 4 and paragraph 53.);
computing a maximum number of encoded UCI bits based on the number of available bits for transmission and the TBS (Yin, Figs. 2, 4 and paragraphs 45, 53.); and
transmitting the maximum number of UCI input bits to the UE for uplink transmission of UCI in a Physical Uplink Shared Channel (PUSCH) (Yin, Fig. 9 and paragraphs 96.).
3GPP further teaches computing a number of encoded UCI bits by adjusting the maximum number of encoded UCI bits in order to satisfy an effective coding rate (3GPP, section 3.2 Second Round.);
computing a maximum number of UCI input bits, corresponding to the number of encoded UCI bits, based on a computed multiplier (3GPP, section 3.2 Second Round.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught in Yin with 3GPP to have a method for providing a number of input bits for transmission of UCI (Uplink Control Information) from a UE (User Equipment), the method comprising: computing a number of available bits for transmission and a transport block size TBS; computing a maximum number of encoded UCI bits based on the number of available bits for transmission and the TBS; computing a number of encoded UCI bits by adjusting the maximum number of encoded UCI bits in order to satisfy an effective coding rate; computing a maximum number of UCI input bits, corresponding to the number of encoded UCI bits, based on a computed multiplier; and transmitting the maximum number of UCI input bits to the UE for uplink transmission of UCI in a Physical Uplink Shared Channel (PUSCH). Because faced with known decoder and coding-rate limits (1706-bit polar payload, maximum effective coding rate), it would be obvious to adjust the UCI bit budget computed from PUSCH resources so that the coding rate for UCI stays within those limits.
For claim 2, Yin and 3GPP further teach the method of claim 1, wherein computing the number of available bits for transmission and the TBS is based on a plurality of parameters comprising: a number of Physical Resource Blocks allocated to the UE (nPRB); a number of Resource Elements allocated for Phase Tracking Reference Signal symbols (nREPTRS); and a number of overhead bits (XOH) (Yin, Fig. 10 and paragraph 98.).
For claim 3, Yin and 3GPP further teach the method of claim 1,
wherein computing the maximum number of encoded UCI bits is further based on a maximum effective coding rate corresponding to a PUSCH decoder and based on a maximum effective UCI coding rate corresponding to a Physical Uplink Contol Channel (PUCCH) decoder (Yin, Fig. 10 and paragraph 98.); and
wherein the maximum effective coding rate correspoding to the PUSCH decoder and the maximum effective UCI coding rate corresponding to the PUCCH decoder are received from an upper layer processor of a base station (Yin, Fig. 10 and paragraph 66.).
For claim 4, Yin and 3GPP further teach the method of claim 3, wherein the maximum effective coding rate corresponding to the PUSCH decoder (Yin, Fig. 10 and paragraph 98.) and the maximum effective UCI coding rate corresponding to the PUCCH decoder comprise vendor-specific information (Yin, Fig. 10 and paragraph 43.).
For claim 5, Yin and 3GPP further teach the method of claim 3, wherein the base station comprises a gNodeB (Yin, Fig. 1 and paragraph 39.).
For claim 6, Yin and 3GPP further teach the method of claim 1 further comprising: computing a maximum number of UCI input bits for each of a plurality of UCI types (Yin, Fig. 14 and paragraph 121.).
For claim 7, Yin and 3GPP further teach the method of claim 6, wherein transmitting the maximum number of UCI input to the UE for uplink transmission of UCI in the PUSCH comprises: transmitting the maximum number of UCI input bits for each of the plurality of UCI types to the UE for uplink transmission of UCI in the PUSCH (Yin, Fig. 14 and paragraph 121.).
For claim 8, Yin and 3GPP further teach the method of claim 7, wherein the plurality of UCI types comprises: a hybrid automatic repeat request acknowledgement (HARQ-ACK) information; a Channel State Information Part 1 (CSI-P1); and a Channel State Information Part 2 (CSI-P2) (Yin, Fig. 10 and paragraphs 47, 49. See also 3GPP, background.).
For claim 9, Yin and 3GPP further teach the method of claim 6, wherein computing the maximum number of UCI input bits for each of the plurality of UCI types comprises, for each UCI type: computing a first value corresponding to a maximum number of input bits with a plurality of Cyclic Redundancy Check (CRC) bits; and computing a second value corresponding to a maximum number of input bits with the plurality of CRC bits removed (Yin, Fig. 2 and paragraphs 45-46.).
For claim 10, Yin and 3GPP further teach the method of claim 1 wherein computing the maximum number of UCI input bits, corresponding to the number of encoded UCI bits, based on a computed multiplier comprises: backing-out the maximum number of UCI inputs available to the UE prior to encoding (Yin, Fig. 2 and paragraph 57).
For claim 11, Yin and 3GPP further teach the method of claim 1, further comprising:
receiving the PUSCH with the UCI, from the UE, based on the maximum number of UCI input bits (Yin, Fig. 9 and paragraphs 96.).
For claim 12, Yin teaches a non-transitory memory encoded with machine readable instructions that, when executed by a processor (Yin, Fig. 1 item 102 and paragraph 39.), causes the processor to implement a process, comprising:
computing a number of available bits for transmission and a transport block size TBS (Yin, Fig. 4 and paragraph 53.);
computing a maximum number of encoded UCI bits based on the number of available bits for transmission and the TBS (Yin, Figs. 2, 4 and paragraphs 45, 53.); and
transmitting the maximum number of UCI input bits to the UE for uplink transmission of UCI in a Physical Uplink Shared Channel (PUSCH) (Yin, Fig. 9 and paragraphs 96.).
3GPP further teaches computing a number of encoded UCI bits by adjusting the maximum number of encoded UCI bits in order to satisfy an effective coding rate (3GPP, section 3.2 Second Round.);
computing a maximum number of UCI input bits, corresponding to the number of encoded UCI bits, based on a computed multiplier (3GPP, section 3.2 Second Round.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught in Yin with 3GPP to have a method comprising: computing a number of available bits for transmission and a transport block size TBS; computing a maximum number of encoded UCI bits based on the number of available bits for transmission and the TBS; computing a number of encoded UCI bits by adjusting the maximum number of encoded UCI bits in order to satisfy an effective coding rate; computing a maximum number of UCI input bits, corresponding to the number of encoded UCI bits, based on a computed multiplier; and transmitting the maximum number of UCI input bits to the UE for uplink transmission of UCI in a Physical Uplink Shared Channel (PUSCH). Because faced with known decoder and coding-rate limits (1706-bit polar payload, maximum effective coding rate), it would be obvious to adjust the UCI bit budget computed from PUSCH resources so that the coding rate for UCI stays within those limits.
For claim 13, Yin and 3GPP further teach the non-transitory memory of claim 12, wherein the non-transitory memory is coupled to a baseband processor within a base station (Yin, Fig. 1 and paragraph 39.).
For claim 14, Yin and 3GPP further teach the non-transitory memory of claim 13, wherein the base station is a gNodeB (Yin, Fig. 1 and paragraph 39.).
For claim 15, Yin and 3GPP further teach the non-transitory memory of claim 12,
wherein computing the maximum number of encoded UCI bits is further based on a maximum effective coding rate corresponding to a PUSCH decoder and based on a maximum effective UCI coding rate corresponding to a Physical Uplink Contol Channel (PUCCH) decoder (Yin, Fig. 10 and paragraph 98.); and
wherein the maximum effective coding rate correspoding to the PUSCH decoder and the maximum effective UCI coding rate corresponding to the PUCCH decoder are received from an upper layer processor of a base station (Yin, Fig. 10 and paragraph 66.).
For claim 16, Yin and 3GPP further teach the non-transitory memory of claim 15, wherein the maximum effective coding rate corresponding to the PUSCH decoder (Yin, Fig. 10 and paragraph 98.) and the maximum effective UCI coding rate corresponding to the PUCCH decoder comprise vendor-specific information (Yin, Fig. 10 and paragraph 43.).
For claim 17, Yin and 3GPP further teach the non-transitory memory of claim 12, wherein the process further comprises: computing a maximum number of UCI input bits for each of a plurality of UCI types (Yin, Fig. 14 and paragraph 121.).
For claim 18, Yin and 3GPP further teach the non-transitory memory of claim 17, wherein transmitting the maximum number of UCI input to the UE for uplink transmission of UCI in the PUSCH comprises: transmitting the maximum number of UCI input bits for each of the plurality of UCI types to the UE for uplink transmission of UCI in the PUSCH (Yin, Fig. 14 and paragraph 121.).
For claim 19, Yin and 3GPP further teach the non-transitory memory of claim 17, wherein computing the maximum number of UCI input bits for each of the plurality of UCI types comprises, for each UCI type: computing a first value corresponding to a maximum number of input bits with a plurality of Cyclic Redundancy Check (CRC) bits; and computing a second value corresponding to a maximum number of input bits with the plurality of CRC bits removed (Yin, Fig. 2 and paragraphs 45-46.).
For claim 20, Yin and 3GPP further teach the non-transitory memory of claim 12, further comprising: receiving the PUSCH with the UCI, from the UE, based on the maximum number of UCI input bits (Yin, Fig. 9 and paragraphs 96.).
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILL W LIN whose telephone number is (571)272-8749. The examiner can normally be reached M-F 8:00-5:00.
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/WILL W LIN/Primary Examiner, Art Unit 2412