DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114 was filed in this application 05/12/2026 after a decision by the Patent Trial and Appeal Board, but before the filing of a Notice of Appeal to the Court of Appeals for the Federal Circuit or the commencement of a civil action. The request, however, lacks the fee required by 37 CFR 1.17(e) and/or the submission required by 37 CFR 1.114. Accordingly, the RCE is improper and any time period running was not tolled by the filing of the improper request.
Response to Arguments
Applicant's arguments filed 05/12/2026 regarding the prior art rejections of Claims 16 and 31 have been fully considered and are persuasive. Applicant’s arguments with respect to claim(s) 16 and 31 have been considered but are moot in view of the new ground of rejection introduced because of the added limitations.
The Remarks argue that:
Paramanandam does not disclose a real time clock, do not disclose RTC volatile memory accessible by the processor, do not disclose continuous power to the RTC independently of a processor power switch, and do not disclose storing communication-establishment data and/or encryption keys in RTC volatile memory. Paramanandam does not teach the "first kind/second kind" storage scheme. Paramanandam's citation to low-power operation or recording injection entries does not teach avoiding non-volatile-memory erase operations by storing pairing, communication- establishment, or encryption data in continuously powered RTC volatile memory.
Vembu does not teach a drug-delivery-device RTC having volatile memory accessible by a processor, continuously powered independently of a processor power switch, and used to retain pairing, communication-establishment, or encryption- key data to avoid erasing flash memory. Regulation of CPU core power states in a computing platform is not a teaching of a continuously powered RTC volatile memory in a drug delivery device. Nor is it a teaching that communication-establishment data or encryption keys are stored in such RTC volatile memory.
The dependent claims are patentable for at least the same reasons, and several dependent claims recite additional limitations not taught or suggested by the applied references.
The Examiner agrees Paramanandam does not disclose a real time clock, do not disclose RTC volatile memory accessible by the processor, do not disclose continuous power to the RTC independently of a processor power switch, and do not disclose storing communication-establishment data and/or encryption keys in RTC volatile memory. Paramanandam does not teach the "first kind/second kind" storage scheme. Paramanandam's citation to low-power operation or recording injection entries does not teach avoiding non-volatile-memory erase operations by storing pairing, communication- establishment, or encryption data in continuously powered RTC volatile memory. However, with the new prior art, Otterstedt, in combination with Xie and Jayaraman the features recited in the amended independent claims 1, 14, and 20 can be deduced. The previous prior art rejection is maintained.
The Examiner agrees Vembu does not teach a drug-delivery-device RTC having volatile memory accessible by a processor, continuously powered independently of a processor power switch, and used to retain pairing, communication-establishment, or encryption- key data to avoid erasing flash memory. Regulation of CPU core power states in a computing platform is not a teaching of a continuously powered RTC volatile memory in a drug delivery device. Nor is it a teaching that communication-establishment data or encryption keys are stored in such RTC volatile memory.
However, as shown below, using the prior art references in combination with one another and not individually, one skilled in the art could conclude the claimed invention. The added prior art reference, Morris teaches continuous power to the RTC and RTC volatile memory through controller instruction. Vembu teaches the "first kind/second kind" storage scheme as it teaches dynamic and static data. These prior arts cure the deficiencies of Paramanandam which teaches a drug delivery device and communication-establishment data and/or encryption keys. Paramanandam also suggests continuous power disclosing power modes, reducing power without completely turning off power. For these reasons amended claims 16 and 31 have been rejected accordingly.
Claims 17 – 30 which depend from amended claim 16, have been considered and rejected.
Claims 32 – 35 which depend from amended claim 31, have been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 – 35 are rejected under 35 U.S.C. 103 as being unpatentable over PARAMANANDAM (WO 2020257137 A1) in view of Vembu (US 9582216 B2) in view of Morris (US 2017/0286194 A1).
With regards to claim 16, PARAMANANDAM teaches:
An electronic system configured for application in a drug delivery device or a drug delivery add-on device to implement a data storage, the electronic system comprising: a processor (0018, The controller 120 may include one or more processors; the controller 120 may include one or more electronic memory components, such as one or more registers, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and/or flash memory) a power switch for controlling powering of the processor, (0021 & 0005, One example of the low-power mode of the controller 120 may be a case in which power to the controller 120 is cut off, for example, by a switch external to the controller 120. Another example may be a so-called“sleep” mode of the controller 120. In some embodiments, the controller 120 may draw less power from the power source 1 14 of the drug delivery device 102 in the low-power mode than in active mode. To transition from the low-power mode to the active mode, the controller 120 may require a trigger corresponding to an external action, such as, for example, switching on the power or sending a“wake-up” signal to the controller 120. The controller is also configured to generate in the memory a data entry indicative of the injection and/or a state of the drug delivery device, and switch into the low-power mode subsequent to or contemporaneous with detecting that the injection mechanism has performed the injection.) data related to a use of the drug delivery device (0005, The controller is also configured to generate in the memory a data entry indicative of the injection and/or a state of the drug delivery device, and switch into the low-power mode subsequent to or contemporaneous with detecting that the injection mechanism has performed the injection.) to store, as the second kind of data, data related to communication and required for establishing a data transmission from the electronic system to an external computing device, and/or encryption data, (0035 & 0038, the processor 184 may store at least some of the information (e.g., a record of an injection) in the memory 186 and/or another digital storage module (not shown) of the user device 104. The communication between the wireless communication module 130 and the user device 104 may be encrypted using one or more encryption methods.)
PARAMANANDAM fails to teach:
for processing data for distinguishing between a first kind of data and a second kind of data, wherein the first kind of data is provided to not be changed over the lifetime of the drug delivery device and the second kind of data is provided to change over the lifetime of the drug delivery device; and wherein the processor is configured to store the first kind of data in the non-volatile memory and the second kind of data in the volatile memory.
However, Vembu teaches:
for processing data for distinguishing between a first kind of data and a second kind of data, wherein the first kind of data is provided to not be changed over the lifetime of the drug delivery device and the second kind of data is provided to change over the lifetime of the drug delivery device; and wherein the processor is configured to store the first kind of data in the non-volatile memory and the second kind of data in the volatile memory. (59, As mentioned above, according to many embodiments, the code is generally static, as the binary files do not change during execution. On the other hand, data may change or it may not change, depending on a type of data. For example, static data (e.g., constants) will not change but volatile data (e.g., a stored variable that is recalculated based on continually changing input) does change. Thus, code and static data can be placed in a read-only section of memory, whereas volatile data would generally be placed in a read/write section of memory.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of an electronic system configured for application in a drug delivery device of PARAMANANDAM with the teaching of Vembu, which teaches a first kind of data and a second kind of data and their distinctions in order to implement a structure to the memory storage based on the data retrieved (Vembu: 59, Then when the operating system 204 is allocating memory space to store the structure, it will see the “volatile” bit as set and know to allocate the structure in the volatile data section of DRAM memory space. Alternatively, if a data variable is declared as a constant value, the software application may clear the “volatile” bit to tell the operating system to allocate the data as static.)
PARAMANANDAM in view of Vembu fails to teach:
a real time clock comprising a volatile memory being accessible by the processor; wherein independently from a state of the power switch, the real time clock is configured to be continuously supplied with electric power to maintain data stored in the volatile memory, wherein the processor is configured to store at least a part of processed data in the volatile memory; in the volatile memory of the real time clock.
However, Morris teaches:
a real time clock comprising a volatile memory being accessible by the processor, (0135, The mobile computing device 430 may include a display 435, a memory 433, and a real time clock 434 for displaying, storing and tracking sensor information, respectively. The memory 433 may be a single memory device or multiple memory devices and may be a volatile or non-volatile memory for storing data and/or instructions for software programs and applications.) wherein independently from a state of the power switch, the real time clock is configured to be continuously supplied with electric power to maintain data stored in the volatile memory, wherein the processor is configured to store at least a part of processed data in the volatile memory (0125, the sensor electronics module 426 can include a potentiostat, a power source for providing power to continuous analyte sensor 422, other components useful for signal processing and data storage, and/or a telemetry module for transmitting data from itself to one or more mobile computing devices 430a-e. Electronics can be affixed to a printed circuit board (PCB), or the like, and can take a variety of forms. For example, the electronics can take the form of an integrated circuit (IC), such as an Application-Specific Integrated Circuit (ASIC), a microcontroller, and/or a processor.) in the volatile memory of the real time clock. (0135, The mobile computing device 430 may include a display 435, a memory 433, and a real time clock 434 for displaying, storing and tracking sensor information, respectively. The memory 433 may be a single memory device or multiple memory devices and may be a volatile or non-volatile memory for storing data and/or instructions for software programs and applications)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of an electronic system configured for application in a drug delivery device of PARAMANANDAM with the teaching of Morris, which teaches realtime clock and volatile memory in order to store wireless communication data. (Morris: 0135, for displaying, storing and tracking sensor information, respectively.)
With regards to claim 17, PARAMANANDAM teaches the electronic system of claim 16:
wherein the electronic component with the volatile memory is a real time clock with the volatile memory being accessible by the processor, and wherein the processor is configured to access the volatile memory and to store at least part of the processed data in the volatile memory (0003 & 0018, the external device can take time; The controller 120 may include one or more processors; the controller 120 may include one or more electronic memory components, such as one or more registers, random access memory (RAM)).
With regards to claim 18, PARAMANANDAM teaches the electronic system of claim 16:
wherein the processor is configured to store encryption data in the volatile memory (0023 & 0038, the controller 120 and the wireless communication module 130 may be in communicative connection with each other via a communication bus 128. The communication bus 128 may also communicatively connect other components including, for example, the memory 122, the removable storage device 124, the auxiliary circuitry 126, the mechanical drive 140, the controller 120 and/or to the wireless communication module 130. The communication between the wireless communication module 130 and the user device 104 may be encrypted using one or more encryption methods. The encryption may use symmetric and/or public keys).
With regards to claim 19, PARAMANANDAM teaches the electronic system of claim 18:
wherein the encryption data includes one or more encryption keys (0038, The communication between the wireless communication module 130 and the user device 104 may be encrypted using one or more encryption methods. The encryption may use symmetric and/or public keys).
With regards to claim 20, PARAMANANDAM teaches the electronic system of claim 16:
wherein the processor is configured to store data related to a use of the drug delivery device in the non-volatile memory (0018, Additionally or alternatively, the controller 120 may be in communicative connection with the removable storage device 124, such, as a flash drive, an SD (secure digital) card, and/or a microSD card).
With regards to claim 21, PARAMANANDAM teaches the electronic system of claim 20:
wherein the data related to the use of the drug delivery device includes data related to doses delivered with the drug delivery device (0003, Certain automated drug delivery devices include sensors and other electronics for monitoring use of the device. Information collected by such sensors can be wirelessly communicated to an external device such as a smartphone so that this information can be displayed to a user, stored in a memory, or made available to a healthcare provider).
With regards to claim 22, PARAMANANDAM teaches the electronic system of claim 20:
wherein the non-volatile memory has a storage size sufficient for storing entire data related to the use of the drug delivery device, the entire data comprising data related to doses delivered with the drug delivery device and generated during a lifetime of the drug delivery device (0061, the wireless communication module 130 may access an injection log and/or the drug delivery device state data records stored in the memory 122 or from the removable storage device 124).
With regards to claim 23, PARAMANANDAM teaches the electronic system of claim 16:
further comprising a communication interface for data transmission, wherein the processor is configured to store communication related data in the volatile memory (0020, The wireless communication module 130 may include, in communicative connection with at least one processing component, one or more memory components, such as one or more registers, RAM, ROM, EEPROM, and/or on-board flash memory).
With regards to claim 24, PARAMANANDAM teaches the electronic system of claim 23:
wherein the communication related data comprises data required for establishing a data transmission from the electronic system to an external computing device (0020, The wireless communication module 130 may include one or more communication components including at least one transmitter and at least one receiver).
With regards to claim 25, PARAMANANDAM teaches the electronic system of claim 16:
further comprising a primary battery or a cell as a power supply, wherein the primary battery or the cell is mounted together with other components of the electronic system on a printed circuit board and dimensioned to provide electric power over the lifetime of the drug delivery device (0016, the power source 114 is a rechargeable battery, configured to electrically connect to a charging circuit that may be disposed at least partially outside of the drug delivery device 102) wherein, during the lifetime, no erase operation of the non-volatile memory is carried out (0028, The one or more data entries may include error codes generated during self-test routines, the controller 120 detects using the sensors 160a-d, a failed injection attempt and generates a data entry in the injection log in response to the failed injection attempt. After generating the data entry, and also subsequent and/or in response to detecting that the injection mechanism completed an injection, the controller 120 may switch into a low-power mode).
With regards to claim 26, PARAMANANDAM teaches the electronic system of claim 16:
wherein the processor is configured to perform at least one check and/or correction cycle of the data stored or to be stored in the volatile memory to ensure data integrity (0028, The one or more data entries may include error codes generated during self-test routines, the controller 120 detects using the sensors 160a-d, a failed injection attempt and generates a data entry in the injection log in response to the failed injection attempt).
With regards to claim 27, PARAMANANDAM teaches the electronic system of claim 26:
wherein the processor is configured to perform as check cycles a checksum or hash value check on the data before storing the data in the volatile memory and storing the checksum or hash value alongside the stored data and after reading the data and the checksum or hash value from the volatile memory (0046, The controller 120 and the wireless communication module 130 may be configured to communicate with each other via a processor interface 210. The processor interface 210 may employ protocols with flow control that include request to send (RTS) and clear to send (CTS) signals as well as transmit (Tx) and receive (Rx) signals).
With regards to claim 28, PARAMANANDAM teaches the electronic system of claim 26:
wherein the processor is configured to perform as check cycles multiple read operations for reading data from the volatile memory repeatedly and to compare the repeatedly read data in order to detect transient errors (0046, The controller 120 and the wireless communication module 130 may be configured to communicate with each other via a processor interface 210. The processor interface 210 may employ protocols with flow control that include request to send (RTS) and clear to send (CTS) signals as well as transmit (Tx) and receive (Rx) signals).
With regards to claim 29, PARAMANANDAM teaches the electronic system of claim 26:
wherein the processor is configured to perform as a check cycle a read operation of data from the volatile memory after the data was stored in the volatile memory and to compare the read data with the written data in order to ensure the data was stored correctly (0018 & 0046, The memory 122 in the controller 120 or in communicative connection with the controller 120 may include one or more electronic memory components, such as one or more registers, random access memory (RAM), read-only memory (ROM); The controller 120 and the wireless communication module 130 may be configured to communicate with each other via a processor interface 210. The processor interface 210 may employ protocols with flow control that include request to send (RTS) and clear to send (CTS) signals as well as transmit (Tx) and receive (Rx) signals).
With regards to claim 30, PARAMANANDAM teaches the electronic system of claim 26:
wherein the processor is configured to perform as a correction cycle repeating a previous data storing operation in response to detecting, (0033, After broadcasting the message one or more times and/or repeatedly for a prescribed time interval, the wireless communication module 130 may switch into the low-power mode) during the check cycle, an error of the data stored during the previous data storing operation (0028, The one or more data entries may include error codes generated during self-test routines, the controller 120 detects using the sensors 160a-d, a failed injection attempt and generates a data entry in the injection log in response to the failed injection attempt).
With regards to claim 31, PARAMANANDAM in view of Vembu in view of Morris teaches the computer-implemented method and corresponds to claim 1 as analyzed accordingly.
With regards to claim 32, PARAMANANDAM in view of Vembu in view of Morris teaches the computer-implemented method of claim 31:
wherein the processing of data by the processor for distinguishing between a first kind of data and a second kind of data comprises: determining that a dataset among the data to be processed belongs to the first kind of data (Abstract, The controller is also configured to generate in memory a data entry indicative of the injection and/or a state of the drug delivery device) if the dataset contains data related to a use of the drug delivery device, and determining that a dataset among the data to be processed belongs to the second kind of data when the dataset contains data related to communication and/or encryption data (0063 & 0038, transmitting a message indicative of the first injection and/or the second injection. In some implementations, upon establishing the connection with the user device 104, the wireless communication module 130 sends a controller activation trigger; The communication between the wireless communication module 130 and the user device 104 may be encrypted using one or more encryption methods).
With regards to claim 33, PARAMANANDAM in view of Vembu in view of Morris teaches the computer-implemented method of claim 32:
wherein the data related to the use of the drug delivery device comprises data related to doses delivered with the drug delivery device, wherein the data related to communication comprises data required for establishing a data transmission from the electronic device to an external computing device, and the encryption data comprises one or more encryption keys (0038, The communication between the wireless communication module 130 and the user device 104 may be encrypted using one or more encryption methods. The encryption may use symmetric and/or public keys The wireless communication module 130 and the user device 104 may use Wired Equivalency Privacy (WEP), Wi-Fi Protected Access (WPA), and/or WPA2 wireless security protocols. In some implementations, to authenticate the wireless communication module 130 and/or the user device 104).
With regards to claim 34, PARAMANANDAM in view of Vembu in view of Morris teaches the computer-implemented method of claim 31:
further comprising: performing at least one check and/or correction cycle of the data stored or to be stored in the volatile memory to ensure data integrity, comprising performing one or more of the following: as check cycles a checksum or hash value check on the data before storing the data in the volatile memory and storing the associated checksum or hash value alongside the stored data and after reading the data and its associated checksum or hash value from the volatile memory (0028 & 0018, The one or more data entries may include error codes generated during self-test routines, the controller 120 detects using the sensors 160a-d, a failed injection attempt and generates a data entry in the injection log in response to the failed injection attempt. The memory 122 in the controller 120 or in communicative connection with the controller 120 may include one or more electronic memory components, such as one or more registers, random access memory (RAM)); as check cycles multiple read operations for reading data from the volatile memory repeatedly and comparing the repeatedly read data in order to detect transient errors; as a check cycle a read operation of data from the volatile memory after the data was stored in the volatile memory and comparing the read data with the written data in order to ensure the data was stored correctly; or as a correction cycle repeating a previous data storing operation if, during a check cycle, an error of the data stored during the previous data storing operation was detected (0046, The controller 120 and the wireless communication module 130 may be configured to communicate with each other via a processor interface 210. The processor interface 210 may employ protocols with flow control that include request to send (RTS) and clear to send (CTS) signals as well as transmit (Tx) and receive (Rx) signals).
With regards to claim 35, PARAMANANDAM in view of Vembu in view of Morris teaches the computer-implemented method of claim 31:
wherein the electronic component is a real time clock with the volatile memory accessible by the processor, and wherein the processor is configured to access the volatile memory and to store at least part of the processed data in the volatile memory (0003 & 0018, the external device can take time; The controller 120 may include one or more processors; the controller 120 may include one or more electronic memory components, such as one or more registers, random access memory (RAM)).
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
KUEHNI (EP 3734605 A1): An electronic unit of a drug delivery device is configured to prepare payload data comprising data items according to an allocation scheme, and to encrypt, based on an encryption key, transmit data including the payload data.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Applicant's amendments have been considered but are moot in view of the new prior art
introduced in the rejection presented in this Office action.
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should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 7/16/2026
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