DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2023/0306906 A1) in view of Han et al. (US 2024/0206226 A1).
As to claim 1, Yang teaches an array substrate (Yang, FIG. 1, [0057], an array substrate of “display device 100”), comprising a plurality of pixel driving circuits (Yang, FIGS. 1 and 36, [0058], the circuit for “pixels PXL”) and a plurality of third control signal lines (Yang, FIG. 36, [0061], “EBLi”);
wherein a respective pixel driving circuit (Yang, FIGS. 1 and 36, [0058], the circuit for “pixel PXL”) of the plurality of pixel driving circuits comprises a driving transistor (Yang, FIG. 36, [0082], “transistor T1 (or driving transistor)”), a data write transistor (Yang, FIG. 36, [0084], “transistor T2 (or switching transistor)”), a compensating transistor (Yang, FIG. 36, [0087], “transistor T5”), a third reset transistor (Yang, FIG. 36, [0091], “transistor T9 (or bias transistor)”), a first capacitor (Yang, FIG. 36, [0083], “hold capacitor CHOLD”) having a first capacitor electrode and a second capacitor electrode (Yang, see FIG. 36, [0083], Examiner interprets the capacitor node of “CHOLD” connected to “N4” as the 1st capacitor electrode), a second capacitor (Yang, FIG. 36, [0083], “storage capacitor CST”) having a third capacitor electrode and a fourth capacitor electrode (Yang, FIG. 36, [0083], Examiner interprets the capacitor node of “CST” connected to “N4” as the 4th capacitor electrode), and a third node connecting line (Yang, FIG. 36, the connecting line corresponding to “N4”);
wherein a respective third control signal line (Yang, FIG. 36, [0061], “EBLi”) of the plurality of third control signal lines is configured to provide control signals (Yang, FIG. 36, [0091], “bias control signal EB”) to a gate electrode of the third reset transistor (Yang, FIG. 36, [0091], “transistor T9 (or bias transistor)”);
wherein the third node connecting line (Yang, FIG. 36, the connecting line corresponding to “N4”) is connected to second electrodes of the compensating transistor (Yang, see FIG. 36, [0087], “transistor T5”) and the data write transistor (Yang, see FIG. 36, [0084], “transistor T2 (or switching transistor)”), and is connected to the first capacitor electrode (Yang, see FIG. 36, [0083], the capacitor node of “CHOLD” connected to “N4”) and the fourth capacitor electrode (Yang, FIG. 36, [0083], the capacitor node of “CST” connected to “N4”).
Yang does not teach “an orthographic projection of the third node connecting line on a base substrate at least partially overlaps with an orthographic projection of the respective third control signal line on the base substrate”.
However, Han teaches the concept that an orthographic projection of the third node connecting line (Han, FIG. 4, [0102], “connection line L2”) on a base substrate (Han, FIG. 1, [0107], “base substrate 10”) at least partially overlaps with an orthographic projection of the respective third control signal line (Han, FIG. 4B, [0142], “reset signal line RST2”) on the base substrate (Han, see FIGS. 2A, 3, 4E, 4G-4I, [0013] and [0102]).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “N4” taught by Yang to be configured as “N1”, as taught by Han, in order to reduce the load of resistor and ensure the sufficient writing of the signal, so as to effectively avoid the problem of static electricity (Han, [0095], [0104], and [0116]).
As to claim 3, Yang in view of Han teaches the array substrate of claim 1, further comprising a plurality of gate lines (Yang, FIG. 36, [0146], “write gate line GWLi”), a plurality of light emitting control signal lines (Yang, FIG. 36, [0242], “emission control line EML1i”), and a plurality of first control signal lines (Yang, FIG. 36, [0087], “compensation gate line GCLi”);
wherein the respective pixel driving circuit (Yang, FIGS. 1 and 36, [0058], the circuit for “pixel PXL”) further comprises a light emitting control transistor (Yang, FIG. 36, [0090], “transistor T8 (or first emission transistor)”) and a first reset transistor (Yang, FIG. 36, [0086], “transistor T4 (or initialization transistor)”);
a respective gate line (Yang, FIG. 36, [0146], “write gate line GWLi”) of the plurality of gate lines is configured to provide gate scanning signals (Yang, FIG. 36, [0084], “write gate signal GW (or first gate signal)”) to a gate electrode of the data write transistor (Yang, see FIG. 36, [0084], “transistor T2 (or switching transistor)”);
a respective light emitting control signal line (Yang, FIG. 36, [0242], “emission control line EML1i”) of the plurality of light emitting control signal lines is configured to provide light emitting control signals (Yang, FIG. 36, [0090], “emission control signal EM1”) to a gate electrode of the light emitting control transistor (Yang, FIG. 36, [0090], “transistor T8 (or first emission transistor)”);
a respective first control signal line (Yang, FIG. 36, [0087], “compensation gate line GCLi”) of the plurality of first control signal lines is configured to provide control signals (Yang, FIG. 36, [0085], “compensation gate signal GC”) to a gate electrode of the first reset transistor (Yang, FIG. 36, [0086], “transistor T4 (or initialization transistor)”);
wherein the orthographic projection of the third node connecting line (Han, FIG. 4, [0102], “connection line L2”) on the base substrate (Han, FIG. 1, [0107], “base substrate 10”) at least partially overlaps with an orthographic projection of at least one of the respective light emitting control signal line, the respective first control signal line, an active layer of the driving transistor, the third capacitor electrode ([0127], “electrode plate CC1 and/or CC2” of “storage capacitor Cst”), or a unitary structure comprising the first capacitor electrode and the fourth capacitor electrode on the base substrate. Examiner renders the same motivation as in claim 1.
As to claim 7, Yang in view of Han teaches the array substrate of claim 1, further comprising a plurality of light emitting control signal lines (Yang, FIG. 36, [0242], “emission control line EML1i”);
wherein the respective pixel driving circuit (Yang, FIGS. 1 and 36, [0058], the circuit for “pixel PXL”) further comprises a light emitting control transistor (Yang, FIG. 36, [0090], “transistor T8 (or first emission transistor)”);
a respective light emitting control signal line (Yang, FIG. 36, [0242], “emission control line EML1i”) of the plurality of light emitting control signal lines is configured to provide light emitting control signals (Yang, FIG. 36, [0090], “emission control signal EM1”) to a gate electrode of the light emitting control transistor (Yang, see FIG. 36, [0090], “transistor T8 (or first emission transistor)”); and
the orthographic projection of the third node connecting line (Han, FIG. 4, [0102], “connection line L2”) on the base substrate (Han, FIG. 1, [0107], “base substrate 10”) at least partially overlaps with an orthographic projection of the respective light emitting control signal line (Han, e.g., see FIGS. 4B-4H, [0128], “light-emitting control signal line EM2”) on the base substrate (Han, FIG. 1, [0107], “base substrate 10”). Examiner renders the same motivation as in claim 1.
As to claim 9, Yang in view of Han teaches the array substrate of claim 1, further comprising a plurality of first control signal lines (Yang, FIG. 36, [0087], “compensation gate line GCLi”);
wherein the respective pixel driving circuit (Yang, FIGS. 1 and 36, [0058], the circuit for “pixel PXL”) further comprises a first reset transistor (Yang, FIG. 36, [0086], “transistor T4 (or initialization transistor)”);
a respective first control signal line (Yang, FIG. 36, [0087], “compensation gate line GCLi”) of the plurality of first control signal lines is configured to provide control signals (Yang, FIG. 36, [0085], “compensation gate signal GC”) to a gate electrode of the first reset transistor (Yang, FIG. 36, [0086], “transistor T4 (or initialization transistor)”);
the orthographic projection of the third node connecting line (Han, FIG. 4, [0102], “connection line L2”) on the base substrate (Han, FIG. 1, [0107], “base substrate 10”) at least partially overlaps with an orthographic projection of the respective first control signal line (Han, see FIGS. 4A-4H, [0142], “reset signal line RST1”) on the base substrate (Han, FIG. 1, [0107], “base substrate 10”). Examiner renders the same motivation as in claim 1.
As to claim 20, Yang teaches a display apparatus (Yang, FIG. 1, [0057], “display device 100”), comprising the array substrate (Yang, FIG. 1, [0057], an array substrate of “display device 100”) of claim 1, and one or more integrated circuits (Yang, FIG. 1, e.g., “gate driver 121 122 123”, “data driver 130”, “timing controller 140”, etc.) connected to the array substrate (Yang, see FIG. 1).
Allowable Subject Matter
Claims 2, 4-6, 8 and 10-19 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, the closest known prior art, i.e., Yang et al. (US 2023/0306906 A1), Han et al. (US 2024/0206226 A1), Wu et al. (CN 104200771 A, IDS), Qing et al. (CN 115911056 A, IDS), Zhang et al. (CN 115798407 A, IDS), Kang et al. (US 2023/0069447 A1, IDS), Long et al. (US 2022/0359640 A1), Jang et al. (US 2021/0201827 A1), Park et al. (US 2024/0096282 A1) and Jang et al. (US 2021/0201827 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein the respective third control signal line comprises multiple branches including a respective third control signal line third branch in a third gate metal layer; and the orthographic projection of the third node connecting line on the base substrate at least partially overlaps with an orthographic projection of the respective third control signal line third branch on the base substrate”.
As to claim 4, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein the orthographic projection of the third node connecting line on the base substrate at least partially overlaps with each of orthographic projections of the respective light emitting control signal line, the respective first control signal line, an active layer of the driving transistor, the third capacitor electrode, and a unitary structure comprising the first capacitor electrode and the fourth capacitor electrode on the base substrate”.
As to claim 5, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “unitary structure comprising the first capacitor electrode and the fourth capacitor electrode on the base substrate”.
As to claim 6, it depends from claim 5, and is allowable at least for the same reason above.
As to claim 8, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein the respective light emitting control signal line comprises a first portion and a second portion connected to each other; the first portion has a first average line width; the second portion has a second average line width; the first average line width is greater than the second average line width; an orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of the third node connecting line on the base substrate; an orthographic projection of the second portion on the base substrate is non-overlapping with the orthographic projection of the third node connecting line on the base substrate; the second portion comprises a gate electrode of the light emitting control transistor; and the first portion does not comprise any portion of the gate electrode of the light emitting control transistor”.
As to claim 10, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein the respective first control signal line comprises multiple branches in different layers; a respective branch of the multiple branches comprises a third portion, a fourth portion, and a fifth portion; the third portion has a third average line width; the fourth portion has a fourth average line width; the fifth portion has a fifth average line width; the third average line width is greater than the fourth average line width; the fifth average line width is greater than the fourth average line width; an orthographic projection of the fourth portion on the base substrate at least partially overlaps with an orthographic projection of the third node connecting line on the base substrate; an orthographic projection of the third portion on the base substrate is non- overlapping with the orthographic projection of the third node connecting line on the base substrate; an orthographic projection of the fifth portion on the base substrate is non- overlapping with the orthographic projection of the third node connecting line on the base substrate; the third portion comprises at least a portion of a gate electrode of the first reset transistor; the fifth portion comprises at least a portion of a gate electrode of the compensating transistor; and the fourth portion does not comprise any portion of the gate electrode of the first reset transistor or the gate electrode of the compensating transistor”.
As to claim 11, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “a first electrode of the driving transistor and a second electrode of the light emitting control transistor are parts of a unitary structure; a first electrode of the compensating transistor and a second electrode of the third reset transistor are parts of a unitary structure; and the second node connecting line is connected to the second electrode of the light emitting control transistor and the first electrode of the driving transistor through a third via, and connected to the second electrode of the third reset transistor and the first electrode of the compensating transistor thorough a fourth via”.
As to claim 12, it depends from claim 11, and is allowable at least for the reason above.
As to claim 13, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein two adjacent second fanout connecting lines of the plurality of second fanout connecting lines are between two adjacent data lines of the plurality of data lines configured to provide data signals to two adjacent pixel driving circuits in a same row; and a respective data line of the plurality of data lines is between a second fanout connecting line and a second voltage supply line”.
As to claim 14, it depends from claim 13, and is allowable at least for the reason above.
As to claim 15, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “an orthographic projection of the respective gage line on the base substrate is substantially non-overlapping with an orthographic projection of the first node connecting line on the base substrate”.
As to claims 16-17, they depend from claims 15, and are allowable at least for the same reason above.
As to claim 18, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the orthographic projection of the respective gate line on the base substrate and the orthographic projection of the second capacitor electrode on the base substrate are spaced apart by an orthographic projection of the respective first control signal line on the base substrate; the orthographic projection of the respective first control signal line on the base substrate is substantially non-overlapping with the orthographic projection of the respective gate line on the base substrate, and is substantially non-overlapping with the orthographic projection of the second capacitor electrode on the base substrate; and an overlapping area between the orthographic projection of the third node connecting line on the base substrate and the orthographic projection of at least one of the respective light emitting control signal line, the respective first control signal line, the respective third control signal line, the respective gate line on the base substrate is no greater than a third of an area of the orthographic projection of the third node connecting line on the base substrate”.
As to claim 19, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein a respective first reset signal line of the plurality of first reset signal lines comprises a plurality of loops arranged along a direction substantially parallel to first direction; and a respective loop of the plurality of loops is connected to first electrodes of two adjacent first reset transistors of two adjacent pixel driving circuits in a same row”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached on (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Feb. 19, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2621
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