DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the first rate of change" and “the second rate of change”. There is insufficient antecedent basis for this limitation in the claim. The examiner notes that "a first rate of change" and “a second rate of change” were mentioned in claim 3 and that it appears that claim 7, from which claim 8 depends, was possibly meant to depend on claim 3.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al. (U.S. Pub. No. 20210021782).
Regarding claim 1, Sato discloses:
An imaging device comprising:
a plurality of pixels configured to perform photoelectrical conversion (in the pixel unit 10, a plurality of pixels 12 arranged in a matrix to form a plurality of rows and a plurality of columns are provided, and each of the pixels 12 includes a photoelectric converter formed of a photoelectric conversion element such as a photodiode and outputs a pixel signal in accordance with a light amount of incident light, par. 21);
a plurality of comparators (comparator unit 42 on each column where comparator unit 42 on each column of the comparator circuit 40 may be formed of a differential input type comparator 44 where comparator 44 has two input nodes and one output node, par. 25, 39, 40, and Figs. 1 and 3) each including a first input section configured to receive a pixel signal from a corresponding one of the pixels (one input node of the comparator 44 is connected to the output line 16 on a corresponding column via the capacitor C0, where photoelectric converter PD converts (photoelectrically converts) incident light into an amount of charges in accordance with the light amount and accumulates generated charges and transfer transistor M1 transfers charges held in the photoelectric converter PD to the floating diffusion portion FD and amplifier transistor M3 outputs a signal in accordance with the voltage of the floating diffusion portion FD to the output line 16 via the select transistor M4, par. 38, 40, 44) and a second input section configured to receive a reference signal (the other input node of the comparator 44 is connected to the reference signal line 48 via the capacitor C1, par. 40) to be compared with the pixel signal (comparator 44 compares the level of the N-signal and the level of the ramp signal RAMP and comparator 44 compares the level of the (S+N)-signal and the level of the ramp signal RAMP, par. 49), the comparators being provided in correspondence with the plurality of respective pixels (comparator unit 42 on each column of the comparator circuit 40 may be formed of a differential input type comparator 44 and output terminal of the comparator 44 is connected to the storage unit 52 on a corresponding column, where each output line 16 is connected to the pixels 12 aligned in the second (vertical/column direction) direction, respectively, to form a signal line common to these pixels 12, par. 23, 39, 40 and Figs. 1 and 3);
a reference signal line configured to transmit the reference signal (reference signal line 48 connected to comparator 44 where reference signal generation circuit 46 outputs a reference signal having a predetermined amplitude to the comparator units 42 on respective columns via the reference signal line 48 and the reference signal is a ramp signal, par. 26 and 40); and
a setting circuit provided between the reference signal line and the second input section (capacitors C1, C2, and CP and switches SW1 and SW2 connected between reference signal line 48 and comparator 44, par. 39-40 and Fig. 3) and configured to set a rate of change of a voltage level of the reference signal over time (the amplitude (slope) of the ramp signal RAMP can be changed by appropriately controlling the switches SW1 and SW2 of the comparator unit 42, where by changing the amplitude (slope) of the ramp signal RAMP input to the comparator 44, it is possible to switch the AD conversion gain, par. 54 and Fig. 3).
Regarding claim 13, Sato further discloses:
the setting circuit is formed on a same substrate as the plurality of pixels (photoelectric conversion device 100 according to the present embodiment includes a pixel unit 10, a vertical scanning circuit 30, a comparator circuit 40, a reference signal generation circuit 46, a storage circuit 50, a counter circuit 58, a horizontal scanning circuit 60, a signal processing circuit 70, and a control circuit 80 and imaging device 201 is the photoelectric conversion device 100 and the AD conversion unit that is a part of the signal processing unit 208 may be formed on a semiconductor substrate on which the imaging device 201 is provided or formed on a semiconductor substrate separately from the imaging device 201, par. 20, 89, and 90).
Regarding claim 15, Sato discloses:
An imaging device comprising:
a plurality of pixels configured to perform photoelectric conversion (in the pixel unit 10, a plurality of pixels 12 arranged in a matrix to form a plurality of rows and a plurality of columns are provided, and each of the pixels 12 includes a photoelectric converter formed of a photoelectric conversion element such as a photodiode and outputs a pixel signal in accordance with a light amount of incident light, par. 21);
a comparator (comparator unit 42 on each column where comparator unit 42 on each column of the comparator circuit 40 may be formed of a differential input type comparator 44 where comparator 44 has two input nodes and one output node, par. 25, 39, 40, and Figs. 1 and 3) including a first input section configured to receive a pixel signal from a corresponding one of the pixels (one input node of the comparator 44 is connected to the output line 16 on a corresponding column via the capacitor C0, where photoelectric converter PD converts (photoelectrically converts) incident light into an amount of charges in accordance with the light amount and accumulates generated charges and transfer transistor M1 transfers charges held in the photoelectric converter PD to the floating diffusion portion FD and amplifier transistor M3 outputs a signal in accordance with the voltage of the floating diffusion portion FD to the output line 16 via the select transistor M4, par. 38, 40, 44) and a second input section configured to receive a reference signal to be compared with the pixel signal (the other input node of the comparator 44 is connected to the reference signal line 48 via the capacitor C1, par. 40) to be compared with the pixel signal (comparator 44 compares the level of the N-signal and the level of the ramp signal RAMP and comparator 44 compares the level of the (S+N)-signal and the level of the ramp signal RAMP, par. 49);
a reference signal line configured to transmit the reference signal to the second input section (reference signal line 48 connected to comparator 44 where reference signal generation circuit 46 outputs a reference signal having a predetermined amplitude to the comparator units 42 on respective columns via the reference signal line 48 and the reference signal is a ramp signal, par. 26 and 40); and
a setting circuit provided between the reference signal line and the second input section (capacitors C1, C2, and CP and switches SW1 and SW2 connected between reference signal line 48 and comparator 44, par. 39-40 and Fig. 3) and configured to set a rate of change of a voltage level of the reference signal over time (the amplitude (slope) of the ramp signal RAMP can be changed by appropriately controlling the switches SW1 and SW2 of the comparator unit 42, where by changing the amplitude (slope) of the ramp signal RAMP input to the comparator 44, it is possible to switch the AD conversion gain, par. 54 and Fig. 3),
wherein the comparator and the setting circuit are shared by the plurality of pixels (comparator unit 42 on each column of the comparator circuit 40 may be formed of a differential input type comparator 44 and output terminal of the comparator 44 is connected to the storage unit 52 on a corresponding column, where each output line 16 is connected to the pixels 12 aligned in the second (vertical/column direction) direction, respectively, to form a signal line common to these pixels 12, par. 23, 39, and 40 and Figs. 1 and 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (U.S. Pub. No. 20210021782).
Regarding claim 14, Sato further discloses:
a first substrate having provided thereon the plurality of pixels; and a second substrate having provided thereon the setting circuit (in such a way, the comparator circuit 40 and the storage circuit 50 form an AD converter circuit that performs analog-to-digital conversion on a pixel signal output from the pixel 12 from an analog signal to a digital signal, where photoelectric conversion device 100 according to the present embodiment includes a pixel unit 10, and imaging device 201 is the photoelectric conversion device 100 and the AD conversion unit that is a part of the signal processing unit 208 may be formed on a semiconductor substrate on which the imaging device 201 is provided or formed on a semiconductor substrate separately from the imaging device 201, par. 20, 29, 89, and 90).
Sato is silent with regards to the second substrate stacked on the first substrate. Official Notice is taken that it was well known before the effective filing date of the claimed invention to include stacking pixel circuit and pixel signal processing substrates. This is advantageous in that miniaturization of circuits can be achieved as well as lowered power requirements due to minimal distance between circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include second substrate stacked on the first substrate.
Claim 2-7 and 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, no prior art could be located that teaches or fairly suggests a second capacitive element provided between the second input section and a ground voltage source, a first transistor of a first conductivity type provided between the second capacitive element and the ground voltage source, and a second transistor of a second conductivity type provided between a node between the second capacitive element and the first transistor, and the reference signal line, the second transistor having a gate connected to a gate of the first transistor in common, in combination with the rest of the limitations of the claim and parent claim.
Claims 3-8 depend on claim 2 and therefore are objected to.
Regarding claim 9, no prior art could be located that teaches or fairly suggests comparators each execute determination processing of comparing the reference signal with the pixel signal to determine whether a voltage level of the pixel signal is higher or lower than a first threshold, and the setting circuit sets the rate of change of the reference signal for each of the pixels on a basis of a determination result of the determination processing, in combination with the rest of the limitations of the claim and parent claim.
Claim 10 and 12 depend on claim 9 and therefore are rejected.
Regarding claim 11, no prior art could be located that teaches or fairly suggests a determination circuit configured to determine whether a voltage level of the pixel signal is higher or lower than a second threshold, wherein the setting circuit sets the rate of change of the reference signal for each of the pixels on a basis of a determination result of the determination circuit, in combination with the rest of the limitations of the claim.
It is noted that claim 8 would be allowable as dependent on claim 7 if claim 7 were allowed and claim 8 was amended to overcome the 35 USC 112 rejection above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS G GILES whose telephone number is (571)272-2824. The examiner can normally be reached M-F 6:45AM-3:15PM EST (HOTELING).
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/NICHOLAS G GILES/ Primary Examiner, Art Unit 2639