DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
This Office Action is in response to the amended application filed on March 26, 2026. The Remarks of March 26, 2026 have been fully considered and are addressed as follows.
The Remarks regarding the objections to the Drawings are considered. The amendment to claim 6 overcome the objection to the Drawings and the objection is withdrawn. The replacement sheet to Fig. 1 is accepted. There are no further objections to the drawing.
The Remarks regarding the objections to the Specification are considered. The Abstract included in the amendments is accepted. There are no further objections to the Specification.
The Remarks regarding the objections to the Claims are considered. The respective amendments to claims 1, 8, and 11 are accepted. The objections to these claims are withdrawn.
The Remarks regarding the 103 rejections of the Claims are considered and are addressed as follows.
Regarding the amended claims 1 and 8, the applicant (page 9) argues:
“Independent claims 1 and 8 state that the first via hole is partially filled with the first via and the second via hole is partially filled with the second via. The Examiner states on page 4 of the Office Action that it "is also well-known in the art that a via could be formed by depositing conductive material on the inner wall of a via hole ...". The Examiner provides no support for this statement. Yun shows the via holes 931 and 932 being completely filled with the vias, and provides no teaching or suggestion that they can only be partially filled with vias.”
Applicant's arguments have been considered but are moot in view of the new ground(s) of rejection. The applicant (pp. 9-10) further argues “that the interconnect in Yun is not provided within a feed layer”. The examiner respectfully disagrees. Yun (Fig. 12; [0149]) discloses: “the plurality of conductive layers 901 and the plurality of via holes 931 and 932 may form a plurality of feeding paths 941 and 942”. A person skilled in the art knows that a PCB structure with a feeding path includes a feed layer, which may comprise a transmission line – for example, a coplanar waveguide transmission line or a microstrip transmission line, connecting the corresponding vias to provide a signal path from the IC circuit 250 to the antenna element 950 (see, [0150]). The interconnect shown in the annotated Fig. 12 in Yun below is a part of the feeding path connecting the vias and, thus, is in the feed layer.
The applicant (p. 10) further argues that Yun does not teach “prepregs buildup layers” and “at least one beamforming integrated circuit (IC) formed on the prepreg buildup layers on one side of the PCB structure.” The examiner respectfully disagrees. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. In this regard, Navarro (Fig. 6; col. 9, lines 39-59) teaches a PCB structure (layers 529), buildup layers (527) on one side of the PCB structure, wherein the buildup layers are only prepreg layers (see col. 9, lines 39-48), and an integrated circuit (540) disposed on top of the buildup layers. Navarro (Figs. 11A-11B; col. 14, lines 24-57) further teaches that the integrated circuit (540) may comprise at least one beamforming circuit (see col. 14, lines 51-52). It would be obvious to one of ordinary skill in the art to modify Yun by substituting the buildup layers and the integrated circuit of Yun with the buildup layers and the beamforming circuit of Navarro. In regards with the buildup layers, this modification would provide a thinner PCB structure to accommodate the desired space requirements for the PCB (see Navarro, col. 9, lines 53-56). In regards with the beamforming integrated circuit, this modification would provide an antenna which can perform beamforming operations (see Navarro, col. 1, lines 49-51).
The applicant (p. 11) further argues that “Navarro does not teach or suggest partially filled via holes or an interconnect provided in a feed layer that electrically connects a top via and a bottom via.” Applicant's arguments have been considered but are moot in view of the new ground(s) of rejection.
Regarding the amendment to claims 1 and 8 “the buildup layers are only prepreg layers “, the amendment necessitates new ground(s) of rejection based on a new Prior Art reference. In light of this, the applicant’s arguments that the cited prior art references do not teach the limitation in question are moot.
Regarding the amended claims 3 and 10, the amendments to the claims necessitate new ground(s) of rejection based on a new Prior Art reference. In light of this, the applicant’s arguments that the cited prior art references do not teach the amended claims are moot.
Furthermore, "[a]ny judgment on obviousness is in a sense necessarily a reconstruction based on hindsight reasoning, but so long as it takes into account only knowledge which was within the level of ordinary skill in the art at the time the claimed invention was made and does not include knowledge gleaned only from applicant’s disclosure, such a reconstruction is proper." In re McLaughlin, 443 F.2d 1392, 1395, 170 USPQ 209, 212 (CCPA 1971).
Also, the factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim Objections
Claims 2, 9-10, 13, and 15-16 are objected to because of the following informalities:
Claim 2 (line 3) and claim 9 (line 3): “the beam forming IC” should be amended to “the beamforming IC”;
Claims 9-10 and 15-16: “The antenna according to claim 8” should be amended to “The phased array antenna according to claim 8”;
Claim 9 (line 5): “the at least one antenna radiating element” should be amended to “the at least one patch antenna radiating element”;
Claim 13 (lines 1-2): “the portion of the first via hole” should be amended to “a portion of the first via hole”;
Claim 13 (lines 2-3): “the portion of the second via hole” should be amended to “a portion of the second via hole”;
Claim 15 (lines 1-2): “the portion of the first via hole” should be amended to “a portion of the first via hole”;
Claim 15 (lines 2-3): “the portion of the second via hole” should be amended to “a portion of the second via hole”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 (lines 9-10) and claim 8 (lines 9-10) recite “the buildup layers are only prepreg layers”. Previously in these claims, two distinct sets of buildup layers have been defined – “buildup layers formed on the one side of the PCB structure” and “buildup layers formed on the opposite side of the PCB structure”. Therefore, it is not clear whether “the buildup layers” in the limitation recited above refer to “buildup layers formed on the one side of the PCB structure”, “buildup layers formed on the opposite side of the PCB structure”, or all buildup layers. For examination purposes, this limitation is interpreted as: “first buildup layers formed on the one side of the PCB structure and second buildup layers formed on the opposite side of the PCB structure, wherein both the first buildup layers and the second buildup layers are only prepreg layers”.
Claim 1 (lines 11-12 and 13-14) and claim 8 (lines 11-12 and 13-14) recite “the prepreg buildup layers”. The scope of these claims is indefinite because prepreg buildup layers have not been previously defined. Further, it is not clear whether “the prepreg buildup layers” are different from the buildup layers recited earlier in the claims, and, if not, which of the buildup layers the term refers to.
Claims 2-7 and 12-14 inherit the indefiniteness of claim 1 and are subsequently rejected, as well.
Claims 9-11 and 15-16 inherit the indefiniteness of claim 1 and are subsequently rejected, as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US 20200212539 A1, hereinafter Yun) in view of Thurairajaratnam et al. (US 20130098671 A1, hereinafter Thurai), Navarro et al. (US 10074900 B2, hereinafter Navarro), and Alpman et al. (US 20200091608 A1, hereinafter Alpman).
Regarding claim 1, as best understood, Yun (Fig. 12; [0143-0150]) discloses an antenna (240) comprising:
a printed circuit board (PCB) structure including a plurality of layers (regarding the PCB structure including a plurality of layers, see annotated Fig. 12 in Yun below), said PCB structure including a first via hole (regarding the first via hole, see annotated Fig. 12 in Yun below) formed into the plurality of layers through one side of the PCB structure and filled with a first via (regarding the first via, see annotated Fig. 12 in Yun below) and a second via hole (regarding the second via hole, see annotated Fig. 12 in Yun below) formed into the plurality of layers through an opposite side of the PCB structure and filled with a second via (regarding the second via, see annotated Fig. 12 in Yun below), wherein the first and second vias are electrically coupled by an interconnect (regarding the interconnect, see annotated Fig. 12 in Yun below);
buildup layers formed on the one side of the PCB structure and buildup layers formed on the opposite side of the PCB structure (regarding the buildup layers formed on the one side of the PCB structure and the buildup layers formed on the opposite side of the PCB structure, see annotated Fig. 12 in Yun below);
at least one integrated circuit (IC) (250) formed on the buildup layers on the one side of the PCB structure; and
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at least one antenna radiating element (950) formed on the buildup layers on the opposite side of the PCB structure.
Yun does not explicitly disclose partially filled first and second vias, the IC is at least one beamforming integrated circuit and the limitation wherein the buildup layers are only prepreg layers.
Thurai (Fig. 1) teaches a via hole (the via hole associated with via 140) formed into a plurality of layers of a PCB structure and partially filled with a via (140).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the first via hole is partially filled with a first via and the second via hole is partially filled with a second via as taught by Thurai. This modification would provide a first via and a second via which extend to and connect the desired signal traces (see Thurai, [0037]).
The modified Yun does not explicitly teach beamforming integrated circuit and the limitation wherein the buildup layers are only prepreg layers.
Navarro (Fig. 6; col. 9, lines 39-59) teaches a PCB structure (layers 529), buildup layers (527) on one side of the PCB structure, wherein the buildup layers are prepreg layers (see col. 9, lines 39-48), and an integrated circuit (540) disposed on top of the buildup layers. Navarro (Figs. 11A-11B; col. 14, lines 24-57) further teaches that the integrated circuit (540) may comprise at least one beamforming circuit (see col. 14, lines 51-52).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun by substituting the integrated circuit of Yun with the beamforming circuit of Navarro. This modification would provide an antenna which can perform beamforming operations (see Navarro, col. 1, lines 49-51).
The modified Yun does not teach the limitation wherein the buildup layers are only prepreg layers.
Alpman ([1200]) teaches a PCB structure (10005) comprising buildup layers formed on one side of the PCB structure and buildup layers formed on an opposite side of the PCB structure, wherein the buildup layers are only prepreg layers.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun by substituting the buildup layers of Yun with the buildup layers of Alpman, wherein the buildup layers are only prepreg layers. This modification would provide a more compact antenna due to the prepreg layers being very thin (see Alpman, [1200]).
Regarding claim 2, as best understood, the modified Yun teaches the antenna of claim 1 as addressed above.
The modified Yun does not explicitly teach the limitation wherein the prepreg buildup layers on the one side of the PCB structure include microvias electrically coupled to the beam forming IC and the first via and the prepreg buildup layers on the opposite side of the PCB structure include microvias electrically coupled to the at least one antenna radiating element and the second via.
Navarro (col. 17, lines 63-67 and col. 18, lines 1-6) teaches the PCB structure (525) comprises microvias to connect the IC (540) to antenna elements (560).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the prepreg buildup layers on the one side of the PCB structure include microvias electrically coupled to the beam forming IC and the first via and the buildup prepreg layers on the opposite side of the PCB structure include microvias electrically coupled to the at least one antenna radiating element and the second via. This modification would allow for increased electronic circuit packaging density (see Navarro, col. 3, lines 60-67 and col. 4, lines 1-5).
Regarding claim 4, as best understood, the modified Yun teaches the antenna of claim 1 as addressed above.
Yun (Fig. 12; [0147]) further teaches the at least one antenna radiating element (950) is a patch antenna radiating element.
Regarding claim 5, as best understood, the modified Yun teaches the antenna of claim 1 as addressed above.
Yun (Fig. 12; [0149]) further teaches the interconnect (regarding the interconnect, see annotated Fig. 12 in Yun above) is in a feed layer (regarding the feed layer see annotated Fig. 12 in Yun above; [0149] discloses: “the plurality of conductive layers 901 and the plurality of via holes 931 and 932 may form a plurality of feeding paths 941 and 942”; a person skilled in the art knows that a PCB structure with a feeding path includes a feed layer, which may comprise a transmission line – for example, a coplanar waveguide transmission line or a microstrip transmission line, connecting the corresponding vias to provide a signal path from the IC circuit 250 to the antenna element 950 (see, [0150]); the interconnect shown in the annotated Fig. 12 in Yun above is a part of the feeding path connecting the vias and, thus, is in the feed layer) in the PCB structure.
Regarding claim 6, as best understood, the modified Yun teaches the antenna of claim 1 as addressed above.
The modified Yun does not teach explicitly the limitation the antenna is a phased array antenna.
Navarro (11A-B; col. 14, lines 51-53) teaches a phased array antenna (col. 14, lines 51-53 discloses “Integrated circuit die 540 may provide beamforming circuits for four antenna elements 660 d through 660 g.”; it is well-known in the art that multiple antenna elements connected to beamforming circuits provide a phased array antenna).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the antenna is a phased array antenna as taught by Navarro. This modification would provide a phased array antenna for performing beamforming operations (see Navarro, col. 1, lines 41-51).
Regarding claim 7, as best understood, the modified Yun teaches the antenna of claim 6 as addressed above.
The modified Yun does not explicitly teach the antenna is part of a 5G radio.
However, Yun (Fig. 2; [0060], lines 8-15) teaches an antenna (244) which is part of a 5G radio (the antenna 244 is connected to a processor 214 for providing 5G communications – see [0060], lines 8-15).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the antenna is part of a 5G radio. This modification would provide an antenna supporting the desired communication network (see Yun, [0060], lines 8-15).
Regarding claim 12, as best understood, the modified Yun teaches the antenna of claim 1 as addressed above.
Yun (Fig. 12; [0149-0150]) further teaches the plurality of layers include a feed layer (regarding the feed layer, see annotated Fig. 12 in Yun above), said interconnect being positioned in the feed layer (regarding the feed layer and the interconnect being positioned in the feed layer, [0149] discloses: “the plurality of conductive layers 901 and the plurality of via holes 931 and 932 may form a plurality of feeding paths 941 and 942”; a person skilled in the art knows that a PCB structure with a feeding path includes a feed layer, which may comprise a transmission line – for example, a coplanar waveguide transmission line or a microstrip transmission line, connecting the corresponding vias to provide a signal path from the IC circuit 250 to the antenna element 950 (see, [0150]); the interconnect shown in the annotated Fig. 12 in Yun above is a part of the feeding path connecting the vias and, thus, is in the feed layer).
Regarding claim 13, as best understood, the modified Yun teaches the antenna of claim 1 as addressed above.
The modified Yun does not explicitly teach the limitation wherein the portion of the first via hole that is not filled with the first via is filled with a dielectric and the portion of the second via hole that is not filled with the second via is filled with a dielectric.
However, it is well-known in the art that when a via hole is only partially filled with conductive material (via), the portion of the via hole that is not filled with the first via may be filled with a dielectric material in order to preserve the structural integrity of the PCB assembly and to avoid discontinuities in the dielectric substrate of the signal transmission lines which can cause undesired perturbations in the transmission lines impedance (this is especially important at very high frequencies – e.g., mm-wave and higher, wherein discontinuities in the dielectric material can be comparable to the wavelength of the electromagnetic radiation).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the portion of the first via hole that is not filled with the first via is filled with a dielectric and the portion of the second via hole that is not filled with the second via is filled with a dielectric. This modification would provide an antenna having the benefits cited above.
Regarding claim 14, as best understood, the modified Yun teaches the antenna of claim 1 as addressed above.
The modified Yun does not explicitly teach the limitation wherein the first via hole and the second via hole are provided as close together as manufacturing tolerances allow.
However, a person skilled in the art knows that two adjacent via holes can be provided as close together as manufacturing tolerances allow. By providing the via holes and, by default, the vias as close together as possible one can achieve a more compact footprint of the antenna assembly and can minimize transmission losses by the virtue of minimizing the length of the interconnect between the two vias (i.e., the transmission line connecting the vias).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the first via hole and the second via hole are provided as close together as manufacturing tolerances allow. This modification would provide an antenna having the benefits cited above.
Claims 8-9, 11, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yun (cited above) in view of Thurai (cited above), Navarro (cited above), and Alpman (cited above).
Regarding claim 8, as best understood, Yun (Figs. 5, 12; [0143-0150]) discloses an array antenna (240) comprising:
a printed circuit board (PCB) structure including a plurality of layers (regarding the PCB structure including a plurality of layers, see annotated Fig. 12 in Yun above), said PCB structure including a first via hole (regarding the first via hole, see annotated Fig. 12 in Yun above) formed into the plurality of layers through one side of the PCB structure and partially filled with a first via (regarding the first via, see annotated Fig. 12 in Yun above) and a second via hole (regarding the second via hole, see annotated Fig. 12 in Yun above) formed into the plurality of layers through an opposite side of the PCB structure and partially filled with a second via (regarding the second via, see annotated Fig. 12 in Yun above), wherein the first and second vias are electrically coupled by an interconnect provided in a feed layer of the plurality of layers (regarding the interconnect and the feed layer, see annotated Fig. 12 in Yun above; [0149] discloses: “the plurality of conductive layers 901 and the plurality of via holes 931 and 932 may form a plurality of feeding paths 941 and 942”; a person skilled in the art knows that a PCB structure with a feeding path includes a feed layer, which may comprise a transmission line – for example, a coplanar waveguide transmission line or a microstrip transmission line, connecting the corresponding vias to provide a signal path from the IC circuit 250 to the antenna element 950 (see, [0150]); the interconnect shown in the annotated Fig. 12 in Yun above is a part of the feeding path connecting the vias and, thus, is positioned in the feed layer);
buildup layers formed on the one side of the PCB structure and buildup layers formed on the opposite side of the PCB structure (regarding the buildup layers formed on the one side of the PCB structure and the buildup layers formed on the opposite side of the PCB structure, see annotated Fig. 12 in Yun above);
at least one integrated circuit (IC) (250) formed on the prepreg buildup layers on the one side of the PCB structure; and
at least one patch antenna radiating element (950) formed on the prepreg buildup layers on the opposite side of the PCB structure.
Yun does not explicitly disclose partially filled first and second vias, beamforming integrated circuit, and the limitation wherein the buildup layers are only prepreg layers.
Thurai (Fig. 1) teaches a via hole (the via hole associated with via 140) formed into a plurality of layers of a PCB structure and partially filled with a via (140).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the first via hole is partially filled with a first via and the second via hole is partially filled with a second via as taught by Thurai. This modification would provide a first via and a second via which extend to and connect the desired signal traces (see Thurai, [0037]).
The modified Yun does not explicitly teach beamforming integrated circuit and the limitation wherein the buildup layers are only prepreg layers.
Navarro (Fig. 6; col. 9, lines 39-59) teaches a PCB structure (layers 529), buildup layers (527) on one side of the PCB structure, wherein the buildup layers are prepreg layers (see col. 9, lines 39-48), and an integrated circuit (540) disposed on top of the buildup layers. Navarro (Figs. 11A-11B; col. 14, lines 24-57) further teaches that the integrated circuit (540) may comprise at least one beamforming circuit (see col. 14, lines 51-52).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun by substituting the integrated circuit of Yun with the beamforming circuit of Navarro. This modification would provide an antenna which can perform beamforming operations (see Navarro, col. 1, lines 49-51).
The modified Yun does not teach the limitation wherein the buildup layers are only prepreg layers.
Alpman ([1200]) teaches a PCB structure (10005) comprising buildup layers formed on one side of the PCB structure and buildup layers formed on an opposite side of the PCB structure, wherein the buildup layers are only prepreg layers.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun by substituting the buildup layers of Yun with the buildup layers of Alpman, wherein the buildup layers are only prepreg layers. This modification would provide a more compact antenna due to the prepreg layers being very thin (see Alpman, [1200]).
Regarding claim 9, as best understood, the modified Yun teaches the antenna of claim 8 as addressed above.
The modified Yun does not explicitly teach the limitation wherein the prepreg buildup layers on the one side of the PCB structure include microvias electrically coupled to the beam forming IC and the first via and the prepreg buildup layers on the opposite side of the PCB structure include microvias electrically coupled to the at least one antenna radiating element and the second via.
Navarro (col. 17, lines 63-67 and col. 18, lines 1-6) teaches the PCB structure (525) comprises microvias to connect the IC (540) to antenna elements (560).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the prepreg buildup layers on the one side of the PCB structure include microvias electrically coupled to the beam forming IC and the first via and the buildup prepreg layers on the opposite side of the PCB structure include microvias electrically coupled to the at least one antenna radiating element and the second via. This modification would allow for increased electronic circuit packaging density (see Navarro, col. 3, lines 60-67 and col. 4, lines 1-5).
Regarding claim 11, as best understood, the modified Yun teaches the antenna of claim 8 as addressed above.
The modified Yun does not explicitly teach the antenna is part of a 5G radio.
However, Yun (Fig. 2; [0060], lines 8-15) teaches an antenna (244) which is part of a 5G radio (the antenna 244 is connected to a processor 214 for providing 5G communications – see [0060], lines 8-15).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the antenna is part of a 5G radio. This modification would provide an antenna supporting the desired communication network (see Yun, [0060], lines 8-15).
Regarding claim 15, as best understood, the modified Yun teaches the antenna of claim 8 as addressed above.
The modified Yun does not explicitly teach the limitation wherein the portion of the first via hole that is not filled with the first via is filled with a dielectric and the portion of the second via hole that is not filled with the second via is filled with a dielectric.
However, it is well-known in the art that when a via hole is only partially filled with conductive material (via), the portion of the via hole that is not filled with the first via may be filled with a dielectric material in order to preserve the structural integrity of the PCB assembly and to avoid discontinuities in the dielectric substrate of the signal transmission lines which can cause undesired perturbations in the transmission lines impedance (this is especially important at very high frequencies – e.g., mm-wave and higher, wherein discontinuities in the dielectric material can be comparable to the wavelength of the electromagnetic radiation).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the portion of the first via hole that is not filled with the first via is filled with a dielectric and the portion of the second via hole that is not filled with the second via is filled with a dielectric. This modification would provide an antenna having the benefits cited above.
Regarding claim 16, as best understood, the modified Yun teaches the antenna of claim 8 as addressed above.
The modified Yun does not explicitly teach the limitation wherein the first via hole and the second via hole are provided as close together as manufacturing tolerances allow.
However, a person skilled in the art knows that two adjacent via holes can be provided as close together as manufacturing tolerances allow. By providing the via holes and, by default, the vias as close together as possible one can achieve a more compact footprint of the antenna assembly and can minimize transmission losses by the virtue of minimizing the length of the interconnect between the two vias (i.e., the transmission line connecting the vias).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the first via hole and the second via hole are provided as close together as manufacturing tolerances allow. This modification would provide an antenna having the benefits cited above.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over the modified Yun as applied to claim 1 in view of Cheng et al. (US 9276549 B1, hereinafter Cheng).
Regarding claim 3, as best understood, the modified Yun teaches the antenna of claim 1 as addressed above.
The modified Yun does not teach the limitation wherein the first via includes a first stub that extends beyond the interconnect and the second via includes a second stub that extends beyond the interconnect, wherein the first stub and the second stub have lengths for impedance matching between the first via and the second via.
Cheng (Fig. 2) teaches a first via (10) includes a first stub (12) that extends beyond an interconnect (regarding the interconnect, see annotated Fig. 2 in Cheng below) and a second via (20) includes a second stub (21) that extends beyond the interconnect, wherein the first stub and the second stub have lengths for impedance matching between the first via and the second via (regarding the impedance matching, col. 2, lines 50-59 disclose: “All vias of the via system can include a characteristic impedance Zvia, and the via system can include a differential impedance Z0. By adjusting the first length L1 and the second length L2, signal transmission of the signals through the via system can be optimized.”; per Fig. 2, adjusting the length L1 means adjusting the lengths of the first stub and the second stub, Lstub2 and Lstub3, respectively, and, therefore, the lengths of these stubs provide impedance matching between the first via and the second via, which is achieved when the signal transmission is
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optimized).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the first via includes a first stub that extends beyond the interconnect and the second via includes a second stub that extends beyond the interconnect, wherein the first stub and the second stub have lengths for impedance matching between the first via and the second via as taught by Cheng. This modification would provide an antenna having optimized signal transmission of the signals through the via system (see Cheng, col. 2, lines 50-59).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over the modified Yun as applied to claim 8 in view of Cheng (cited above).
Regarding claim 10, as best understood, the modified Yun teaches the antenna of claim 8 as addressed above.
The modified Yun does not teach the limitation wherein the first via includes a first stub that extends beyond the interconnect and the second via includes a second stub that extends beyond the interconnect, wherein the first stub and the second stub have lengths for impedance matching between the first via and the second via.
Cheng (Fig. 2) teaches a first via (10) includes a first stub (12) that extends beyond an interconnect (regarding the interconnect, see annotated Fig. 2 in Cheng above) and a second via (20) includes a second stub (21) that extends beyond the interconnect, wherein the first stub and the second stub have lengths for impedance matching between the first via and the second via (regarding the impedance matching, col. 2, lines 50-59 disclose: “All vias of the via system can include a characteristic impedance Zvia, and the via system can include a differential impedance Z0. By adjusting the first length L1 and the second length L2, signal transmission of the signals through the via system can be optimized.”; per Fig. 2, adjusting the length L1 means adjusting the lengths of the first stub and the second stub, Lstub2 and Lstub3, respectively, and, therefore, the lengths of these stubs provide impedance matching between the first via and the second via, which is achieved when the signal transmission is optimized.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yun so that the first via includes a first stub that extends beyond the interconnect and the second via includes a second stub that extends beyond the interconnect, wherein the first stub and the second stub have lengths for impedance matching between the first via and the second via as taught by Cheng. This modification would provide an antenna having optimized signal transmission of the signals through the via system (see Cheng, col. 2, lines 50-59).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIN STOYTCHEV STOYTCHEV whose telephone number is (571)272-3467. The examiner can normally be reached Mon-Fri, 8:00-17:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dimary Lopez can be reached at 571-270-7893. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARIN STOYTCHEV STOYTCHEV/Examiner, Art Unit 2845
/DIMARY S LOPEZ CRUZ/Supervisory Patent Examiner, Art Unit 2845
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