DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 20-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 8, 2026.
Applicant’s election without traverse of claims 1-17 and 19 in the reply filed on July 8, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (CN 106502474) (English translation attached).
Regarding claim 1, Lu discloses (Figs. 1-7; sections 0033-0083) an array substrate comprising a display region, wherein the display region comprises at least: a plurality of touch electrodes (16) constituting a plurality of touch rows and a plurality of touch columns, and a plurality of pixel units (01, 200) constituting a plurality of pixel rows and a plurality of pixel columns, orthographic projections of the touch units on the array substrate are at least partially overlapped with orthographic projections of the plurality of pixel units on the array substrate, a pixel unit comprises a plurality of sub-pixels (01); a touch lead group (100) is provided between at least one adjacent pixel columns; the touch lead group comprises at least a first lead (100) and a second lead (100) provided side by side (Fig. 7); the first lead is connected with a touch electrode in a touch row, and the second lead is connected with another touch electrode in an adjacent touch row (section 0033).
Regarding claim 2, Lu discloses (Figs. 1-7; sections 0033-0083) at least one touch column comprises N touch electrodes (16) arranged sequentially along a pixel column direction, an orthographic projection of the touch column on the array substrate is at least partially overlapped with orthographic projections of N/2 pixel columns on the array substrate, the first lead (100) located between an i-th pixel column and an (i+1)-th pixel column is connected to touch electrodes (16) in an (2i-1)-th touch row, the second lead (100) located between the i-th pixel column and the (i+1)-th pixel column is connected to touch electrodes (16) in an 2i-th touch row, N is an even number greater than 1, and i is a positive integer greater than or equal to 1 and less than or equal to N/2 (Figs. 1, 5, 7; section 0043)).
Regarding claim 3, Lu discloses (Figs. 1-7; sections 0033-0083) at least one pixel unit comprises a first sub-pixel (01), a second sub-pixel (01) and a third sub-pixel (01) arranged sequentially along a pixel row direction, the sub-pixel comprises a gate line (11), a data line (20), a thin film transistor (sections 0040, 0051) and a pixel electrode, the thin film transistor is respectively connected to the gate line, the data line and the pixel electrode, the touch electrode is reused as a common electrode, and the first lead and the second lead are reused as common electrode lines; the first lead (100) is disposed at a side of the third sub-pixel away from the first sub-pixel, and the second lead is disposed at a side of the first lead away from the first sub-pixel (sections 0072-0081).
Regarding claim 4, Lu discloses (Figs. 1-7; sections 0033-0083) in at least one pixel row, a first connection block (101) is provided on the first lead (100), and the first connection block is connected with one touch electrode (16) through a first via (20) (section 0046).
Regarding claim 5, Lu discloses (Figs. 1-7; sections 0033-0083) in at least one pixel row, the first lead comprises at least a first straight line segment, a second straight line segment, and a bending segment (for example, portion adjacent 01’s where G2 is located) between the first straight line segment and the second straight line segment, a first end of the bending segment is connected to the first straight line segment, a second end of the bending segment is connected to the second straight line segment, a middle part of the bending segment protrudes in a direction away from the second lead, and the first connection block is disposed in a region formed by bending of the bending segment (Figs. 1, 5, 7).
Regarding claim 6, Lu discloses (Figs. 1-7; sections 0033-0083) an orthographic projection of the first connection block (101) on the array substrate is at least partially overlapped with an orthographic projection of the gate line (11, 300) on the array substrate.
Regarding claim 7, Lu discloses (Figs. 1-7; sections 0033-0083) an orthographic projection of the first via (20) on the array substrate is at least partially overlapped with an orthographic projection of the gate line on the array substrate.
Regarding claim 8, Lu discloses (Figs. 1-7; sections 0033-0083) in at least one pixel row, a second connection block (101) is provided on the second lead (100), and the second connection block is connected with another touch electrode (16) through a second via (20) (section 0046).
Regarding claim 9, Lu discloses (Figs. 1-7; sections 0033-0083) in at least one pixel row, the first lead comprises at least a first straight line segment, a second straight line segment, and a bending segment (for example, portion adjacent 01’s where G4 is located) between the first straight line segment and the second straight line segment, a first end of the bending segment is connected to the first straight line segment, a second end of the bending segment is connected to the second straight line segment, a middle part of the bending segment protrudes in a direction away from the second lead, and the second connection block is disposed in a region formed by bending of the bending segment (Figs. 1, 5, 7).
Regarding claim 10, Lu discloses (Figs. 1-7; sections 0033-0083) an orthographic projection of the second connection block (101) on the array substrate is at least partially overlapped with an orthographic projection of the gate line (11, 300) on the array substrate.
Regarding claim 11, Lu discloses (Figs. 1-7; sections 0033-0083) an orthographic projection of the second via (20) on the array substrate is at least partially overlapped with an orthographic projection of the gate line on the array substrate.
Regarding claim 12, Lu discloses (Figs. 1-7; sections 0033-0083) in at least one pixel unit, the touch electrode comprises an electrode part (100) and a connection part (102), the electrode part is disposed within the pixel unit, the connection part is disposed between adjacent pixel units and connected with electrode parts within the adjacent pixel units (Fig. 5).
Regarding claim 13, Lu discloses (Figs. 1-7; sections 0033-0083) in at least one pixel unit, an orthographic projection of the electrode part on the array substrate is not overlapped with an orthographic projection of the gate line (300) on the array substrate, an orthographic projection of the electrode part on the array substrate is not overlapped with an orthographic projection of the first lead line (100) on the array substrate, and an orthographic projection of the electrode part on the array substrate is not overlapped with an orthographic projection of the second lead line (100) on the array substrate.
Regarding claim 14, Lu discloses (Figs. 1-7; sections 0033-0083) in at least one pixel unit, an orthographic projection of the connection part on the array substrate is at least partially overlapped with an orthographic projection of the gate line (300) on the array substrate, an orthographic projection of the connection part on the array substrate is at least partially overlapped with an orthographic projection of the first lead line (100) on the array substrate, and an orthographic projection of the connection part on the array substrate is at least partially overlapped with an orthographic projection of the second lead line (100) on the array substrate.
Regarding claim 15, Lu discloses (Figs. 1-7; sections 0033-0083) in at least one pixel unit, at least one connection part (102) is connected to the first lead through a first via (20), or at least one connection part (102) is connected to the second lead through a second via (20).
Regarding claim 19, Lu discloses (Figs. 1-7; sections 0033-0083) a display apparatus, comprising the array substrate (section 0007).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Lee et al. (US 20200090567).
Regarding claim 16, Lu does not necessarily disclose the array substrate further comprises a bonding region located at a side of the display region and an upper bezel region located at a side of the display region away from the bonding region; the bonding region comprises at least a plurality of pins, the upper bezel region comprises at least a test circuit, the test circuit is correspondingly connected with the plurality of pins of the bonding region through a plurality of connection lines, and the test circuit is configured to detect short circuit defects of the array substrate.
Lee discloses (Figs. 1a-18) the array substrate further comprises a bonding region (114) located at a side of the display region (102) and an upper bezel region (104) located at a side of the display region away from the bonding region; the bonding region comprises at least a plurality of pins (170, 1012), the upper bezel region comprises at least a test circuit (1020), the test circuit is correspondingly connected with the plurality of pins (1012) of the bonding region through a plurality of connection lines, and the test circuit is configured to detect short circuit defects of the array substrate (section 0056). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Lee to test and probe the electronic components of the display device and perform the detection of the touch sensing function and the display function.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: the prior art does not disclose or suggest the array substrate of claim 17, in particular the limitations of the test circuit comprises a plurality of test units corresponding to positions of the plurality of touch columns; at least one test unit comprises a first test line, a second test line, a switch control line, a first switch and a second switch; the first test line is connected with the first lead in the display region through the first switch, the second test line is connected with the second lead in the display region through the second switch, and the switch control line is connected with control terminals of the first switch and the second switch; the first test line is configured to transmit a first gray-scale voltage to the first lead under control of the switch control line, and the second test line is configured to transmit a second gray-scale voltage to the second lead under control of the switch control line; a voltage value of the first gray-scale voltage is greater than a voltage value of the second gray-scale voltage, or the voltage value of the first gray-scale voltage is less than the voltage value of the second gray-scale voltage, wherein the test unit further comprises a first data lead, a second data lead, a third data lead, a third switch, a fourth switch, and a fifth switch, the first data lead is connected with a data line of a first sub-pixel in the display region through the third switch, the second data lead is connected with a data line of a second sub-pixel in the display region through the fourth switch, the third data lead is connected with a data line of a third sub-pixel in the display region through the fifth switch, the switch control line is connected with control terminals of the third switch, the fourth switch and the fifth switch; the first data lead, the second data lead, and the third data lead are configured to transmit a common reference voltage to data lines of the display region under control of the switch control line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES S CHANG whose telephone number is (571)270-5024. The examiner can normally be reached Monday - Friday, 9:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Caley can be reached at (571) 272-2286. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHARLES S CHANG/Primary Examiner, Art Unit 2871
Prosecution Insights