DETAILED ACTION
This non-final office action is responsive to application 18/695,316 as submitted 25 March 2024.
Claim status is preliminary amendment with currently pending claims 1-16 in which amended claims are 6-7, 9, and 11-13; claims 15-16 are newly presented.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The application has an effective filing date of 09/26/21.
Information Disclosure Statement
As required by MPEP 609(c), the applicant’s submissions of the Information Disclosure Statement dated 06/25/24 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by MPEP 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Specification
The specification is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. See MPEP 606.01.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such functional language is replete, a non-exhaustive list of representative claim limitations comprise the following:
Claim 1: A data processing apparatus comprising:
“a controlling module, configured to switch”
“a parameter management module, configured to set”
“an inputting and outputting module, configured to respond”
Claim 3: The data apparatus… wherein
“writing unit, configured to write”
“reading unit, configured to read”
Claim 4: The data processing apparatus… wherein
“a first inputting sub-module…to provide an inputting signal”
“a first outputting sub-module…to receive a computing result”
“a second inputting sub-module…to provide an inputting signal”
“a second outputting sub-module…to receive a computing result”
Claim 5: The data processing apparatus… wherein
“first data buffering unit is configured to receive”
“holding unit is configured to sample”
“accumulation unit is configured to provide”
“second data buffering unit is configured to output”
“third data buffering unit is configured to receive”
“fourth data buffering unit is configured to output”
Claim 10: The data apparatus… further comprising:
“a multiplexing unit selection module, configured to… select”
Claim 11: The data processing apparatus… further comprising:
“a processing element interface module, configured to communicate”
Claim 12: The data processing apparatus… further comprising:
“a functional function unit, configured to provide”
Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The corresponding structure is interpreted in light of the specification. The specification does not make it clear that the modules and units are limited to particular embodiments. Such modules are illustrated by drawing Fig 4 e.g. black-boxes 200, 300, 400 and 500, comprised of nothing, and the specification largely repeats language of claimed modules and units, broadly stating [0039] “these units and modules may be implemented by circuits” the phrase ‘may be’ is not must and examples are given to disparage such implementation such as by software [0044] “For example, the controlling module 200 may be implemented as hardware or firmware such as a CPU, SoC, FPGA, ASIC, or any combination of hardware or firmware and software”
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. Particularly, claims recite functional language of modules and units configured to perform limitations as noted above under claim interpretation which invoke 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The functional modules and units are illustrated e.g. Fig 4 and described [0039,44]. Neither the specification nor the drawings describe sufficient supporting structure for each functional module and unit that clearly links the structure, material, or acts in performance of the entire claimed function. Accordingly, the claims are indefinite and are rejected under 35 U.S.C. 112(b). For purposes of examination, the functions are interpreted as any combination of hardware or firmware and software. The rejection applies to the dependent claims which fail to cure all deficiencies. Thus, claims 1-16 are rejected as being indefinite under 35 USC 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 4-10 and 15-16 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. Particularly, claims recite a “first connection end side” and “second connection end side” which relate sub-modules connected to modules. It is unclear what the ‘end side’ of a module constitutes and how the connection is arranged relative to another module, so as to clearly ascertain the meets and bounds afforded by the claim. The specification’s detailed description references ‘end side’ only at [0050] merely repeating claim language similar to summary, and shows modules Fig 4 as merely block diagram. The functionality may point to alternate aspects such as an array’s row and column operations Fig 1B, or various data paths of Fig 11-13. No definitions are given to guide how the language is to be read. For purposes of examination, the connection end sides are broadly interpreted as any connection. In view of the foregoing, the claims are indefinite and thus claims 4-10 and 15-16 are rejected as indefinite under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4, 6-7, 9 and 11-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. In determining whether the claims are subject matter eligible, the examiner applies guidance set forth under MPEP 2106.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter? Yes—all claims fall within one of the four statutory categories: claims 1, 4, 6-7, 9 and 11-12 are drawn to an apparatus/machine, and claims 13-14 are a method/process for the apparatus. Accordingly, the claims recite statutory subject matter and the analysis should proceed per MPEP 2106.03.
Step 2A, prong one: Does the claim recite an abstract idea, law of nature or natural phenomenon? Yes—the claims, under the broadest reasonable interpretation, recites an abstract idea. In this case, claims fall within the enumerated grouping of abstract idea being “Math Concepts” and/or “Mental Processes”, but for the recitation of generic computer components. In particular, claims recite:
“a bidirectional data processing module, comprising at least computing task comprises an inference computing task and a training computing task” (Math tasks, the BRI of “array” includes “vector” i.e. for vector-matrix multiplication [0036]. No model or AI network required, tasks involve training/learning and inference/estimation)
“a controlling module, configured to switch a working mode of the bidirectional data processing module to an inference working mode to perform the inference computing task, and to switch the working mode of the bidirectional data processing module to a training working mode to perform the training computing task” (Mental process, select a mode as choice of operations. Again, no model or AI network required)
“a parameter management module, configured to set a weight parameter of the bidirectional data processing module” (Mental evaluation e.g. set manually by-hand as in tuning parameters, or by Math update function)
Focus of the claim concern switching modes to perform tasks using an array. Since the array does not require more than computing by math and the training does not require AI, these functions may broadly be performed as array/vector-matrix multiplication and learning or estimations tasks selected manually by choice to set or adjust some coefficient parameter. These functions do not preclude mental performance with math functions. Therefore, the claim recites math concepts and/or mental processes as the abstract idea.
Step 2A, prong two: Does the claim recite additional elements that integrate the judicial exception into a practical application? No—a practical application is not integrated by the judicial exception because the additional elements are as follows:
“A data processing apparatus, comprising:” cont’d “one storage” MPEP 2106.05(f) merely uses a computer as a tool to perform an abstract idea
“an inputting and outputting module, configured to respond to a controlling of the controlling module to generate a computing inputting signal according to inputting data of the computing task, provide the computing inputting signal to the bidirectional data processing module, and receive a computing outputting signal from the bidirectional data processing and generate outputting data according to the computing outputting signal” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, being recited at a high level of generality and/or necessary data inputting and outputting
Balance of the claim concerns apparatus with storage as well as inputting and outputting. These elements provide only generic computing components to process data I/O. The output is not applied to any concrete, real-world use case demonstrating application, much less the practical nature thereof. Accordingly, the claim remains drawn to the abstract idea and the additional elements fail to integrate the judicial exception into a practical application.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception? No—the claims do not include additional elements that amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea in to a practical application, the additional elements are identified with respect to MPEP 2106.05 and do not demonstrate an inventive concept. Particularly, the additional elements are as follows:
“A data processing apparatus, comprising:” cont’d “one storage” MPEP 2106.05(f) merely uses a computer as a tool to perform an abstract idea. Particularly, these elements do not qualify as a particular machine under MPEP 2106.05(b)
“an inputting and outputting module, configured to respond to a controlling of the controlling module to generate a computing inputting signal according to inputting data of the computing task, provide the computing inputting signal to the bidirectional data processing module, and receive a computing outputting signal from the bidirectional data processing and generate outputting data according to the computing outputting signal” MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception, being recited at a high level of generality and/or necessary data inputting and outputting. Particularly, inputting and outputting is a well-understood, routine and conventional activity under MPEP 2106.05(d)(II)(iv) storing and retrieving information in memory, and/or (i) receiving and transmitting data over a network
Significantly more is not satisfied by the additional elements for the reasons noted above. If the claim language provides only a result-oriented solution, with insufficient detail for how a computer accomplishes it, then the claims do contain an inventive concept. Taken alone, their additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. There is no indication that the combination of elements improves the functioning of a computer or improves any other technology. Their collective functions merely provide conventional computer implementation. As such, claim 1 is found ineligible for patent under 35 U.S.C. 101.
Dependent claims 4, 6-7, 9 embellish inputting and outputting with first and second end side connections that connect sub-modules to modules. The end side connections are largely unintelligible as possible translation issue, and may be considered as additional elements falling under MPEP 2106.05(g) adding insignificant extra-solution activity to the judicial exception. The connecting may be simulation for example. Accordingly, the additional elements are insufficient to integrate the judicial exception into a practical application or amount to significantly more.
Dependent claim 11 discloses a processing element interface module, configured to communicate with an external device outside the data processing apparatus. The limitation is considered an additional element which falls under MPEP 2106.05(g) insignificant extra-solution activity to the judicial exception. Particularly, said extra-solution activity is a well-understood, routine and conventional activity under MPEP 2106.05(d)(II)(i) using the internet. Accordingly, the claim remains drawn to the abstract idea and the additional elements are insufficient to integrate the judicial exception into a practical application or amount to significantly more.
Dependent claim 12 discloses a functional function unit to provide non-linear arithmetic operations. This is considered part of the abstract idea being mathematical calculations. There are no additional elements.
Dependent claim 13 discloses obtaining current working mode and controlling by executing the inference and training responsive to working mode being in respective mode. This is considered part of the abstract idea as mental process to observe current state for subsequent carrying out the tasks which may may be implemented by-hand or with aid of pen and paper. There are no additional elements.
Dependent claim 14 discloses wherein bidirectional module performs inference and training modes comprising receiving, performing, and generating limitations. The limitations may be considered additional elements that fall under MPEP 2106.05(g) insignificant extra-solution activities. For example, receiving and storing are well-understood, routine and conventional activities under MPEP 2106.05(d)(II) (i) receiving data over a network and (iv) storing and retrieving information in memory. The generating refers back to the output which may be a necessary output retrieved from the memory. Accordingly, the claims remain directed to the abstract idea and the additional elements are insufficient to integrate the judicial exception into a practical application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by:
Liu et al., “Memristor-based LSTM network with in situ training and its applications” hereinafter Liu (ElSevier Neural Networks; Huazhong Univ. Wuhan, China. August 2020).
With respect to claim 1, Liu teaches:
A data processing apparatus {Liu discloses [P.309 ¶1,3] “memristor devices… In this paper, a memristor-based LSTM network, MbLSTM is presented to execute LSTM functions in hardware”}, comprising:
a bidirectional data processing module, comprising at least one storage and computing integration computing array, configured to perform a computing task, wherein the computing task comprises an inference computing task and a training computing task {Liu [P.306 Sect. 4.4 ¶1] “memristor array can be used to store” and computes LSTM training & inference - [P.305 Sect. 4.1-4.2] “Inference process” & “BPTT training” notes “When the forward pass is over, the backward pass begins” where forward and backward is bidirectional, forward pass is inference and backward pass is training. Similar [P.303 ¶1] “forward pass (inference phase)” and [P.306 ¶4] “in situ training” (in-place/online). Illustratively, see e.g. Figs 2, 4-5, 9-10};
a controlling module, configured to switch a working mode of the bidirectional data processing module to an inference working mode to perform the inference computing task, and to switch the working mode of the bidirectional data processing module to a training working mode to perform the training computing task {Liu [P.303 ¶1] “switch control signal” shown Fig 2 “S and S̄ are signals to switch the operation mode of inference or error backpropagation” teaches mode switching between inference and backpropagation training (abbrv. BPTT is backpropagation through time), again per [P.303 ¶1] “In the training phase, S is low level and S̄ is high level” similar [P.306-7 Sect.4.4 Step 1,5], shown again at Fig 5. The working mode is operation and interpreted to comprise operations for inputs to the switching};
a parameter management module, configured to set a weight parameter of the bidirectional data processing module {Liu see [P.305-6 Sect. 4.3] “∆W is the weight update value” updating is setting, the weight is a parameter, applied as per [P.307 Step6] “Update memristor conductance through the weight update scheme”. Additionally note [P.303 ¶1] “trainable parameters in one LSTM”}; and
an inputting and outputting module, configured to respond to a controlling of the controlling module to generate a computing inputting signal according to inputting data of the computing task, provide the computing inputting signal to the bidirectional data processing module, and receive a computing outputting signal from the bidirectional data processing module and generate outputting data according to the computing outputting signal {Liu [P.304 Sect.4 ¶1] “sequence data is input to MbLSTM, getting output data” the inputs and outputs specified e.g. [P.306-7 Step 2,4] and shown Fig 4 “LSTM can generate vector ct and ht. ht is then rescaled in order to be input to the LSTM units in the next time step” introduced [P.302 Sect. 3.1] “memristor-based LSTM units that generate ft, It, at and ot” Fig 1 emphasis being generative technique for the inputs and outputs over time steps as sequence laid out in Fig 4. Statistically, outputs may be of the form Eqs. 29,31. Additionally see Figs 7 and 10 MbLSTM repeats until convergence with arrows indicating input and output of peripheral circuit}.
With respect to claim 2, Liu teaches the data processing apparatus according to claim 1, wherein
the computing array comprises a memristor array for realizing the storage and computing integration, and the memristor array comprises a plurality of memristors arranged in an array {Liu [P.306 Sect. 4.4 ¶1] “memristor array can be used to store” and compute as shown Figs 2, 4-5 and 9 illustrating crossbar grid of memristors}.
With respect to claim 12, Liu teaches the data processing apparatus according to claim 1, further comprising:
a functional function unit, configured to provide a non-linear arithmetic operation to the outputting data {Liu Fig 1 “sigmoid activation function and the tanh activation function” shown with output gate, sigmoid and tanh (hyperbolic tangent) are non-linear (plotted Fig 3) arithmetic operations of the LSTM implemented Eqs. 7-12. The activation functions are implemented in hardware Fig 2}.
With respect to claim 13, Liu teaches a data processing method, for the data processing apparatus according to claim 1, comprising:
obtaining a current working mode and controlling the bidirectional data processing module by the controlling module {Liu [P.306 ¶2] “memristor’s current state” reflects mode/phase [P.303 ¶1] Fig 2 as controlled according to the switch control signal};
in response to the working mode being the inference working mode, the bidirectional data processing module using an inference weight parameter used to perform the inference computing task to execute the inference computing task {Liu Fig 7 right-bottom, prediction for inference [P.305 Sect. 4.1] repeats over time-steps using LSTM with weights subject to update per [Sect. 4.2-4.3]. Further, execution includes simulation [P.307 Sect. 5-5.1] and performed by the memristor circuit Figs 2, 4 so as to [P.309 Sect.6] “execute LSTM functions in hardware”};
in response to the working mode being the training working mode, the bidirectional data processing module using a training weight parameter used to perform the training computing task to execute the training computing task {Liu Fig 7 right-top training, the training per [P.305 Sect. 4.2-4.3] includes weight update & gradient calculation, execution comprises simulation e.g. [P.307 Sect.5.3] “training uses the SGD (stochastic gradient descent) algorithm” for [P.309 Sect.6] “in situ training”}.
With respect to claim 14, Liu teaches a data processing method, for the data processing apparatus according to claim 13, wherein the bidirectional data processing module performing the inference computing task comprising:
receiving the first inputting data and generating a first computing inputting signal from the first inputting data {Liu Fig 2 input voltages for inference phase of LSTM unit which generates vectors including input gate Eq.8. See [P.302-03 Sect. 3.1], [P.305 Sect. 4.1]};
performing a storage and computing integration operation on the first computing inputting signal, and outputting a first computing outputting signal {Liu Fig 2 symbol in blue denotes memristor, meaning (mem)ory (res)istor, the memory stores, an output is Fig 2 bottom, similar at Fig 5};
generating the first outputting data according to the first computing outputting signal {Liu [P.305 Sect. 4.1] “generate the output” e.g. Fig 2 shown at bottom, similar at [P.303 Last¶] “LSTM units that generate f, i, a, and o” o vector being output, gated Fig 1}; and
the bidirectional data processing module performing the training computing task comprising: {Liu [P.305 Sect. 4.2] BPTT training of LSTM network, again at [P.306-07 Sect. 4.4]}
receiving the second inputting data and generating a second computing inputting signal from the second inputting data {Liu Figs 2 and/or 5 input Vδ(2) shown top, described per [P.303 ¶1] “In the training phase… error backpropagation and then Vδ is the input voltage vector” further detailed [P.305 Sect. 4.2] BPTT training Eqs. 42-43 takes δ as argument for gradient of weight, allows for in-situ training, see e.g. [P.306-07 Sect. 4.4] “Taking one input sample and one training epoch for example, training steps of MbLSTM are as follows” Step 5};
performing a storage and computing integration operation on the second computing inputting signal, and outputting a second computing outputting signal {Liu Figs 2,5 symbol in blue denotes memristor, meaning (mem)ory (res)istor, the memory stores for compute by the circuit, and output is Fig 2 bottom, similar at Fig 5}; and
generating the second outputting data based on the second computing outputting signal {Liu Figs 2 and/or 5 output Ɪδ(2) shown right, described [P.303 ¶1] “In the training phase… Ɪδ is the output current vector” further detailed Eq.30 [P.304 Sect. 3.2], see [P.307 Sect. 5.3] “60,000 training samples…number of training epochs is 20” for the generative LSTM}.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of:
Shi et al., “Design of In-Situ Learning Bidirectional Associative Memory Neural Network Circuit with Memristor Synapse” hereinafter Shi (IEEE, Huazhong Univ. Wuhan, China).
With respect to claim 3, Liu teaches the data processing apparatus according to claim 2, wherein the parameter management module comprises
changing a conductance value of each of the plurality of memristors using the weight parameter {Liu [P.305 Sect. 4.3] “conductance update value is” Eq.45 “where ∆W is the weight update value. The conductance of the memristor is updated by” Eq.46}; and
However, Liu does not expressly characterize this using read and write which is met by Shi:
a weight array writing unit, configured to write the weight parameter to the memristor array; and a weight array reading unit, configured to read the conductance value of each of the plurality of memristors from the memristor array to complete a reading of the weight parameter {Shi Fig 5 “Weight read and write part” caption [P.747] “Memristor’s read and write operations are performed serially in weight read and write part… The reading weight is saved in the sample” e.g. Eq.9, and [P.745] “the relationship between the synaptic weight and memristor conductance is” Eq.8, thus [P.749 ¶1] “mapping memristor’s conductance to synaptic weight” further see Fig 8 “in learning process, two read and write operation round is applied to memristor crossbar to modify their weight”}.
Shi is directed to bidirectional memory neural network with memristor array thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to weight write and read per Shi in combination with Liu’s conductance update for memristors to arrive at the invention as claimed as applying known techniques to known devices ready for improvement to yield predictable results and/or a motivation [P.743 Last2¶] “Due to the less information transfer with external circuits, the energy consumption of hardware communication is effectively reduced” and further [P.746 ¶2] “weight read and write circuit applies voltages with different amplitudes to memristor to adjust is resistance” such that [P.749 ¶1] “In the first writing phase, only memristors with positive adjustment value are allowed to participate in weight adjustment. In next 25us, network will repeat read and write process, but only memristors with negative adjustment value are allowed to change” similar at [P.747 ¶3].
Claims 4, 6-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of:
Rasch et al., US PG Pub No 2023/0097217A1 hereinafter Rasch (IBM).
With respect to claim 4, Liu teaches the data processing apparatus according to claim 1, wherein the inputting and outputting module comprises:
a first inputting sub-module, connected to a first connection end side of the bidirectional data processing module to provide an inputting signal of the first inputting data of the inference computing task {Liu Fig 2 input voltage signal Vxt(1) shown left for inference process, described per [P.305 Sect. 4.1] inference process inputs voltages fed to LSTM units to vector representation, again at [P.306 Step2] and [P.307 Sect. 5.1]. The submodule may regard individual LSTM units e.g. as shown Figs 2, 4, 7 and with connections per schematic, and the first end side may regard row for source of input voltage};
a first outputting sub-module, connected to a second connection end side of the bidirectional data processing module to receive a computing result of the inference computing task and generate a first outputting data {Liu Fig 2 output at bottom denoted zt(1) for inference, inference is prediction with a result being Fig 7 “prediction result” obtained from Fig 6 Module_1 Vout output voltage from y(1) which is in-turn Fig 5 bottom yt(1) output. The notation (1) & superscript t for time denotes first in time-series operations. The submodule may regard individual LSTM units e.g. as shown Figs 2, 4, 7 and with connections per schematic, and the second end side may comprise column. See [P.305 Sect. 4.1] Inference process “LSTM… generate the output”};
a second inputting sub-module, connected to the second connection end side of the bidirectional data processing module to provide an inputting signal based on the second inputting data of the training computing task {Liu Figs 2 and/or 5 input Vδ(2) shown top, described per [P.303 ¶1] “In the training phase… error backpropagation and then Vδ is the input voltage vector” further detailed [P.305 Sect. 4.2] BPTT training Eqs. 42-43 takes δ as argument for gradient of weight, allows for in-situ training, see e.g. [P.306-07 Sect. 4.4] “Taking one input sample and one training epoch for example, training steps of MbLSTM are as follows” Step 5 is BPTT. The connection is per schematic and second end side may regard column as already noted}; and
a second outputting sub-module, connected to the first connection end side of the bidirectional data processing module to receive a computing result of the training computing task and generate a second outputting data {Liu Figs 2 and/or 5 output Ɪδ(2) shown right, described [P.303 ¶1] “In the training phase… Ɪδ is the output current vector” further detailed Eq.30 [P.304 Sect. 3.2] for the generative LSTM Fig 4, see [P.307 Sect. 5.3] “60,000 training samples…number of training epochs is 20” plotted Figs 12-16}.
However, it is not prima facie apparent that the end side connection of submodules to modules are connected as arranged which is taught or suggested by Rasch.
Rasch illustrates Fig 4:425,435 I/O modules with arrows indicating bidirectional data movement, similar at Fig 5 and discloses “selectively connect” [0043] for [0039] inference and training to perform matrix vector multiplication. Rasch uses the term RPU as memristor [0034].
Rasch is directed to RPU/memristor arrays for training and inference with forward and backward processes thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to selectively connect among modules for input and output per Rasch in combination to arrive at the invention as claimed as obvious to try in choosing from a finite number of identified, predictable solutions for connecting modules with a reasonable expectation of success and/or a motivation to “enable off-chip I/O communication” [0030] such that “throughput is enhanced by using the input/output” [0049] and more generally “personalize the electronic circuitry” [0083].
With respect to claim 6, the rejection of claim 4 is applied with equal motivation for the limitation being substantively commensurate with the teachings applied to claim 4.
With respect to claim 7, Liu teaches the data processing apparatus according to claim 1, wherein the inputting and outputting module comprises:
a first inputting and outputting sub-module, connected to a first connection end side of the bidirectional data processing module to provide a first inputting signal based on a first inputting data of the inference computing task, and connected to the first connection end side of the bidirectional data processing module to receive a computing result of the training computing task and generate a second outputting data {Liu Fig 2 input-left voltage signal Vxt(1) and output-bottom denoted zt(1) for inference process, described [P.305 Sect. 4.1] inference process inputs voltages fed to LSTM units to vector representation, again at [P.306 Step2] and [P.307 Sect. 5.1]. Further, Fig 7 “prediction result” obtained from Fig 6 Module_1 Vout output voltage from y(1) which is in-turn Fig 5 bottom yt(1) output. The notation (1) & superscript t for time denotes first in time-series operations. The submodule may regard individual LSTM units e.g. as shown Figs 2, 4, 7 and with connections per schematic, and the first end side may regard row for source of input voltage. [P.305 Sect. 4.1] “LSTM… generate the output”};
a second inputting and outputting sub-module, connected to a second connection end side of the bidirectional data processing module to provide an inputting signal based on the second inputting data of the training computing task, and connected to the second connection end side of the bidirectional data processing module to receive a computing result of the inference computing task and generate the first outputting data {Liu Figs 2, 5 input Vδ(2) shown top, right shows output Ɪδ(2) described [P.303 ¶1] “In the training phase… Ɪδ is the output current vector” detailed Eq.30 and per [P.303 ¶1] “In the training phase… error backpropagation and then Vδ is the input voltage vector” further detailed [P.305 Sect. 4.2] BPTT training Eqs. 42-43 takes δ as argument for gradient of weight, allows for in-situ training, see e.g. [P.306-07 Sect. 4.4] “Taking one input sample and one training epoch for example, training steps of MbLSTM are as follows” Step 5 is BPTT. The connection is per schematic and second end side may regard column. See [P.307 Sect. 5.3] “60,000 training samples…number of training epochs is 20” plotted Figs 12-16}.
However, it is not prima facie apparent that the end side connection of submodules to modules are connected as arranged which is taught or suggested by Rasch.
Rasch illustrates Fig 4:425,435 I/O modules with arrows indicating bidirectional data movement, similar at Fig 5 and discloses “selectively connect” [0043] for [0039] inference and training to perform matrix vector multiplication. Rasch uses the term RPU as memristor [0034].
Rasch is directed to RPU/memristor arrays for training and inference with forward and backward processes thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to selectively connect among modules for input and output per Rasch in combination to arrive at the invention as claimed as obvious to try in choosing from a finite number of identified, predictable solutions for connecting modules with a reasonable expectation of success and/or a motivation to “enable off-chip I/O communication” [0030] such that “throughput is enhanced by using the input/output” [0049] and more generally “personalize the electronic circuitry” [0083].
With respect to claim 9, the rejection of claim 7 is applied with equal motivation for the limitation being substantively commensurate with the teachings applied to claim 7.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of:
Gupta et al., US PG Pub No 2019/0205741A1 hereinafter Gupta.
With respect to claim 11, Liu teaches the data processing apparatus according to claim 1, further comprising: {Liu Fig 10 peripheral circuit, arrows back and forth such that some interface is requisite} Gupta teaches
a processing element interface module, configured to communicate with an external device outside the data processing apparatus {Gupta Fig 6 PCIe interface with PCIe Bus, described [0072-75] “connect peripherals in computing and communications platforms. A PCIe ‘lane’ comprises two simplex interconnect links between two PCI devices, each in opposite directions… bidirectional” devices shown e.g. Figs 1-3, and introduced [0027] “interface with a Peripheral Component Interconnect Express (PCIe) host processor”}.
Gupta is directed to bidirectional data processing with array of memristors for inference and training of neural networks as well as switching hardware thus being analogous. A person having ordinary skill in the art would have considered it obvious prior to the effective filing date to use PCIe interface per Gupta for Liu’s peripheral circuit in combination for as obvious to try in choosing from a finite number of identified, predictable solutions for interfacing through routine experimentation, with a reasonable expectation of success and/or a motivation [0072] “The PCIe standard offers the flexibility of increasing throughput.”
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nugent, Alex “Memristor Crossbars as Easy as Raspberry Pi, Part 1” KnowM discloses memristor breakout board: knowm.org/memristor-crossbars-as-easy-as-raspberry-pi/ published 02 Sept 2020
Qin et al., “Recent Progress on Memristive Convolutional Neural Networks for Edge Intelligence” Wuhan, see Fig 6b
Yao et al., “Fully hardware-implemented memristor convolutional neural network” Fig 1,3
Wen et al., “Memristive LSTM Network for Sentiment Analysis” Figs 1,6 hardware
Boybat Kara et al., US PG Pub No 2020/0118001A1 IBM see Fig 2
Sebastian et al., “Memory devices and applications for in-memory computing” see Fig 6
Amirsoleimani et al., “CODEX: Stochastic Encoding Method to Relax Resistive Crossbar Accelerator Design Requirements” Univ. Toronto, see Fig 2 training/inference
Luo et al., “FullReuse: A Novel ReRAM-based CNN Accelerator Reusing Data in Multiple Levels” Fig 4 shows Subarrays in hierarchical arrangement of tiled PE array
Conclusion
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