DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 16-21 and 23-30 are pending for examination. Claims 16 and 30 are independent claims. This Office Action is FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 26 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 26, line 6 “the difference” is indefinite and unclear if refers to “a difference” claim 26, line 4 or claim 25, line 7? Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 16-21 and 23-30 are rejected under 35 U.S.C. 101 because the claimed invention is directed to (an) abstract idea(s) without significantly more.
Claims 16 and 30 recite:
sequence monitoring of multiple threads being executed at least partly in parallel on an electronic control unit of an automated vehicle
in an AUTOSAR® adaptive platform or a Linux® platform,
providing, to a first monitoring thread of the multiple threads, a first timestamp generated at a first predefined time during execution of a first thread to be monitored;
providing, to the first monitoring thread, a second timestamp generated at a second predefined time during execution of a second thread to be monitored; and
checking, by the first monitoring thread, whether the first timestamp is provided before the second timestamp;
wherein the first thread to be monitored and the second thread to be monitored are executed at least partly in parallel.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes:
Claim 16 is a process.
Claim 30 is a machine.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘sequence monitoring’ limitation in #1 above, ‘providing to a first monitoring thread’ in limitations #3 and #4, ‘checking’ limitation in #5 and ‘wherein’ clause limitation in #6 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. For example, ‘sequence monitoring’ and ‘checking’ in the context of this claim encompasses a person making a judgement about timestamp data and ‘providing to a first monitoring thread’ is thought process of person using pen and paper to receive timestamps.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘monitoring’ limitation in # 1, ‘providing’ limitation in #3 and #4 above, as claimed and under BRI, are additional elements that are insignificant extra-solution activity. For example, “monitoring” and “providing” in the context of this claim encompasses mere data gathering. As mentioned above, the ‘providing’ limitation in #3 and #4 recites “to a first monitoring thread” and under BRI is equivalent to a human being’s mental process using pen and paper to receive the timestamps-these are data gathering and analyzing. Furthermore, the ‘sequence monitoring’ limitation in #1 above recites “multiple threads being executed at least partly in parallel” and ‘wherein’ clause limitation in #6 above recites “first thread to be monitored and the second thread…are executed at least partly in parallel” that as claimed and under BRI are parallel data messages that include the time or parallel pieces of paper that have the time written on them and are given to a person and, thus, are insignificant extra-solution activity. See MPEP 2106.05(g).
The ‘in an AUTOSAR® adaptive…or a Linux® platform’ limitation in # 2 above, as claimed and under BRI, is an additional element that is mere instructions to apply an exception. For example, “in an … platform’ in the context of this claim encompasses use of the abstract idea (the claimed ‘sequence monitoring’) in a generic computer system platform. See MPEP 2106.05(f).
Additionally, one or more of the claims recite the following additional elements:
an electronic control unit (Claims 16, 30)
an automated vehicle (Claim 16)
core(s) (Claim 21)
a shared memory (Claim 28)
a hardware counter (Claim 29)
a processor (Claim 30)
a memory (Claim 30)
These additional elements are recited at a high level of generality (i.e. as generic computer components or systems) such that they amount to no more than components comprising mere instructions to apply the exception. Accordingly, these additional elements do not integrate the abstract idea(s) into a practical application because they do not impose any meaningful limits on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components comprising mere instructions to apply the exception. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Additionally, with regards to # 1 and # 3-4 above, per MPEP 2106.05(d)(Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network).
Claim 17 limitations ‘providing, to a second monitoring thread’ the first timestamp and the second timestamp and ‘checking’ are very similar to claim limitations of Claim 16 and are patent ineligible under similar reasoning.
Claim 18 merely further describes the claimed ‘multiple threads’ of Claim 16.
Claim 19 merely further describes the claimed ‘timestamp’ of Claim 16.
Claim 20 recites:
raising an error flag by use of the first and/or the second monitoring thread in case a result of the checking by the first monitoring thread or the second monitoring thread is that the first timestamp is not provided before the second timestamp.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: a process.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘raising’ limitation in # 5 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. For example, “raising” in the context of this claim encompasses the person making an observation about data.
Claim 21 merely further describes the claimed multiple threads of Claim 16.
Claim 23 merely further describes the claimed first and second thread of Claim 16.
Claim 24 limitations ‘providing … to the first monitoring thread’ and ‘providing … to the second monitoring thread’ the first timestamp and the second timestamp are very similar to claim limitations of Claim 16 and are patent ineligible under similar reasoning.
Claim 25 limitations ‘providing … to the first monitoring thread’ the start timestamp and the end timestamp and ‘computing’ and ‘comparing’ are very similar to claim limitations of Claim 16 and are patent ineligible under similar reasoning.
Claim 26 limitations ‘providing … to the second monitoring thread’ the start timestamp and the end timestamp and ‘computing’ and ‘comparing’ are very similar to claim limitations of Claim 16 and are patent ineligible under similar reasoning.
Claim 27 limitation ‘raising an error flag’ is very similar to claim limitations of Claim 20 and are patent ineligible under similar reasoning.
Claim 28 limitations ‘providing’, ‘saving’, and ‘reading’ are very similar to claim limitations of Claim 16 and are patent ineligible under similar reasoning.
Claim 29 merely further describes the claimed electronic control unit, first timestamp, second timestamp, start timestamp and end timestamp of Claims 16 and 25.
For at least the reasoning provided above, Claims 16-21 and 23-30 are patent ineligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-21 and 23-30 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al., (U.S. Patent Publn. No. 2017/0088164 A1), hereinafter Kobayashi in view of Lee et al., (U.S. Patent Publn. No. 2010/0077258 A1), hereinafter Lee.
Regarding claim 16, Kobayashi teaches:
A method for sequence monitoring of multiple threads being executed at least partly in parallel on an electronic control unit of an automated vehicle (Kobayashi, Abstract, “perform monitoring of an execution sequence of a task executed by a control program of the on-vehicle electronic equipment …”. Fig. 2 shows ECU 30. Paragraph 0010 teaches “electronic equipment controlled by the control apparatus of on-vehicle electronic equipment and are capable of continuously performing the control of the on-vehicle electronic equipment” (i.e. automated vehicle). Fig. 8 and 9 Processing 1 to N paragraph 0064 teaches each processing corresponds to a particular thread. Processing of next period with another group of threads that has different stop times is shown in right portion of figure. See paragraphs 0062-0066 for a description of Fig. 8 and paragraphs 0067-0073 for a description of Fig. 9. Paragraph 0063 teaches that the threads in processing of next period are in sequence after previous period.), the method comprising:
providing, to a first monitoring thread of the multiple threads (Kobayashi, Abstract, “an execution sequence monitoring comparison circuit …perform monitoring of an execution sequence of a task executed by a control program of the on-vehicle electronic equipment …”. Paragraph 0048 teaches “the processes mean a plurality of control procedures that configure the control program…” [i.e. first monitoring thread]. Multiple threads are Processing 1 to Processing N shown in Figs. 8 and 9 and the processing of next period Processing 1 to Processing 3.), a first timestamp generated at a first predefined time during execution of a first thread to be monitored (Kobayashi, Figs. 8-9 teaches that a first thread may be any one of Processing 1 (i.e. first thread) to Processing N. Paragraph 0054 and Fig. 7, block S2 “Number Processing of Setting Register and Storing in Log Register” selects one of Processing 1 to Processing N. Paragraph 0065 and Fig. 8 shows a Stop time measurement for each Processing 1 to Processing N so for Processing 1 first thread, the first timestamp generated at a first predefined time is the time of the Stop. Paragraph 0065 “each processing is terminated before an elapsed time for the above each processing (the rising solid line from the bottom left to the top right in FIG. 8), that is, the execution time reaches the execution time threshold preliminarily set for each processing (the chain line of a horizontal direction shown in FIG. 8), the monitoring of the execution time by the execution time monitoring timer circuit 111 is stopped.”);
providing, to the first monitoring thread, a second timestamp generated at a second predefined time during execution of a second thread to be monitored (Kobayashi, Fig. 8, Processing 2 in the leftmost period (i.e. second thread). For Processing 2, as shown in Figs. 5 and 8, completion occurs after sequence flow of Processing 1 and Stop time is a second timestamp generated at a second predefined time); and
checking, by the first monitoring thread, whether the first timestamp is provided before the second timestamp (Kobayashi, Figs. 4-8, paragraph 0046 “execution sequence monitoring comparison circuit 113 is a circuit that monitors whether a task (a processing) executed by the control program in the CPU 130 is performed in order or not, and is a circuit that monitors whether or not the processing is executed under a predetermined process”. Fig. 5, paragraph 0048 teaches “respective head addresses of a plurality of processings (for example, from a processing 1 to a processing n, where n=10) as processing address… of the above each processing (from a processing 1 to a processing n, where n=10) are set.” Fig. 7, paragraphs 0053-0061 teaches “Monitoring execution sequence” and Fig. 8, paragraph 0063 shows “a horizontal axis shows the flow of a plurality of processings, FIG. 8 also shows a case of further shifting to the same processing in the next period in the case of setting the number of a plurality of processings of one process to “N”.” ).
Kobayashi does not distinctly disclose an AUTOSAR® adaptive platform or a Linux® platform and wherein the first thread to be monitored and the second thread to be monitored are executed at least partly in parallel.
Lee, in the same field of endeavor, teaches an AUTOSAR® adaptive platform or a Linux® platform (Lee, paragraph 0020 teaches “stored in RAM 168 is operating system 154. Operating systems, useful in CEC complexes susceptible to running operations and responding to hung operations according to embodiments of the present invention, include LinuxTM …and others as will occur to those of skill in the art.”) and wherein the first thread to be monitored and the second thread to be monitored are executed at least partly in parallel (Lee, Fig. 2A and Fig. 3A paragraph 0039 “Next, the service processor may determine if multiple operation threads are running (step 303). The service processor may do this step by counting the number of entries in the list of threads, for example, list of threads 240 of FIG. 2A.”).
.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kobayashi to incorporate the teachings of Lee and provide for an AUTOSAR® adaptive platform or a Linux® platform and wherein the first thread to be monitored and the second thread to be monitored are executed at least partly in parallel because such multithreaded operating system platforms are needed and useful in Central Electronics Complex servers that run thread operations at the same time and respond to hung operations and other thread timing issues that are present in such multithreaded systems (Lee, see paragraph 0020).
Regarding dependent claim 17, Kobayashi teaches further comprising:
providing, to a second monitoring thread of the multiple threads (Kobayashi, paragraph 0048 teaches “ the processes mean a plurality of control procedures that configure the control program, for example, include…process… and so on. Basically, each process periodically executes a plurality of processings [Fig. 5-6], and the number of the plurality of processings is different for every process.” Fig. 4 Execution Time Monitoring Timer Circuit 111 is another process or a different process and is second monitoring thread that executes a second plurality of processings.), the first timestamp generated at the first predefined time during the execution of the first thread to be monitored (Kobayashi, Figs. 8-9 teaches that a first thread may be any one of Processing 1 to Processing N. Paragraph 0054 and Fig. 7, block S2 “Number Processing of Setting Register and Storing in Log Register” selects one of Processing 1 to Processing N. Paragraph 0065 and Fig. 8 shows a Stop time measurement for each Processing 1 to Processing N so for Processing 1 first thread, the first timestamp generated at the first predefined time is the time of the Stop. Paragraph 0065 “each processing is terminated before an elapsed time for the above each processing (the rising solid line from the bottom left to the top right in FIG. 8), that is, the execution time reaches the execution time threshold preliminarily set for each processing (the chain line of a horizontal direction shown in FIG. 8), the monitoring of the execution time by the execution time monitoring timer circuit 111 is stopped.”);
providing, to the second monitoring thread, the second timestamp generated at the second predefined time during the execution of the second thread to be monitored (Kobayashi, Fig. 8, Processing 2 in the leftmost period or Processing 1 in “Processing of Next Period” (i.e. second thread). For Processing 2, as shown in Figs. 5 and 8, completion occurs after sequence flow of Processing 1 (even though started at same time paragraph 0064) and Stop time is a second timestamp generated at a second predefined time); and
checking, by the second monitoring thread, if the first timestamp is provided before the second timestamp (Kobayashi, Figs. 4-8, paragraph 0046 second monitoring thread is process as described in mapping above “a circuit that monitors whether a task (a processing) executed by the control program in the CPU 130 is performed in order or not, and is a circuit that monitors whether or not the processing is executed under a predetermined process”. Fig. 5, paragraph 0048 teaches “respective head addresses of a plurality of processings (for example, from a processing 1 to a processing n, where n=10) as processing address… of the above each processing (from a processing 1 to a processing n, where n=10) are set.” Fig. 7, paragraphs 0053-0061 teaches “Monitoring execution sequence” and Fig. 8 shows “a horizontal axis shows the flow of a plurality of processings, FIG. 8 also shows a case of further shifting to the same processing in the next period in the case of setting the number of a plurality of processings of one process to “N”.”).
Regarding dependent claim 18, Kobayashi teaches wherein the multiple threads are executed with a non-deterministic schedule (Kobayashi, Figs. 7 and 9 teaches alternative processing because of time abnormality in previous period takes next period execution order out of sequence (i.e. non-deterministic schedule). Paragraph 0057 “On the other hand, in the case of judging that there is an abnormality in the sequence of processing, shift to the next Step S6 that performs the generation of the HW alarm and the alternative processing and so on.”).
Regarding dependent claim 19, Kobayashi teaches wherein the first timestamp and the second timestamp are part of or build a first sequence to be monitored out of multiple sequences to be monitored (Kobayashi, Fig. 8 and 9 and description in the specification shows a sequence Processing 1 to Processing N for a period (i.e. first sequence to be monitored) and continue “Processing of Next Period” (i.e. multiple sequences to be monitored)).
Regarding dependent claim 20, Kobayashi teaches further comprising:
raising an error flag by use of the first and/or the second monitoring thread in case a result of the checking by the first monitoring thread or the second monitoring thread is that the first timestamp is not provided before the second timestamp (Kobayashi, Fig. 4, paragraph 0046 “execution sequence monitoring comparison circuit 113 is a circuit that monitors whether a task (a processing) executed by the control program in the CPU 130 is performed in order or not, and is a circuit that monitors whether or not the processing is executed under a predetermined process” [i.e. checking by the first or the second monitoring thread]. Fig. 7, paragraphs 0053-0061 teaches “Monitoring execution sequence” and paragraph 0057 “On the other hand, in the case of judging that there is an abnormality in the sequence of processing, shift to the next Step S6 that performs the generation of the HW alarm and the alternative processing and so on.” Fig. 7, paragraph 0056 teaches “In the next Step S4, information about that processing detected last time is what number execution sequence is fetched from the log information of the log register, and in the subsequent Step S5, it is judged whether or not execution sequence of processing detected this time corresponds to next execution sequence of processing detected last time.” Paragraph 0059 teaches “As described above, in the execution sequence monitoring comparison circuit 113 within the program execution monitoring dedicated circuit 110 of the present embodiment, although the monitoring of execution sequence of the above control program is performed based on respective head addresses (processing addresses) of a plurality of processings (the processing 1 to the processing n), for example, in the program execution monitoring of the present embodiment, it is also possible to employ a configuration and a method that read execution sequence of each process from the program counter [i.e. time stamp] of the CPU 130, compare with the processing address preliminarily registered in the setting register within the program execution monitoring dedicated circuit 110, and monitor the validity of selection of process itself and so on.” [i.e. the first time stamp is not provided before the second timestamp]. Paragraph 0050 teaches “other attached circuit 117 is provided with a hardware (HW) timer, a timer counter, a comparison register etc., and is further provided with a generating circuit of the interruption processing and the HW alarm, a log register for storing the execution sequence and the execution time read from the CPU 130…”. Paragraph 0058 teaches “As the above alternative processing, for example, it is possible to perform interruption with respect to the CPU 130 …” (i.e. interrupt is an error flag)).
Regarding dependent claim 21, Kobayashi teaches wherein the multiple threads are executed on a same core or on different cores of the electronic control unit (Kobayashi, paragraphs 0043-0046, Fig. 3 is schematic configuration of a micro control unit (MCU) that shows CPU 130 that is single core or multi-core).
Regarding dependent claim 23, Kobayashi teaches wherein the first and the second monitoring thread are not executed completely in parallel (Kobayashi, Fig. 8 and 9 Processing 1 to N for Fig. 8 Execution Sequence Monitoring Comparison Circuit 113 (first monitoring thread) and Execution Time Monitoring Timer Circuit 111 (e.g. second monitoring thread) interrupt error flag for out of sequence or exceeding Execution Time Threshold shown in Fig. 9 causes the threads to not execute completely in parallel. See paragraphs 0062-0066 for a description of Fig. 8 and paragraphs 0067-0073 for a description of Fig. 9.).
Regarding dependent claim 24, Kobayashi teaches wherein:
the multiple threads are executed cyclically (Kobayashi, Fig. 8 and Fig. 9 shows Processing 1 to Processing N for a First Period and then for “Processing of Next Period” with flow of plurality of processing along the horizontal axis (i.e. executed cyclically)), and the method further comprises:
providing the first and the second timestamp of a previous cycle to the first monitoring thread (Kobayashi, Figs. 8-9 if “Processing of Next Period” is current thread and previous Processing 1-N is previous cycle thread. Processing 1 stop time measurement (i.e. first timestamp) Processing 2 stop time measurement (i.e. second timestamp)); and
providing the first and the second timestamp of a current cycle to the second monitoring thread (Kobayashi, Figs. 8-9 if “Processing of Next Period” is current cycle thread and previous Processing 1-N is previous cycle thread. Processing 1 stop time measurement (i.e. first timestamp) Processing 2 stop time measurement (i.e. second timestamp) from “Processing of Next Period”. Second monitoring thread: Paragraph 0048 teaches “the processes mean a plurality of control procedures that configure the control program, for example, include…process… and so on. Basically, each process periodically executes a plurality of processings [Fig. 5-6], and the number of the plurality of processings is different for every process.” So another process (e.g. Execution Time Monitoring Timer Circuit 111) is second monitoring thread that executes a second plurality of processings.).
Regarding dependent claim 25, Kobayashi teaches wherein the method further comprises:
providing, to the first monitoring thread, a start timestamp corresponding to a starting time of the first thread to be monitored (Kobayashi, Figs. 5-9 and particularly Fig. 8 “Start” time for each of Processing 1 to Processing N, paragraph 0064 “the execution time monitoring timer circuit 111, when each processing n is started, at the same, the monitoring of the execution time by the execution time monitoring timer circuit 111 starts.” So start timestamp and stop timestamp are monitored for each thread.);
providing, to the first monitoring thread, an end timestamp corresponding to an end time of the first thread to be monitored (Kobayashi, Figs. 5-9 and particularly Fig. 8 “Start” time for each of Processing 1 to Processing N, paragraph 0064 “the execution time monitoring timer circuit 111, when each processing n is started, at the same, the monitoring of the execution time by the execution time monitoring timer circuit 111 starts.” So start timestamp and stop timestamp are monitored for each thread.);
computing, by use of the first monitoring thread, a difference between the start timestamp and the end timestamp (Kobayashi, paragraph 0064, Fig. 8 “execution time monitoring timer circuit 111, when each processing n is started… the monitoring of the execution time by the execution time monitoring timer circuit 111 starts. In addition, here, the above monitoring of execution time is performed by means of a timer within the program execution monitoring dedicated circuit.” Paragraph 0097 “processing N, it is possible to implement a scheme so as to stop … a timer counter of the execution time … or, it is also possible to enable stopping the timer counter”); and
comparing, by use of the first monitoring thread, the difference to a predefined threshold for monitoring a time schedule of the first thread to be monitored (Kobayashi, , Fig. 8 “Execution Time Threshold”, paragraph 0062, “the execution time of the processing does not exceed the predetermined execution time threshold”. Paragraph 0047 “ Further, the execution time monitoring timer circuit 111 is a circuit that monitors whether each processing is executed after the elapse of a time more than or equal to a certain threshold predetermined for every processing or not.” Fig. 5 and 6 shows that the threshold is predefined).
Regarding dependent claim 26, Kobayashi teaches further comprising:
providing, to the second monitoring thread (Kobayashi, paragraph 0048 teaches “ the processes mean a plurality of control procedures that configure the control program, for example, include…process… and so on. Basically, each process periodically executes a plurality of processings [Fig. 5-6], and the number of the plurality of processings is different for every process.” So another process is second monitoring thread that executes a second plurality of processings.), the start timestamp and the end timestamp (Kobayashi, second monitoring thread process needs same information (paragraph 0039-0042 e.g. speed of vehicle, steering torque, steering angle) of Processing 1 to Processing N of steering system shown in Fig. 1);
computing, by use of the second monitoring thread, a difference between the start timestamp and the end timestamp (Kobayashi, paragraph 0064, Fig. 8 “execution time monitoring timer circuit 111, when each processing n is started… the monitoring of the execution time by the execution time monitoring timer circuit 111 starts. In addition, here, the above monitoring of execution time is performed by means of a timer within the program execution monitoring dedicated circuit.” Paragraph 0097 “processing N, it is possible to implement a scheme so as to stop … a timer counter of the execution time … or, it is also possible to enable stopping the timer counter”); and
comparing, by use of the second monitoring thread, the difference to the predefined threshold for monitoring the time schedule of the first thread to be monitored (Kobayashi, , Fig. 8 “Execution Time Threshold”, paragraph 0062, “the execution time of the processing does not exceed the predetermined execution time threshold”. Paragraph 0047 “ Further, the execution time monitoring timer circuit 111 is a circuit that monitors whether each processing is executed after the elapse of a time more than or equal to a certain threshold predetermined for every processing or not.” Fig. 5 and 6 shows that the threshold is predefined).
Regarding dependent claim 27, Kobayashi teaches further comprising:
raising an error flag by use of the first and/or the second monitoring thread in case a result of the comparison is that the difference is beyond, above and/or outside a predefined range around the predefined threshold (Kobayashi, Fig. 4, paragraph 0050 “other attached circuit 117 is provided with a hardware (HW) timer, a timer counter, a comparison register etc., and is further provided with a generating circuit of the interruption processing and the HW alarm, a log register for storing the execution sequence and the execution time read from the CPU 130, the presence or absence of alternative processing execution etc.” Fig. 9, paragraphs 0070-0071 “as shown in the processing 2 of FIG. 9, in the case that the execution time of the processing reaches a preliminarily set execution time threshold, an interruption is informed to the CPU 130 [i.e. error flag] by means of the program execution monitoring dedicated circuit as the occurrence of the abnormality in the execution time and then an interruption processing is performed.”).
Regarding dependent claim 28, Kobayashi teaches wherein
the electronic control unit comprises a shared memory being accessible by each one of the multiple threads (Kobayashi, Fig. 4 ,Setting Register 115, Fig. 5, paragraph 0048 “Further, the setting register 115 is a register that preliminarily records setting information used in the operation of the program execution monitoring dedicated circuit 110. For example, FIG. 5 is a setting example of the setting register 115 of the program execution monitoring dedicated circuit 110 within the MCU 31 with respect to a certain process. In FIG. 5, respective head addresses of a plurality of processings (for example, from a processing 1 to a processing n, where n=10) as processing address and execution time thresholds of the above each processing (from a processing 1 to a processing n, where n=10) are set.”), and the method further comprises:
providing the first, the second, the end and/or the start timestamp to the first and/or the second monitoring thread (Kobayashi, Figs. 8-9 control program processes such as execution sequence monitoring comparison circuit 113 and execution time monitoring timer circuit 111 measure and track Start and Stop timestamps for each Processing);
saving the first, the second, the end and/or the start timestamp in the shared memory (Kobayashi, Execution Time Threshold Fig. 5 and Fig. 6 is an end timestamp and is stored in the setting register 115); and
reading, by use of the first and/or the second monitoring thread, the saved first, the saved second, the saved end and/or the saved start timestamp from the shared memory (Kobayashi, control program processes such as execution sequence monitoring comparison circuit 113 and execution time monitoring timer circuit 111 read the Execution Time Threshold (i.e. end timestamp) for each of Processing 1 to Processing N during execution measurement examples in Figs. 8-9).
Regarding dependent claim 29, Kobayashi teaches wherein
the electronic control unit comprises a hardware counter (Kobayashi, Program Execution Monitoring Dedicated Circuit 110 (part of MCU 31 and MCU 31 is part of Electronic Control Unit 30) paragraph 0050 teaches “Further, the other attached circuit 117 is provided with a hardware (HW) timer, a timer counter, a comparison register etc….”),
the first timestamp is generated based on a value of the hardware counter at the first predefined time during the execution of the first thread to be monitored (Kobayashi, Fig. 8, paragraph 0064 for each Processing n “the monitoring of the execution time by the execution time monitoring timer circuit 111 starts. In addition, here, the above monitoring of execution time is performed by means of a timer within the program execution monitoring dedicated circuit. Further, with respect to the above time measurement, it is also possible to perform a mutual conversion between a timer counter value of the program execution monitoring dedicated circuit 110 and a calculation value of a real time based on the timer counter value of the program execution monitoring dedicated circuit 110 and then use these.”),
the second timestamp is generated based on a value of the hardware counter at the second predefined time during the execution of the second thread to be monitored (Kobayashi, Fig. 8, paragraph 0064 for each Processing n “the monitoring of the execution time by the execution time monitoring timer circuit 111 starts. In addition, here, the above monitoring of execution time is performed by means of a timer within the program execution monitoring dedicated circuit. Further, with respect to the above time measurement, it is also possible to perform a mutual conversion between a timer counter value of the program execution monitoring dedicated circuit 110 and a calculation value of a real time based on the timer counter value of the program execution monitoring dedicated circuit 110 and then use these.”),
the start timestamp is generated based on a value of the hardware counter at the starting time of the first thread to be monitored (Kobayashi, Fig. 8, paragraph 0064 for each Processing n “the monitoring of the execution time by the execution time monitoring timer circuit 111 starts. In addition, here, the above monitoring of execution time is performed by means of a timer within the program execution monitoring dedicated circuit. Further, with respect to the above time measurement, it is also possible to perform a mutual conversion between a timer counter value of the program execution monitoring dedicated circuit 110 and a calculation value of a real time based on the timer counter value of the program execution monitoring dedicated circuit 110 and then use these.” Fig. 8 has vertical axis of execution time so Start times of each processing thread Processing 1 to Processing N are time values from time counter value.), and/or
the end timestamp is generated based on a value of the hardware counter at the end time of the first thread to be monitored (Kobayashi, Fig. 8, paragraph 0064 for each Processing n “the monitoring of the execution time by the execution time monitoring timer circuit 111 starts. In addition, here, the above monitoring of execution time is performed by means of a timer within the program execution monitoring dedicated circuit. Further, with respect to the above time measurement, it is also possible to perform a mutual conversion between a timer counter value of the program execution monitoring dedicated circuit 110 and a calculation value of a real time based on the timer counter value of the program execution monitoring dedicated circuit 110 and then use these.” Fig. 8 has vertical axis of execution time so Stop/end times of each processing thread Processing 1 to Processing N are time values from time counter value.).
Regarding claim 30, Kobayashi teaches:
An electronic control unit (Kobayashi, Fig. 2, ECU 30, paragraph 0043), comprising:
a processor (Kobayashi, Fig. 3, MCU 31 includes a CPU 130, paragraph 0044);
a memory in communication with the processor, the memory storing a plurality of instructions executable by the processor to configure the electronic control unit to (Kobayashi, Fig. 3, MCU 31 includes a ROM 150, RAM 170, paragraph 0044 teaches “Further, here, a control program of the electric power steering apparatus being comprised of a plurality of processes, control data, etc. are stored in the ROM 150, the CPU 130 performs the control of the electric power steering apparatus by executing the above control program, and the RAM 170 functions also as a work memory when the CPU 130 operates.”):
provide, to a first monitoring thread of multiple threads (Kobayashi, Abstract, “an execution sequence monitoring comparison circuit …perform monitoring of an execution sequence of a task executed by a control program of the on-vehicle electronic equipment …”. Paragraph 0048 teaches “the processes mean a plurality of control procedures that configure the control program…” [i.e. first monitoring thread]. Multiple threads are Processing 1 to Processing N shown in Figs. 8 and 9 and the processing of next period Processing 1 to Processing 3.), a first timestamp generated at a first predefined time during execution of a first thread to be monitored (Kobayashi, Figs. 8-9 teaches that a first thread may be any one of Processing 1 (i.e. first thread) to Processing N. Paragraph 0054 and Fig. 7, block S2 “Number Processing of Setting Register and Storing in Log Register” selects one of Processing 1 to Processing N. Paragraph 0065 and Fig. 8 shows a Stop time measurement for each Processing 1 to Processing N so for Processing 1 first thread, the first timestamp generated at a first predefined time is the time of the Stop. Paragraph 0065 “each processing is terminated before an elapsed time for the above each processing (the rising solid line from the bottom left to the top right in FIG. 8), that is, the execution time reaches the execution time threshold preliminarily set for each processing (the chain line of a horizontal direction shown in FIG. 8), the monitoring of the execution time by the execution time monitoring timer circuit 111 is stopped.”);
provide, to the first monitoring thread, a second timestamp generated at a second predefined time during execution of a second thread to be monitored (Kobayashi, Fig. 8, Processing 2 in the leftmost period (i.e. second thread). For Processing 2, as shown in Figs. 5 and 8, completion occurs after sequence flow of Processing 1 and Stop time is a second timestamp generated at a second predefined time); and
check, by the first monitoring thread, whether the first timestamp is provided before the second timestamp (Kobayashi, Figs. 4-8, paragraph 0046 “execution sequence monitoring comparison circuit 113 is a circuit that monitors whether a task (a processing) executed by the control program in the CPU 130 is performed in order or not, and is a circuit that monitors whether or not the processing is executed under a predetermined process”. Fig. 5, paragraph 0048 teaches “respective head addresses of a plurality of processings (for example, from a processing 1 to a processing n, where n=10) as processing address… of the above each processing (from a processing 1 to a processing n, where n=10) are set.” Fig. 7, paragraphs 0053-0061 teaches “Monitoring execution sequence” and Fig. 8 shows “a horizontal axis shows the flow of a plurality of processings, FIG. 8 also shows a case of further shifting to the same processing in the next period in the case of setting the number of a plurality of processings of one process to “N”.” ).
Kobayashi does not distinctly disclose operating in an AUTOSAR® adaptive platform or a Linux® platform and wherein the first thread to be monitored and the second thread to be monitored are executed at least partly in parallel.
Lee, in the same field of endeavor, teaches operating in an AUTOSAR® adaptive platform or a Linux® platform (Lee, paragraph 0020 teaches “stored in RAM 168 is operating system 154. Operating systems, useful in CEC complexes susceptible to running operations and responding to hung operations according to embodiments of the present invention, include LinuxTM …and others as will occur to those of skill in the art.”) and wherein the first thread to be monitored and the second thread to be monitored are executed at least partly in parallel (Lee, Fig. 2A and Fig. 3A paragraph 0039 “Next, the service processor may determine if multiple operation threads are running (step 303). The service processor may do this step by counting the number of entries in the list of threads, for example, list of threads 240 of FIG. 2A.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kobayashi to incorporate the teachings of Lee and provide for operating in an AUTOSAR® adaptive platform or a Linux® platform and wherein the first thread to be monitored and the second thread to be monitored are executed at least partly in parallel because such multithreaded operating system platforms are needed and useful in Central Electronics Complex servers that run thread operations at the same time and respond to hung operations and other thread timing issues that are present in such multithreaded systems (Lee, see paragraph 0020).
Response to Arguments
Applicant’s arguments filed 12/22/2025 have been fully considered, but they are not persuasive.
With regards to the 35 U.S.C. 101 Abstract Idea rejections of claims 16-30, Applicant’s representative on page 11 of the Reply argues:
the claims … are directed to eligible subject matter at least because they provide significantly more than the abstract idea by providing a technological improvement to the functioning of a computer. Specifically, the method according to amended claim 16 provides for "increasing a computing power of the electronic control unit such that larger data amounts may be handled in shorter time spans." ¶[0040]. This improvement to the functioning of a computer is in part due to the first thread to be monitored and the second thread to be monitored being executed at least partly in parallel.
The Examiner respectfully disagrees with Applicant’s argument that the final limitation 6 of amended claim 16 “first thread …are executed at least partly in parallel” is an additional element that amounts to significantly more than the judicial exception by providing a technological improvement to the functioning of a computer. As explained in the 35 U.S.C. 101 Abstract idea rejection given above, this limitation merely adds insignificant detail to the abstract idea originally recited in limitation 1 of claim 16 and repeats part of limitation 1 (“executed at least partly in parallel”). Furthermore, this final limitation 6 of amended claim 16 alone or in combination with the other elements does not provide significant detail as to the technological improvement in the functioning of the computer. Parallel processing in the reliability art is routine, well understood and conventional technological activity and thus, described at the level of detail given in claim 16, is not a technological improvement in the functioning of a computer.
In addition, as described in the 35 U.S.C. 101 Abstract idea rejection given above, limitation 6 is interpreted under BRI as parallel data messages that include the time or parallel pieces of paper that have the time written on them and are given to a person and, thus, are insignificant extra-solution activity. See MPEP 2106.05(g).
In their arguments, Applicant cites to paragraph [0040] of the originally filed specification describing an improvement of increasing computing power of the ECU so that larger amounts of data may be handled in shorter time but this improvement is not recited in any of the claims. Thus, the features upon which applicant relies to show the technological improvement (i.e., increasing computing power to handle more data in less time) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Thus, Applicant’s arguments with regards to the 35 U.S.C. 101 Abstract Idea rejections are not persuasive.
With regards to the 35 U.S.C. 102(a)(1) and 102(a)(2) rejections of independent claims 16 and 30, Applicant’s arguments with respect to these claims have been considered but are moot because the arguments are directed to the claim amendments that are addressed in the Examiner’s new grounds of rejections given above.
For at least the reasoning provided above, amended independent Claims 16 and 30 remain rejected.
With regard to the remaining dependent claims 17-21 and 23-29, the Remarks on page 12 argue that “Claims 17-21 and 23-29 are patentable due to their dependence from claim 16.” Applicant’s representative does not discuss any further reasons as to why Kobayashi does not teach the limitations of these claims; therefore, Claims 17-21 and 23-29 remain rejected using at least the reasoning provided above in this Office Action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure. Applicants are required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/INDRANIL CHOWDHURY/ Examiner, Art Unit 2114
/ASHISH THOMAS/ Supervisory Patent Examiner, Art Unit 2114