DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-4, in the reply filed on 05/13/2026 is acknowledged.
Claims 5-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/13/2026.
Drawings
The drawings are objected to because while an insulating member (Item 7) is shown in Fig. 10 of the Applicant’s drawings, Item 7 is not indicated as being a part of the insulating substrate as is recited in the Applicant’s specification and claim 4. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Takizawa (US 2021/0082780) hereinafter “Takizawa”.
Regarding claim 1, Fig. 2 of Takizawa teach a semiconductor device comprising: a plurality of semiconductor elements (Items 3); an insulating substrate (Combination of Items 22, 20, 21 and 12) having, on its upper surface, a mounting area where the plurality of semiconductor elements (Items 3) are mounted and a non-mounting area (Combination of the top surface of Item 12 and Top surface of Item 26) protruding upward from the mounting area (Top surface of Item 21 where Items 3 are located) and where the plurality of semiconductor elements are not mounted; and where a metal lead electrode (Item W1) is bonded (See Examiner’s Note below) to an upper surface of each of the semiconductor elements with a bonding material (Where the wire is bonded/attached to the semiconductor element in some manner; See Examiner’s Note below), where a difference in height between the mounting area and the non-mounting area is greater than or equal to a thickness of each of the semiconductor elements.
Examiner’s Note: The Examiner notes that the recitation of a “bonding material” does not require any specific material nor does it require that the material of the bonding material be different from the metal lead electrode. Therefore, any material that allows the wiring of Takizawa to be bonded to the semiconductor elements reads on the bonding material.
Regarding claim 2, Fig. 5B of Takizawa further teaches where the insulating substrate (Combination of Items 22, 20, 21 and 12) includes an insulating base material (Item 20), and a circuit pattern (Item 21) provided on the insulating base material (Item 20), an upper surface of the circuit pattern has a convex portion (Top surface of Item 26), an end surface of the convex portion is the non-mounting area, and the upper surface of the circuit pattern (Item 21) other than the convex portion is the mounting area.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Alternatively, Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al. (US 2015/0115282) hereinafter “Takahashi”.
Regarding claim 1, Fig. 6 of Takahashi teaches a semiconductor device comprising: a plurality of semiconductor elements (Items 22); an insulating substrate (Combination of Items 30A, 14, 16 and 18) having, on its upper surface, a mounting area (Portions of top surface of Items 16 where Items 22 are located) where the plurality of semiconductor elements (Items 22) are mounted and a non-mounting area (Top surface of Item 30a) protruding upward from the mounting area and where the plurality of semiconductor elements (Items 22) are not mounted; and a metal lead electrode (Item 40), wherein a difference in height between the mounting area and the non-mounting area is greater than or equal to a thickness of each of the semiconductor elements (Items 22).
Fig. 6 of Takahashi does not teach where the metal lead electrode is bonded to an upper surface of each of the semiconductor elements with a bonding material.
However, Fig. 12 of Takahashi teaches where the metal lead electrode (Item 40) is electrically connected to a plurality of semiconductor elements (Item 22) and Fig. 13 of Takahashi teaches where the metal lead (Combination of Items 40 and 90) is bonded to an upper surface of a semiconductor element (Item 22) with a bonding material (Item 20).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the metal lead electrode be bonded to an upper surface of each of the semiconductor elements with a bonding material because this eliminates the need to connect a wire to the semiconductor element which reduces manufacturing costs (Takahashi Paragraph 0052).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al. (US 2015/0115282) hereinafter “Takahashi” in view of Yoshihara (US 2022/0115351) hereinafter “Yoshihara”.
Regarding claim 3, Takahashi teaches all of the elements of the claimed invention as stated above.
Fig. 6 of Takahashi further teaches where the insulating substrate (Combination of Items 30A, 14, 16 and 18) includes an insulating base material (Item 14), and a circuit pattern (Item 16) provided on the insulating base material (Item 14).
Takahashi does not teach where an upper surface of the circuit pattern has a concave portion, a bottom surface of the concave portion is the mounting area, and the upper surface of the circuit pattern other than the concave portion is the non-mounting area.
Fig. 11 of Yoshihara teaches where an upper surface of a circuit pattern (Item 7A) has a concave portion, a bottom surface of the concave portion is a mounting area, and an upper surface of the circuit pattern (Item 7A) other than the concave portion is a non mounting area.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an upper surface of the circuit pattern have a concave portion, a bottom surface of the concave portion is the mounting area, and the upper surface of the circuit pattern other than the concave portion is the non-mounting area because this suppresses relative movement of the semiconductor element and the circuit pattern in the x and y direction (Yoshihara Paragraph 0074).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al. (US 2015/0115282) hereinafter “Takahashi” in view of Ishibashi et al. (US 2020/0185295) hereinafter “Ishibashi”.
Regarding claim 4, Fig. 6 of Takahashi further teaches where the insulating substrate (Combination of Items 30A, 14, 16 and 18) includes an insulating base material (Item 14), a circuit pattern (Item 16) provided on the insulating base material (Item 14), and an insulating member (Item 30A), an upper surface of the insulating member (Item 30A) is the non-mounting area, and a region of the upper surface of the circuit pattern (Item 16) where the insulating member (Item 30A) is not provided is the mounting area.
Takahashi does not teach where the insulating member is provided on the upper surface of the circuit pattern.
Fig. 1 of Ishibashi teaches where an insulating member (Item 10) is provided on an upper surface of a circuit pattern (Item 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the insulating member be provided on an upper surface of a circuit pattern because this allows the remaining portion of the insulating substrate to be fixed into the insulating member (Ishibashi Paragraph 0029).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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