DETAILED ACTION
1. This action is in response to the application filed on 3/2724.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bandyopadhyay et al. (US 20170302178).
Regarding claim 1: Bandyopadhyay et al. disclose a control method for a switching power supply (i.e. figures 1-6), wherein the switching power supply (i.e. figures 1-6) comprises a first switching transistor (i.e. S1), a second switching transistor (i.e. S2), a filter inductor (i.e. L), and a control module (i.e. module of 101), wherein the first switching transistor (i.e. S1) is connected between a voltage input terminal (i.e. Vin) and the filter inductor (i.e. L), the second switching transistor (i.e. S2) is connected between the first switching transistor (i.e. S1) and a ground terminal (i.e. ground), the filter inductor (i.e. L) is connected between the first switching transistor (i.e. S1) and a voltage output terminal (i.e. Vo) of the switching power supply, and the control module (i.e. module of 101) is configured to control the first switching transistor (i.e. S1) and the second switching transistor (i.e. S2) to turn on or turn off, and
wherein the control method comprises:
after the switching power supply (i.e. figures 1-6) is started, the control module (i.e. module of 101) acquires a voltage waveform (i.e. VSW) at a connection point (i.e. point of VSW) between the first switching transistor (i.e. S1) and the filter inductor (i.e. L);
in response to the voltage waveform (i.e. VSW) at the connection point (i.e. point of VSW) not achieving zero-voltage switching (i.e. ZVS), the control module (i.e. module of 101) adjusts a cut-off current (i.e. figure 6: S2 off during 214) of the second switching transistor (i.e. S2) until the voltage waveform (i.e. VSW) at the connection point just reaches a high level (i.e. figure 6: signal VSW 612, 622 and/or 632 reaching VTH, VIN); and
in response to the voltage waveform (i.e. VSW) at the connection point just reaching the high level (i.e. point of VSW), the control module (i.e. module of 101) controls the first switching transistor (i.e. S1) to turn on to achieve zero-voltage turn-on of the first switching transistor (i.e. S1) (i.e. ¶ 22 and 29-31).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bandyopadhyay et al. (US 20170302178) in view of Kubota et al. (US 20050212498).
Regarding claim 5: Bandyopadhyay et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the switching power supply further comprises an absorption circuit connected in parallel to two ends of the second switching transistor; and the absorption circuit comprises a first resistor and a first capacitor connected in series with each other.
Kubota et al. disclose the switching power supply (i.e. figure 1) further comprises an absorption circuit (i.e. Rsaw1, Csaw1, Csaw2) connected in parallel to two ends of the second switching transistor (i.e. S2); and the absorption circuit comprises a first resistor (i.e. Rsaw1) and a first capacitor (i.e. Csaw1) connected in series with each other.
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Bandyopadhyay et al.’s invention with the power supply as disclose by Kubota et al. to have stability of the switching power supply is ensured without lowering the frequency band of said amplified error signal and stable output ripple characteristics can be materialized.
Regarding claim 16: Bandyopadhyay et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the voltage divider circuit comprises a second resistor and a third resistor connected in series with each other.
Kubota et al. disclose the switching power supply (i.e. figure 1) further comprises the voltage divider circuit comprises a second resistor (i.e. R1) and a third resistor (i.e. R2) connected in series with each other.
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Bandyopadhyay et al.’s invention with the power supply as disclose by Kubota et al. to have stability of the switching power supply is ensured without lowering the frequency band of said amplified error signal and stable output ripple characteristics can be materialized.
Allowable Subject Matter
7. Claims 7-10 and 17-18 are allowed.
The following is an examiner’s statement of reasons for allowance: In regards to claim 7, the prior art fails to disclose a load at an output terminal of the switching power supply changes, and a switching current of the first switching transistor is greater than a first preset value, the control module is further configured to adjust a peak current of the first switching transistor according to an output voltage of the switching power supply to achieve a loop control for stabilizing the output voltage of the switching power supply; after the loop control for stabilizing the output voltage of the switching power supply is implemented, when the load at the output terminal of the switching power supply changes and the switching current of the first switching transistor is less than or equal to the first preset value, the control module is further configured to control the switching current of the first switching transistor to maintain at the first preset value, change a frequency of a drive signal of the first switching transistor, and enter a light-load ZVS mode from a heavy-load ZVS mode to adjust the output voltage of the switching power supply; and after the light-load ZVS mode is entered to adjust the output voltage of the switching power supply, when the load at the output terminal of the switching power supply changes and a time interval between zero-crossing turn-off of the second switching transistor and next turn-on of the second switching transistor is equal to or less than a second preset value, the control module is further configured to enter the heavy-load ZVS mode again from the light-load ZVS mode and adjust the peak current of the first switching transistor.
8. Claims 2-4, 6, 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/ Primary Examiner, Art Unit 2838
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