DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moriya (US20070176518, hereinafter Moriya).
Regarding claim 1, Moriya discloses a piezoelectric vibration device (Figs. 6 and 8) comprising: an insulating substrate (1) that includes a wiring pattern (7, 16) including a plurality of pads (4, 17) on one of a pair of principal surfaces, and an external connection terminal (5) electrically connected to the wiring pattern and electrically connected to an external substrate (9) on the other one of the principal surfaces extending in parallel to the one of the principal surfaces; and at least a piezoelectric oscillator (2) and an integrated circuit element (15) including an oscillation circuit that are mounted on the insulating substrate (1 and 12), wherein the insulating substrate includes a recessed portion (left and right of 12) in the other one of the principal surfaces, and the external connection terminal (5) is arranged in the recessed portion and is configured such that a gap (gap between 5 and 12) is provided between an outer edge of the external connection terminal and a side surface of the recessed portion.
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Regarding claim 6, the IC and the piezoelectric oscillator are formed on the upper surface of the substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1- 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (US20080266003, hereinafter Yamashita) in view of Ito (US20030155638, hereinafter Ito).
Regarding claim 1, Yamashita discloses a piezoelectric vibration device (10) comprising: an insulating substrate (12a) that includes a wiring pattern including a plurality of pads (15, 17) on one of a pair of principal surfaces, and an external connection terminal (18) electrically connected to the wiring pattern and electrically connected to an external substrate (90) on the other one of the principal surfaces extending in parallel to the one of the principal surfaces; and at least a piezoelectric oscillator (20) and an integrated circuit element (IC) including an oscillation circuit that are mounted on the insulating substrate, wherein the insulating substrate includes a recessed portion (where 18 is formed) in the other one of the principal surfaces, and the external connection terminal (18) is arranged in the recessed portion.
Yamashita fails to disclose the terminal electrode being configured such that a gap is provided between an outer edge of the external connection terminal and a side surface of the recessed portion.
Ito discloses an insulating substrate (3) including a recessed portion (3a) and the external connection terminal (5) configured such that a gap is provided between the outer edge of the external terminal and a side surface of the recessed portion (Fig. 4, paragraph [0058]). The recessed portions provide an area to receive the solder balls (7) and establish the electrical connection while minimizing the risk of short circuits once the solder is melted. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the instant application to provide an external connection terminal such that a gap is provided between the outer edge of the external terminal and a side surface of the recessed portion to receive solder balls and establish electrical connections while minimizing the risk of short circuits.
Regarding claim 2, Ito discloses the external connection terminal is arranged in the recessed portion with a predetermined space from an outer edge of the recessed portion provided, when viewed in a perpendicular direction to the other one of the principal surfaces. See Figs. 4 and 5.
Regarding claim 3, a thickness from the one of the principal surfaces to a joined surface that is electrically connected to the external substrate in the external connection terminal is less than a thickness from the one of the principal surfaces to the other one of the principal surfaces. See Figs. 4 and 5.
Regarding claim 4, Ito discloses covering a semiconductor chip (6) with resin (19, 20).
Regarding claim 5, Yamashita and Ito discloses the invention as explained above, but fails to explicitly disclose the insulating substrate configured such that a portion of an internal wiring electrically connecting the wiring pattern and the external connection terminal is not covered with a base material of the insulating substrate and is exposed, the portion of the internal wiring being located at the other one of the principal surfaces. The examiner takes Official Notice that exposed internal wiring not covered with a base material is old and well known in the art for the purpose of establishing and facilitating electrical connections without the need of through holes.
Regarding claim 6, the IC and the piezoelectric oscillator are formed on the upper surface of the substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Miyazaki discloses a piezoelectric oscillator comprising an IC and piezoelectric oscillator formed on opposite surfaces of the substrate and uncovered electrical connections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jaydi San Martin whose telephone number is (571)272-2018. The examiner can normally be reached on M-Th 7:45-6:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dedei Hammond can be reached on 571-270-7938. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J. San Martin/
Primary Examiner, Art Unit 2837
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