Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, in the reply filed on July 1, 2026, is acknowledged.
Claims 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 1, 2026.
Drawings
The drawings are objected to because:
In Fig. 8B, there are missing lines on the left side of the opening containing the heat sink (4) and on the lower portions of the left side of the package (1).
In Fig. 8C, some portions of the labels are missing. In addition, the entire line defining the left side of the package (1) is missing.
In Fig. 8D, the line defining the right-hand side of the second portion of the heat sink (42) is missing. In addition, some portions of the labels are missing.
In Fig. 8E, several lines are missing, including the right-hand side of the second die (6), the left-hand side of the package (1) and most of the right-hand side, and the left-hand side of the wall of the cavity containing the heat sink (4).
In Fig. 8F, the line defining the upper portion of the left-hand side of the cavity containing the heat sink (4) is missing.
In Fig. 10, a line is missing on the right-hand side of the motherboard (3).
In Fig. 11, a line is missing from the top of the motherboard (3) near the left-hand side of the electronic package.
In Fig. 12, most of the lines defining the motherboard (3) are missing.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0006], “the first die and the second die are electrically connected through the interconnect substrate” should be “and the first die and the second die are electrically connected through the interconnect substrate”.
In paragraph [0011], “the first die and the second die are arranged in a space surrounded by the stiffener ring” should be “and the first die and the second die are arranged in a space surrounded by the stiffener ring”.
In paragraph [0013], “the interconnect substrate includes” should be “and the interconnect substrate includes”.
In paragraph [0016], “a width of the second connection bump” and “a width of the first connection bump” should be “a width of the second connection bumps” and “a width of the first connection bumps”, respectively.
Appropriate correction is required.
Claim Objections
Claims 1, 6, 8, and 11 are objected to because of the following informalities:
In claim 1, line 5, “the first surface” should be “and the first surface”.
Claim 6 is dependent directly on claim 1, but it is interposed between two claims that are themselves dependent on claims that are dependent on claim 1 (claim 5 depends on claim 3, and claim 8 depends on claim 2).
In claim 6, line 2, “the first die” should be “and the first die”.
In claim 8, line 6, “the interconnect substrate” should be “and the interconnect substrate”.
In claim 11, line 2, “second connection bump” and “first connection bump” should be “second connection bumps” and “first connection bumps”, respectively.
Appropriate correction is required.
PNG
media_image1.png
582
1131
media_image1.png
Greyscale
Fig. 6 of Lee, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Lee et. al., Pub. No. US 2016/0302308, hereafter referred to as Lee.
Regarding claim 1, Lee teaches all of the limitations of the claim in Fig. 6, reproduced above with annotations added by the examiner: “An electronic packaging” ([0003]; Fig. 6), “comprising: a package substrate” ([0048]; Fig. 6, circuit board 100) “and an interconnect substrate” ([0052], [0057]; Fig. 6, microcircuit structure 10A and core insulating layer 11), “wherein: a first surface of the package” (Fig. 6, upper surface of the circuit board 100) “is provided with a recess” ([0048]; Fig. 6, through hole 101) “in which the interconnect substrate is embedded” (Fig. 6; note that the through hole 101 contains the microcircuit structure 10A and core insulating layer 11); “and a bottom of the interconnect substrate” (Fig. 6, bottom surface of the core insulating layer 11) “is provided with a first heat sink” ([0112]; Fig. 6, metal layer 12); “the first surface of the package substrate” (Fig. 6, upper surface of the circuit board 100) “is provided with a first die” ([0101]; Fig. 6, first electronic component 501) “and a second die” ([0101]; Fig. 6, second electronic component 502), “and the first die and the second die” ([0101]; Fig. 6, first and second electronic components 501 and 502) “are electrically connected through the interconnect substrate” (Fig. 6; note that the first and second electronic components 501 and 502 are connected to the microcircuit structure 10A through the second pads 42).
PNG
media_image2.png
613
676
media_image2.png
Greyscale
Fig. 1 of Gui, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Gui et. al., Pub. No. CN 114599145, hereafter referred to as Gui.
Regarding claim 2, Lee teaches “The electronic packaging according to claim 1”, but does not teach “wherein the recess comprises a first recess and a second recess, the first recess is connected with the second recess, and a width of the second recess is smaller than a width of the first recess; the first heat sink is supported in the second recess, at least part of the first heat sink is arranged in the first recess, and the interconnect substrate is arranged in the first recess and supported on the first heat sink.”
Gui, on the other hand, does teach “wherein the recess comprises a first recess and a second recess” (Gui Fig. 1, first and second grooves 21 and 22), “the first recess is connected with the second recess” (Gui [0042]: “The first groove 21 is spatially connected to the second groove 22…”; Fig. 1, note that the second recess is connected to the first recess), “and a width of the second recess is smaller than a width of the first recess” (Gui [0042]: “…and the first width W1 of the first groove 21 is greater than the second width W2 of the second groove 22.”); “the first heat sink is supported in the second recess” (Gui [0043]; Fig. 1, note that the base 31 of heat dissipation copper block 3 rests on top of the second recess), and “at least part of the first heat sink is arranged in the first recess” (Gui [0043]: “The first groove 21 is used to accommodate the base 31 of the heat dissipation copper block 3…”; Fig. 1, base 31).
The shape of the heat sink in Gui can be incorporated into the device of Lee by creating a two-part recess in said device, the second part being at the bottom and having a smaller width than the first, disposing the first heat sink inside of the recess, and disposing the interconnect substrate on top of the first, larger, portion of the heat sink. The combined device teaches “and the interconnect substrate is arranged in the first recess and supported on the first heat sink” (Lee Fig. 6; microcircuit structure 10A and core insulating layer 11; Gui Fig. 1, first groove 21 and base 31; note that the microcircuit structure 10A and core insulating layer 11 of Lee would be disposed within the first groove 21 of Gui and on top of the base 31 of Gui in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have made a two-part recess as taught by Gui in the device of Lee because the second recess would provide a way for air or a liquid to transport heat away from the heat sink and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art to have arranged the recess such that the second, narrower, recess is on the opposite side from the interconnect substrate of Lee because it would be easier to assemble the device if the recess is so arranged (the heat sink can be formed separately and simply inserted into the opening before providing the interconnect substrate) and it would be a simple combination of elements of the two disclosures.
Regarding claim 3, the combination of Lee and Gui described in the discussion of claim 2 teaches “The electronic packaging according to claim 2”, but does not teach “wherein the first heat sink comprises a first thermal dissipation part and a second thermal dissipation part; the first thermal dissipation part is connected with the second thermal dissipation part, and a width of the second thermal dissipation part is smaller than a width of the first thermal dissipation part; the second thermal dissipation part is arranged in the second recess, and the first thermal dissipation part is arranged in the first recess and supported on a stair at a transitional junction between the first recess and the second recess; and the interconnect substrate is supported on the first thermal dissipation part.”
Gui, on the other hand, does teach “wherein the first heat sink comprises a first thermal dissipation part” (Gui [0043]; Fig. 1, base 31) “and a second thermal dissipation part” (Gui [0043]; Fig. 1, extension 32); “the first thermal dissipation part is connected with the second thermal dissipation part” (Gui Fig. 1; note that the base 31 and the extension 32 are connected), “and a width of the second thermal dissipation part is smaller than a width of the first thermal dissipation part” (Gui [0042]: “…the first width W1 of the first groove 21 is greater than the second width W2 of the second groove 22.” and [0043]: “The first groove 21 is used to accommodate the base 31 of the heat dissipation copper block 3, and the second groove 22 is used to accommodate the extension 32 of the heat dissipation copper block 3.”; Fig. 1, base 31 and extension 32); “the second thermal dissipation part is arranged in the second recess” (Gui [0043]; Fig. 1, note that the extension 32 is disposed inside the second groove 22), “and the first thermal dissipation part is arranged in the first recess” (Gui [0043]; Fig. 1, note that the base 31 is disposed inside the first groove 21) “and supported on a stair at a transitional junction between the first recess and the second recess” (Gui Fig. 1; note that the base rests on a step at the junction between the first groove 21 and the second groove 22).
The two-part heat sink of Gui can be incorporated into the combined device of Lee and Gui described in the discussion of claim 2 by making the heat sink of the combined device with two parts, the first designed to fit inside the first recess and the second designed to fit inside the second recess. The combined device teaches “and the interconnect substrate is supported on the first thermal dissipation part” (Lee Fig. 6; note that the microcircuit structure 10A and core insulating layer 11 would be disposed on top of the base 31 of Gui in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have made the heat sink out of two parts, one narrower than the other, as taught by Gui because it would then fit into the two-part recess of the combined device of Lee and Gui described in the discussion of claim 2 and it would be a simple combination of elements of the two disclosures.
Regarding claim 4, the combination of Lee and Gui described in the discussion of claim 3 further teaches “The electronic packaging according to claim 3, wherein the second recess penetrates through a second surface of the package substrate” (Gui Fig. 1; note that the second groove 22 penetrates through the circuit board 1).
PNG
media_image3.png
552
855
media_image3.png
Greyscale
Fig. 11 of Teng, reproduced with annotations and notation of the axial direction added by the examiner.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Gui, in further view of Teng et. al., Pub. No. US 2020/0411439, hereafter referred to as Teng.
Regarding claim 5, the combination of Lee and Gui described in the discussion of claim 3 teaches “The electronic packaging according to claim 3”, but does not teach “further comprising a thermal dissipation hole, which is arranged in the second thermal dissipation part of the first heat sink at least along an axial direction of the first heat sink.”
Teng, on the other hand, does teach “further comprising a thermal dissipation hole” (Teng Fig. 11, thermal dissipation hole and inlet I and outlet O) and “which is arranged… at least along an axial direction of the first heat sink” (Teng [0038]; Fig. 11; note that the inlet I and outlet O are arranged along the axial direction). Teng further teaches that these holes are arranged in the bottom of the heat sink (Teng [0036]; Fig. 11; heat spreader 121), opposite a chip package (Teng [0026]; Fig. 11, chip package 40) and that they are connected by a channel Teng [0038]: “In some embodiments, the heat spreader 121 further includes an inlet I and an outlet O communicated with the flow channel, wherein the inlet I and the outlet O penetrate through the bottom plate 121b of the heat spreader 121.”).
The thermal dissipation hole of Teng can be incorporated into the combined device of Lee and Gui described in the discussion of claim 3 as similar thermal dissipation holes in the bottom of the heat sink in said combined device, placing said holes in the extension region of the heat sink. The combined device teaches “(a thermal dissipation hole arranged) in the second thermal dissipation part of the first heat sink” (Teng [0038]; Fig. 11, inlet I and outlet O; note that the inlet I and outlet O would be provided in the extension 32 of Gui in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include a thermal dissipation hole as taught by Teng in the combined device of Lee and Gui described in the discussion of claim 3 because doing so would allow for the device to be liquid cooled, and it would be a simple combination of elements of the two disclosures.
PNG
media_image4.png
502
890
media_image4.png
Greyscale
Fig. 1 of Elsherbini, reproduced with annotations and lines separating the stiffener ring and second heat sink added by the examiner.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Elsherbini et. al., Pub. No. US 2020/0273839, hereafter referred to as Elsherbini.
Regarding claim 6, Lee teaches “The electronic packaging according to claim 1”, but does not teach “further comprising: a stiffener ring arranged on the package substrate; the first die and the second die are arranged in a space surrounded by the stiffener ring.”
Elsherbini, on the other hand, teaches a heat spreader (Elsherbini [0032]; Fig. 1, reproduced above with annotations added by the examiner, heat spreader 131) disposed around three semiconductor dies (Elsherbini [0032] and [0037]; Fig. 1, dies 114-2, 114-3, and 114-4). The heat spreader may be divided into two regions, the lower of which may be treated as a stiffener ring and the upper as a second heat sink (Elsherbini Fig. 1, stiffener ring and second heat sink).
The heat spreader of Elsherbini can be incorporated into the device of Lee as a similar heat spreader surrounding the two dies. In light of the ability to divide up the heat spreader into a stiffener ring and a second heat sink, the combined device teaches “further comprising: a stiffener ring arranged on the package substrate” (Elsherbini Fig. 1, stiffener ring) and “the first die and the second die are arranged in a space surrounded by the stiffener ring” (Elsherbini Fig. 1; note that the dies 114-2 and 114-3 are surrounded by the stiffener ring).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include a heat spreader on the top of the device of Lee as taught by Elsherbini because doing so would further enhance the cooling of the device and it would be a simple combination of elements of the two disclosures.
Regarding claim 7, the combination of Lee and Elsherbini described in the discussion of claim 6 further teaches “The electronic packaging according to claim 6, further comprising a second heat sink supported on the stiffener ring” (Elsherbini Fig. 1, note that the second heat sink is supported by the stiffener ring), “wherein the second heat sink corresponds to the first die and the second die” (Elsherbini Fig. 1; note that the second heat sink is disposed above the dies 114-2 and 114-3).
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Gui, in further view of Elsherbini.
Regarding claim 8, the combination of Lee and Gui described in the discussion of claim 2 teaches “The electronic packaging according to claim 2, wherein, the package substrate comprises: a first interconnect layer” (Lee [0051]; Fig. 6, first pads 115), “wherein the first recess is arranged in the first interconnect layer” (Lee [0048]; fig. 6, through hole 101), “and the first interconnect layer comprises first metal wiring layers and first dielectric layers which are alternately stacked” (Lee [0049]: “In this example, the circuit board 100 is a multilayer printed circuit board including a plurality of circuit layers and a plurality of insulating layers, and at least one of the insulating layers is interposed between the circuit layers so as to insulate the circuit layers from each other…”; Fig. 6, circuit board 100); “the interconnect substrate comprises: a second interconnect layer” (Lee [0052]; Fig. 6, microcircuit structure 10A), “comprising second metal wiring layers and second dielectric layers which are alternately stacked” (Lee [0053]: “In this example, the microcircuit structure 10A includes a plurality of circuit layers and a plurality of insulating layers, and at least one of the insulating layers is interposed between the circuit layers so as to insulate the plurality of circuit layers from each other.”), “and an arrangement density of the second metal wiring layers is greater than an arrangement density of the first metal wiring layers” (Lee [0054]: “The circuit layers of the microcircuit structure 10A may have a micropattern having a pitch smaller than that of the circuit layers of the circuit board 100.”), but does not teach “wherein the second dielectric layer comprises an organic material”.
Elsherbini, on the other hand, anticipates “wherein the second dielectric layer comprises an organic material” by teaching that the second dielectric layer may be made of polyimide (Elsherbini [0036]: “In some embodiments, the insulating material of a die 114 may include a dielectric material, such as… polyimide…”), which is an organic material.
The teaching of polyimide as a dielectric material for the semiconductor dies of Elsherbini can be incorporated into the combined device of Lee and Gui described in the discussion of claim 2 by using polyimide as the dielectric material in the dies of said combined device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use polyimide, as taught by Elsherbini, as the dielectric material in the dies of the combined device of Lee and Gui described in the discussion of claim 2 because it is capable of serving the function of a dielectric material and it would be a simple substitution of one material for another.
Regarding claim 9, the combination of Lee, Gui, and Elsherbini described in the discussion of claim 8 further teaches “The electronic packaging according to claim 8, wherein the organic material comprises polyimide” (Elsherbini [0036]).
Regarding claim 10, the combination of Lee, Gui, and Elsherbini described in the discussion of claim 8 teaches “The electronic packaging according to claim 8, wherein the package substrate further comprises: a plurality of first connection bumps located on an upper surface of the first interconnect layer” (Lee [0051]; Fig. 6, first pads 115; note that there are bumps disposed on the first pads 115), “wherein a first chip, a second chip… are electrically connected with the package substrate through the first connection bumps” (Lee [0101]; Fig. 6, electronic components 501 and 502); “the interconnect substrate further comprises a plurality of second connection bumps located on an upper surface of the second interconnect layer” (Lee [0057]; Fig. 6, note the second pads 42 disposed on top of the microcircuit structure 10A), “wherein a part of the first chip and a part of the second chip are electrically connected with the interconnect substrate through the second connection bumps” (Lee [0114]; Fig. 6, note that portions of the electronic components 501 and 502 are connected to the second pads 42), but does not teach “a third chip (is electrically connected with the package substrate through the first connection bumps)”.
Elsherbini, on the other hand, does teach “a third chip (is electrically connected with the package substrate through the first connection bumps)” (Elsherbini [0032]; Fig. 1, die 114-4; also see [0046]: “The die 114-4 may be electrically and mechanically coupled to the package substrate 102 by DTPS interconnects 150-3.”).
The third die of Elsherbini can be incorporated into the combined device of Lee, Gui, and Elsherbini described in the discussion of claim 8 by introducing a third electronic component, solely connected to the first pads 115 of Lee, into said combined device.
It would have been obvious to one of ordinary skill in the art to introduce a third die, as taught by Elsherbini, into the combined device of Lee, Gui, and Elsherbini described in the discussion of claim 8 because a third chip would be capable of providing additional functionality to the device and it would be a simple combination of elements of the two disclosures.
Regarding claim 11, the combination of Lee, Gui, and Elsherbini described in the discussion of claim 10 further teaches “The electronic packaging according to claim 10, wherein, a width of the second connection bump is smaller than a width of the first connection bump; and/or a distance between adjacent second connection bumps is smaller than a distance between adjacent first connection bumps” (Lee [0058]: “In this example, the second pads 42 have a pitch smaller than that of the first pads 115 and 125.”; Lee Fig. 6, first pads 115 and second pads 42).
PNG
media_image5.png
577
731
media_image5.png
Greyscale
Fig. 1 of Ong, reproduced with annotations added by the examiner.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ong et. al., Pub. No. US 2022/0068750, hereafter referred to as Ong.
Regarding claim 12, Lee teaches “An electronic apparatus, comprising the electronic packaging according to claim 1”, but does not teach “a motherboard for an assembly of the electronic packaging, wherein the electronic packaging is electrically connected with the motherboard through the package substrate.”
Ong, on the other hand, teaches a semiconductor package (Ong [0037]; Fig. 1, semiconductor package 100) coupled to a motherboard (Ong [0037]; Fig. 1, circuit board 190) through the package substrate (Ong [0022]; Fig. 1, package substrate 110; also see [0037]: “The semiconductor package 100 may be coupled to a circuit board 190, e.g., a motherboard, through solder balls 192 and associated contact pads.”; note that the solder balls 192 are attached to the package substrate 110).
The circuit board of Ong can be incorporated into the device of Lee by attaching the semiconductor package of Lee to a circuit board.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have attached the device of Lee to a circuit board as taught by Ong because doing so would allow the device of Lee to function as part of a larger electronic device and it would be a simple combination of elements of the two disclosures.
PNG
media_image6.png
544
787
media_image6.png
Greyscale
Fig. 1 of Refai-Ahmed, reproduced with annotations added by the examiner.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Ong in further view of Refai-Ahmed et. al., Pub. No. US 2012/0075807, hereafter referred to as Refai-Ahmed.
Regarding claim 13, the combination of Lee and Ong described in the discussion of claim 12 teaches “The electronic apparatus according to claim 12”, but does not teach “wherein the motherboard is provided with a first through hole at a position corresponding to the recess.”
Refai-Ahmed, on the other hand, does teach “wherein the motherboard is provided with a first through hole at a position corresponding to the recess” (Refai-Ahmed [0029]; Fig. 1, note that the circuit board 85 has an aperture 95 within which a thermal management device 75 is disposed).
The aperture in the circuit board of Refai-Ahmed may be incorporated into the combined device of Lee and Ong described in the discussion of claim 12 as a similar aperture disposed underneath the location of the heat sink of said combined device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce an aperture underneath the heat sink of the combined device of Lee and Ong described in the discussion of claim 12 as taught by Refai-Ahmed because doing so would allow air or a liquid to reach the semiconductor package, allowing it to be cooled, and it would be a simple combination of elements of the two disclosures.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Ong, and Refai-Ahmed, in further view of Gui.
Regarding claim 14, the combination of Lee, Ong, and Refai-Ahmed described in the discussion of claim 13 teaches “The electronic apparatus according to claim 13”, but does not teach “wherein the recess penetrates through a second surface of the package substrate and is connected with the first through hole.”
Gui, on the other hand, teaches a recess penetrating through the bottom of a circuit board containing a heat sink (Gui [0042]; Fig. 1, note that the first and second recesses 21 and 22 penetrate through the top and bottom surfaces of the circuit board 1, respectively).
The recess penetrating through both surfaces of the circuit board taught by Gui can be incorporated into the combined device of Lee, Ong, and Refai-Ahmed as a recess in the semiconductor package that penetrates both surfaces of the circuit board and contains the heat sink. The combined device teaches “wherein the recess penetrates through a second surface of the package substrate and is connected with the first through hole” (Gui [0042]; Fig. 1, first and second recesses 21 and 22; Refai-Ahmed [0029]; Fig. 1, aperture 95; note that the aperture 95 of Refai-Ahmed would be connected with the second recess 22 of Gui in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have had the recess in the package substrate penetrate through the bottom surface of the package, as taught by Gui, and be connected with the aperture of the combined device of Lee, Ong, and Refai-Ahmed because the resulting opening allows the surrounding air or a liquid to more easily reach the heat sink and it would be a simple combination of elements of the two disclosures.
Regarding claim 15, the combination of Lee, Ong, Refai-Ahmed, and Gui described in the discussion of claim 14 teaches “The electronic apparatus according to claim 14”, but does not teach “wherein the first heat sink is protruded into the first through hole from the package substrate.”
Refai-Ahmed, on the other hand, does teach “wherein the first heat sink is protruded into the first through hole from the package substrate” (Refai-Ahmed [0029]; Fig. 1, note that the thermal management device 75 protrudes through the aperture 95).
The protrusion of the heat sink of Refai-Ahmed can be incorporated into the combined device of Lee, Ong, Refai-Ahmed, and Gui described in the discussion of claim 14 by having the heat sink protrude through the aperture of said claimed device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have the heat sink protrude through the aperture of the combined device of Lee, Ong, Refai-Ahmed, and Gui as taught by Refai-Ahmed because doing so would further enhance the ability of the surrounding air or a liquid to transport heat away from the heat sink and it would be a simple combination of elements of the two disclosures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/R.E.T./ Examiner, Art Unit 2818
/STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights