DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Sreenivasan ‘410 (WO 2020051410 A1).
As to claim 1, Sreenivasan ’410 discloses a system (Fig. 1, the system is shown.) for assembling a first substrate (Fig. 4, source wafer 440, see paragraph 00106, below) to a second substrate (Fig. 4, product wafer 450, see paragraph 00106, below), comprising:
one or more deformable substrate chucks (Fig. 7, wafer chuck 700, see paragraph 00110 below) utilized to match a topography of a bonding surface on said first substrate to a topography of a bonding surface on said second substrate (see paragraph 00110, disclosing "Fig. 7 is an example of a topography-controlled thermally-actuated wafer chuck that may be used in one or more embodiments of the present technology. In the embodiments, illustrated in Fig. 7, wafer chuck 700 could further have arrays of embedded z-actuators (piezo-electric, voice coil based, etc.) to change the topography of the wafer during a pick-and-place step"; See paragraph 00111, disclosing “As such, wafer chuck 700 can set the desired topography at the pin surface 770. For example, in some embodiments, topography errors (as well as in-plane distortions) could be sensed in an inline manner using chirped moiré alignment marks patterned on the wafers”).
See paragraphs 00095-111 below:
[0095] Various embodiments of the present technology provide for a wide range of technical effects, advantages, and/or improvements to fabrication systems and components. For example, various embodiments include one or more of the following technical effects, advantages, and/or improvements: 1) enable a number of applications which require nano-meter precise assembly of circuit elements (e.g., applications such as 3D integrated circuits, dies with super-lithographic form factors, hardware security and high-mix, low-volume ASICs, etc.); 2) a nano-meter precise assembly that is achieved by utilizing a variety of techniques including a novel process to produce buried sacrificial layers inside bulk silicon source wafers; 3) use of nanoscale-airflow-aware superstrate designs which pick circuit elements from the source wafers while maintaining lithographic precision to create a nano-meter precise assembly; 4) integration of an in-air overlay correction method, which additionally utilizes moire-based alignment metrology for nano-precise placement of circuit elements onto the product wafer to create a nano-meter precise assembly that is achieved by utilizing a variety of techniques including; and/or 5) a novel circuit design (EDA) schemes for high-mix, low-volume ASICs. Some embodiments may include other technical effects, advantages, and/or improvements as discussed herein.
[0096] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present technology. It will be apparent, however, to one skilled in the art that embodiments of the present technology may be practiced without some of these specific details.
[0097] The techniques introduced here can be embodied as special-purpose hardware (e.g., circuitry), as programmable circuitry appropriately programmed with software and/or firmware, or as a combination of special-purpose and programmable circuitry. Hence, embodiments may include a machine-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), magneto-optical disks, ROMs, random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or other type of media / machine-readable medium suitable for storing electronic instructions.
[0098] The phrases "in some embodiments," "according to some embodiments," "in the embodiments shown," "in other embodiments," and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one implementation of the present technology, and may be included in more than one implementation. In addition, such phrases do not necessarily refer to the same embodiments or different embodiments.
[0099] Various embodiments of the present technology relate to systems and methods for fabricating 3D ICs and Microscale Modular Assembled ASICs (M2A2), using nano-precise pick-and-place assembly techniques. Generic pick-and-place sequences for assembling 3D ICs and M2A2 in accordance with various embodiments are shown in Figs.1 and 2, respectively.
[00100] Fig. 1 illustrates an example of a pick-and-place sequence 100 for assembling 3D ICs that may be used in various embodiments of the present technology. As illustrated in Fig. 1, multiple different source wafers 110A-110N can include a variety of 2D dies that can be assembled using pick and place process 120 to create 3D IC 130. Various embodiments of the 3D IC process shown in Fig. 1 may be configured so that the assembly could happen in a face-to-face (F2F), face- to-back (F2B), back-to-face (B2F) or back-to-back (B2B) fashion. B2F, F2B and B2B stacked 3D ICs could later be connected, for instance, using through-silicon vias (TSVs). F2F stacked 3D ICs could be connected using inter-layer vias (ILVs) as illustrated in callout 140 showing an enlarged portion of 3D IC 130.
[00101] Fig. 2 illustrates an example of a pick-and-place sequence 200 for Microscale Modular Assembled ASIC (M2A2) that may be used in some embodiments of the present technology. As illustrated in the embodiments shown in Fig. 2, can include multiple source wafers 210A-210N each containing different prefabricated blocks (PFBs). In accordance with various embodiments, source wafers 210A-210N can include a plurality of PFBs on top of a sacrificial layer (e.g., Buried Oxide Layer). This is illustrated in cross section 215 of source wafer 210N.
[00102] Pick-and-Place superstrate can be designed to have programmable pickup locations allowing for the pick and place process 220 to pick up a source wafer and transfer one or more PFBs from the source wafer to the product substrate to create a customized assembled ASIC 230. As seen in callout 240 showing an enlarged cross sectional view of a portion 235 of ASIC 230, different PFBs 250 can be placed side by side in a desired order on the product substrate 260. [00103] For any generic pick-and-place assembly sequence, errors can be generated during various intermediate steps, all potentially contributing to the final overlay error. Table I provides a summary of these error sources.
[00104] Various embodiments provide for a variety of techniques to reduce and/or eliminate the above overlay error sources. Said overlay control techniques, described in subsequent sections, can be referred to as“overlay control architecture” for brevity. Unless otherwise stated, the methods disclosed could be applied to any of the applications explored herein.
J-FIL STEPPER BASED MACHINE DESIGN
[00105] Various embodiments of the present technology provide for new designs of a generic pick-and-place tool integrating design elements from a nano-imprint lithography stepper. Fig.3 shows a generic pick-and-place assembly sequence 300 and a nano-imprint lithography sequence 350 side-by-side, illustrating the parallels between them. For example, NIL/J-FIL uses a glass template while some embodiments of the present technology incorporate a pick-and-place stepper that uses a vacuum superstrate. In some embodiments, the pick-and-place stepper could essentially be a NIL template modified to have vacuum lines. NIL/J-FIL uses a UV-curable resist. Some embodiments of the present technology can incorporate a pick-and-place stepper that could use a UV-curable liquid. This could be similar in formulation to a UV-curable resist. NIL/J-FIL uses moiré-based overlay metrology, and MSCS based overlay correction. Overlay metrology in a pick-and-place stepper could be conducted using moiré-based metrology as well in various embodiments. NIL/J-FIL, after UV exposure, includes a separation step, where care is taken to not damage the cured resist. A pick-and-place stepper used in various embodiments of the present technology could use a similar controlled separation to pick up 2D-dies from their source substrates.
[00106] Fig.4 shows a pick-and-place stepper 400 modelled along the lines of a nano-imprint stepper. In the embodiments shown in Fig.4, stepper 400 can include a z-head assembly 410. Z-head assembly 410 can have one or more of the following features: movement z axes, inline overlay metrology, superstrate chuck, and vacuum and etchant routing. Z-head assembly 410 can be moveably mounted on granite bridge 420 on a granite base 430. Source wafer 440 and product wafer 450 can be positioned on wafer chuck assembly 460 allowing for pick and place by superstrate 470 located on z-head assembly 410. Some embodiments may include motion state 480 which both source and product substrate mounted on the same carriage.
[00107] Various embodiments of stepper 400 can have one or more wafer stages, which could be air bearing stages, roller bearing stages, or any other variety/combination of stages that are able to produce planar motion with nanometer precision, while being able to tolerate forces in the normal direction without losing precision. Figs.5A-5B illustrate examples of wafer stage configurations that may be used in some embodiments. In Fig. 5A, a single stage is shown with both source and product wafers on the same carriage. In Fig.5A, the source and product wafers 510 (and the chuck assemblies) can be included in a signal stage carriage. The cuck assemblies can share their (X, Y) degrees-of-freedom but can have independent theta, and higher order actuation. In case of a single stage, the stage could have a multitude of chucks to hold a variety of source and product wafers (Fig. 5A).
[00108] Fig. 5B illustrates embodiments with a multiple T-configuration stages. In a multiple T-configuration, source and product wafers 520 (and the chuck assemblies) can be positioned in the shape of the letter“T” (e.g., top row having three chuck assemblies with a single chuck assembly positioned directly below). In these embodiments, the (X, Y, theta) degrees of freedom can be independently controlled for each of the wafers 520. In some embodiments, additional higher degrees of freedom can be independently controlled. As such, the stepper 400 could have multiple independently moving stages, each with its own single chuck or multitude of chucks (Fig.5B).
[00109] The wafer chucks could have thermal actuator units (heating/cooling elements) embedded inside them. An example design of such a chuck is shown in Fig.6. The additional number of electrical wires and components needed to control the multitude of thermal actuators could be housed in an assembly on the stage carriage, along with an on-board multiplexer to reduce the number of wiring connections running through the stage wire track. The thermal actuators could not only be used to maintain the chuck at a desired constant temperature, but also be used to intentionally vary the thermal profile to attain a specific distortion profile as illustrated in heating cooling elements 610. In the cross-sectional view of the chuck at the bottom of Fig. 6, fins 620 separating the heating elements can be seen. The following reference, which is hereby incorporated by reference in its entirety for all purposes, describes such a feature: Ajay, Paras, et al. "Multifield sub-5 nm overlay in imprint lithography." Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 34.6 (2016): 061605.
[00110] In accordance with various embodiments, the wafer chucks could be made of transparent materials (in the relevant spectra), such as alumina and transparent SiC, to allow for metrology and adhesive-liquid curing from the bottom. Fig. 7 is an example of a topography-controlled thermally-actuated wafer chuck that may be used in one or more embodiments of the present technology. In the embodiments, illustrated in Fig. 7, wafer chuck 700 could further have arrays of embedded z-actuators (piezo-electric, voice coil based, etc.) to change the topography of the wafer during a pick-and-place step. In Fig.7, a bottom view 710 is shown along with a cross-sectional view 720 along line AA.
[00111] Wafer chuck 700 can include topographical control elements 730. As illustrated in the cross-sectional view 720, each of these elements can include thermal actuators 740, thin top section 750, topographical control elements 730 sandwiched in between thermal actuators 740 and a thick bottom section 760. As such, wafer chuck 700 can set the desired topography at the pin surface 770. For example, in some embodiments, topography errors (as well as in-plane distortions) could be sensed in an inline manner using chirped moiré alignment marks patterned on the wafers. Superstrate-substrate topography matching is important in pick-and- place assembly, more so than NIL, because during the pickup step, if 2D-dies/PFBs make contact with the superstrate at different instances, as they would if superstrate- substrate topography is not well matched, it could create localized regions where premature breakage of sacrificial tethers happens, increasing the likelihood of overlay loss. In addition, during the placement step, there is reduced scope for in- liquid alignment to correct overlay errors due to topography mismatch (or other sources, for that matter), since 2D-dies/PFBs are held to the superstrate over significantly smaller areas in comparison to NIL templates (which leads to reduced frictional resistance to sliding). To reduce the above eventualities, various embodiments correct both topography and overlay errors“in-air”.’
Claim 1 is directed towards a system claim. Sreenivasan ‘410 is capable of performing the method (or intended use) wherein a volatile lubricant is utilized during an alignment step. See MPEP 2114 (II. MANNER OF OPERATING THE DEVICE DOES NOT DIFFERENTIATE APPARATUS CLAIM FROM THE PRIOR ART "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original).) and MPEP 2115 (MATERIAL OR ARTICLE WORKED UPON DOES NOT LIMIT APPARATUS CLAIMS Claim analysis is highly fact-dependent. A claim is only limited by positively recited elements. Thus, "[i]nclusion of the material or article worked upon by a structure being claimed does not impart patentability to the claims." In re Otto, 312 F.2d 937, 136 USPQ 458, 459 (CCPA 1963); see also In re Young, 75 F.2d 996, 25 USPQ 69 (CCPA 1935).).
As to claim 2, Sreenivasan ‘410 is capable of being used with a material worked upon or method step wherein said first substrate is bonded to said second substrate using hybrid bonding. See MPEP 2114 and 2115, cited above.
As to claim 3, Sreenivasan ‘410 discloses further wherein at least one of said one or more deformable substrate chucks contains an array of piezo actuators (see paragraph 00110, disclosing “illustrated in Fig. 7, wafer chuck 700 could further have arrays of embedded z-actuators (piezo-electric, voice coil based, etc.) to change the topography of the wafer during a pick-and-place step”).
As to claim 4, Sreenivasan ‘410 is capable of being used with methods wherein said topography of said bonding surface on said first and second substrates is measured using one or more of the following: an air gage, a laser- based topography measurement technique and a tip-based topography measurement technique. See MPEP 2114 and 2115, cited above.
In any event, Sreenivasan ‘410 discloses further wherein said topography of said bonding surface on said first and second substrates is measured using one or more of the following: an air gage, a laser-based topography measurement technique (see paragraph 00095, disclosing “integration of an in-air overlay correction method, which additionally utilizes moire-based alignment metrology for nano-precise placement of circuit elements onto the product wafer to create a nano-meter precise assembly that is achieved by utilizing a variety of techniques”) and a tip-based topography measurement technique.
As to claim 5, Sreenivasan ‘410 discloses further wherein at least one of said one or more deformable substrate chucks contains actuators for overlay correction (see paragraph 00109, disclosing: “The thermal actuators could not only be used to maintain the chuck at a desired constant temperature, but also be used to intentionally vary the thermal profile to attain a specific distortion profile as illustrated in heating cooling elements 610” and paragraph 00111, disclosing: “In addition, during the placement step, there is reduced scope for in- liquid alignment to correct overlay errors due to topography mismatch (or other sources, for that matter), since 2D-dies/PFBs are held to the superstrate over significantly smaller areas in comparison to NIL templates (which leads to reduced frictional resistance to sliding). To reduce the above eventualities, various embodiments correct both topography and overlay errors“in-air’.”); the thermal actuators are shown to be used to provide overlay correction to the chuck.).
As to claim 6, Sreenivasan ‘410 discloses further wherein said actuators comprise thermal actuators (See paragraph 00109, disclosing “The thermal actuators could not only be used to maintain the chuck at a desired constant temperature, but also be used to intentionally vary the thermal profile to attain a specific distortion profile as illustrated in heating cooling elements 610”).
As to claim 7, the system of Sreenivasan ‘410 is capable of being used with methods wherein in-situ overlay metrology is performed using moir6-based techniques. See MPEP 2114 and 2115, cited above.
Additionally, Sreenivasan ‘410 discloses further wherein in-situ overlay metrology is performed using moire-based techniques (see paragraph 00095, disclosing “integration of an in-air overlay correction method, which additionally utilizes moire-based alignment metrology for nano-precise placement of circuit elements onto the product wafer to create a nano-meter precise assembly that is achieved by utilizing a variety of techniques”).
As to claim 8, the system of Sreenivasan ‘410 is capable of being used with methods wherein said in-situ overlay metrology utilizes IR wavelengths. See MPEP 2114 and 2115, cited above.
As to claim 9, the system of Sreenivasan ‘410 is capable of being used with methods wherein said lubricant is dispensed using an inkjet- based method. See MPEP 2114 and 2115, cited above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sreenivasan ‘410 (WO 2020051410 A1) in view of Molnar (US 6541381 B2).
As to claim 1, Sreenivasan ’410 discloses a system (Fig. 1, the system is shown.) for assembling a first substrate (Fig. 4, source wafer 440, see paragraph 00106, below to a second substrate (Fig. 4, product wafer 450, see paragraph 00106, below), comprising:
one or more deformable substrate chucks (Fig. 7, wafer chuck 700, see paragraph 00110 below) utilized to match a topography of a bonding surface on said first substrate to a topography of a bonding surface on said second substrate (see paragraph 00110, disclosing "Fig. 7 is an example of a topography-controlled thermally-actuated wafer chuck that may be used'‘in one or more embodiments of the present technology. In the embodiments, illustrated in Fig. 7, wafer chuck 700 could further have arrays of embedded z-actuators (piezo-electric, voice coil based, etc.) to change the topography of the wafer during a pick-and-place step"; See paragraph 00111, disclosing “As such, wafer chuck 700 can set the desired topography at the pin surface 770. For example, in some embodiments, topography errors (as well as in-plane distortions) could be sensed in an inline manner using chirped moiré alignment marks patterned on the wafers”).
See paragraphs 00095-111 below:
[0095] Various embodiments of the present technology provide for a wide range of technical effects, advantages, and/or improvements to fabrication systems and components. For example, various embodiments include one or more of the following technical effects, advantages, and/or improvements: 1) enable a number of applications which require nano-meter precise assembly of circuit elements (e.g., applications such as 3D integrated circuits, dies with super-lithographic form factors, hardware security and high-mix, low-volume ASICs, etc.); 2) a nano-meter precise assembly that is achieved by utilizing a variety of techniques including a novel process to produce buried sacrificial layers inside bulk silicon source wafers; 3) use of nanoscale-airflow-aware superstrate designs which pick circuit elements from the source wafers while maintaining lithographic precision to create a nano-meter precise assembly; 4) integration of an in-air overlay correction method, which additionally utilizes moire-based alignment metrology for nano-precise placement of circuit elements onto the product wafer to create a nano-meter precise assembly that is achieved by utilizing a variety of techniques including; and/or 5) a novel circuit design (EDA) schemes for high-mix, low-volume ASICs. Some embodiments may include other technical effects, advantages, and/or improvements as discussed herein.
[0096] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present technology. It will be apparent, however, to one skilled in the art that embodiments of the present technology may be practiced without some of these specific details.
[0097] The techniques introduced here can be embodied as special-purpose hardware (e.g., circuitry), as programmable circuitry appropriately programmed with software and/or firmware, or as a combination of special-purpose and programmable circuitry. Hence, embodiments may include a machine-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), magneto-optical disks, ROMs, random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or other type of media / machine-readable medium suitable for storing electronic instructions.
[0098] The phrases "in some embodiments," "according to some embodiments," "in the embodiments shown," "in other embodiments," and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one implementation of the present technology, and may be included in more than one implementation. In addition, such phrases do not necessarily refer to the same embodiments or different embodiments.
[0099] Various embodiments of the present technology relate to systems and methods for fabricating 3D ICs and Microscale Modular Assembled ASICs (M2A2), using nano-precise pick-and-place assembly techniques. Generic pick-and-place sequences for assembling 3D ICs and M2A2 in accordance with various embodiments are shown in Figs.1 and 2, respectively.
[00100] Fig. 1 illustrates an example of a pick-and-place sequence 100 for assembling 3D ICs that may be used in various embodiments of the present technology. As illustrated in Fig. 1, multiple different source wafers 110A-110N can include a variety of 2D dies that can be assembled using pick and place process 120 to create 3D IC 130. Various embodiments of the 3D IC process shown in Fig. 1 may be configured so that the assembly could happen in a face-to-face (F2F), face- to-back (F2B), back-to-face (B2F) or back-to-back (B2B) fashion. B2F, F2B and B2B stacked 3D ICs could later be connected, for instance, using through-silicon vias (TSVs). F2F stacked 3D ICs could be connected using inter-layer vias (ILVs) as illustrated in callout 140 showing an enlarged portion of 3D IC 130.
[00101] Fig. 2 illustrates an example of a pick-and-place sequence 200 for Microscale Modular Assembled ASIC (M2A2) that may be used in some embodiments of the present technology. As illustrated in the embodiments shown in Fig. 2, can include multiple source wafers 210A-210N each containing different prefabricated blocks (PFBs). In accordance with various embodiments, source wafers 210A-210N can include a plurality of PFBs on top of a sacrificial layer (e.g., Buried Oxide Layer). This is illustrated in cross section 215 of source wafer 210N.
[00102] Pick-and-Place superstrate can be designed to have programmable pickup locations allowing for the pick and place process 220 to pick up a source wafer and transfer one or more PFBs from the source wafer to the product substrate to create a customized assembled ASIC 230. As seen in callout 240 showing an enlarged cross sectional view of a portion 235 of ASIC 230, different PFBs 250 can be placed side by side in a desired order on the product substrate 260. [00103] For any generic pick-and-place assembly sequence, errors can be generated during various intermediate steps, all potentially contributing to the final overlay error. Table I provides a summary of these error sources.
[00104] Various embodiments provide for a variety of techniques to reduce and/or eliminate the above overlay error sources. Said overlay control techniques, described in subsequent sections, can be referred to as“overlay control architecture” for brevity. Unless otherwise stated, the methods disclosed could be applied to any of the applications explored herein.
J-FIL STEPPER BASED MACHINE DESIGN
[00105] Various embodiments of the present technology provide for new designs of a generic pick-and-place tool integrating design elements from a nano-imprint lithography stepper. Fig.3 shows a generic pick-and-place assembly sequence 300 and a nano-imprint lithography sequence 350 side-by-side, illustrating the parallels between them. For example, NIL/J-FIL uses a glass template while some embodiments of the present technology incorporate a pick-and-place stepper that uses a vacuum superstrate. In some embodiments, the pick-and-place stepper could essentially be a NIL template modified to have vacuum lines. NIL/J-FIL uses a UV-curable resist. Some embodiments of the present technology can incorporate a pick-and-place stepper that could use a UV-curable liquid. This could be similar in formulation to a UV-curable resist. NIL/J-FIL uses moiré-based overlay metrology, and MSCS based overlay correction. Overlay metrology in a pick-and-place stepper could be conducted using moiré-based metrology as well in various embodiments. NIL/J-FIL, after UV exposure, includes a separation step, where care is taken to not damage the cured resist. A pick-and-place stepper used in various embodiments of the present technology could use a similar controlled separation to pick up 2D-dies from their source substrates.
[00106] Fig.4 shows a pick-and-place stepper 400 modelled along the lines of a nano-imprint stepper. In the embodiments shown in Fig.4, stepper 400 can include a z-head assembly 410. Z-head assembly 410 can have one or more of the following features: movement z axes, inline overlay metrology, superstrate chuck, and vacuum and etchant routing. Z-head assembly 410 can be moveably mounted on granite bridge 420 on a granite base 430. Source wafer 440 and product wafer 450 can be positioned on wafer chuck assembly 460 allowing for pick and place by superstrate 470 located on z-head assembly 410. Some embodiments may include motion state 480 which both source and product substrate mounted on the same carriage.
[00107] Various embodiments of stepper 400 can have one or more wafer stages, which could be air bearing stages, roller bearing stages, or any other variety/combination of stages that are able to produce planar motion with nanometer precision, while being able to tolerate forces in the normal direction without losing precision. Figs.5A-5B illustrate examples of wafer stage configurations that may be used in some embodiments. In Fig. 5A, a single stage is shown with both source and product wafers on the same carriage. In Fig.5A, the source and product wafers 510 (and the chuck assemblies) can be included in a signal stage carriage. The cuck assemblies can share their (X, Y) degrees-of-freedom but can have independent theta, and higher order actuation. In case of a single stage, the stage could have a multitude of chucks to hold a variety of source and product wafers (Fig. 5A).
[00108] Fig. 5B illustrates embodiments with a multiple T-configuration stages. In a multiple T-configuration, source and product wafers 520 (and the chuck assemblies) can be positioned in the shape of the letter“T” (e.g., top row having three chuck assemblies with a single chuck assembly positioned directly below). In these embodiments, the (X, Y, theta) degrees of freedom can be independently controlled for each of the wafers 520. In some embodiments, additional higher degrees of freedom can be independently controlled. As such, the stepper 400 could have multiple independently moving stages, each with its own single chuck or multitude of chucks (Fig.5B).
[00109] The wafer chucks could have thermal actuator units (heating/cooling elements) embedded inside them. An example design of such a chuck is shown in Fig.6. The additional number of electrical wires and components needed to control the multitude of thermal actuators could be housed in an assembly on the stage carriage, along with an on-board multiplexer to reduce the number of wiring connections running through the stage wire track. The thermal actuators could not only be used to maintain the chuck at a desired constant temperature, but also be used to intentionally vary the thermal profile to attain a specific distortion profile as illustrated in heating cooling elements 610. In the cross-sectional view of the chuck at the bottom of Fig. 6, fins 620 separating the heating elements can be seen. The following reference, which is hereby incorporated by reference in its entirety for all purposes, describes such a feature: Ajay, Paras, et al. "Multifield sub-5 nm overlay in imprint lithography." Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 34.6 (2016): 061605.
[00110] In accordance with various embodiments, the wafer chucks could be made of transparent materials (in the relevant spectra), such as alumina and transparent SiC, to allow for metrology and adhesive-liquid curing from the bottom. Fig. 7 is an example of a topography-controlled thermally-actuated wafer chuck that may be used in one or more embodiments of the present technology. In the embodiments, illustrated in Fig. 7, wafer chuck 700 could further have arrays of embedded z-actuators (piezo-electric, voice coil based, etc.) to change the topography of the wafer during a pick-and-place step. In Fig.7, a bottom view 710 is shown along with a cross-sectional view 720 along line AA.
[00111] Wafer chuck 700 can include topographical control elements 730. As illustrated in the cross-sectional view 720, each of these elements can include thermal actuators 740, thin top section 750, topographical control elements 730 sandwiched in between thermal actuators 740 and a thick bottom section 760. As such, wafer chuck 700 can set the desired topography at the pin surface 770. For example, in some embodiments, topography errors (as well as in-plane distortions) could be sensed in an inline manner using chirped moiré alignment marks patterned on the wafers. Superstrate-substrate topography matching is important in pick-and- place assembly, more so than NIL, because during the pickup step, if 2D-dies/PFBs make contact with the superstrate at different instances, as they would if superstrate- substrate topography is not well matched, it could create localized regions where premature breakage of sacrificial tethers happens, increasing the likelihood of overlay loss. In addition, during the placement step, there is reduced scope for in- liquid alignment to correct overlay errors due to topography mismatch (or other sources, for that matter), since 2D-dies/PFBs are held to the superstrate over significantly smaller areas in comparison to NIL templates (which leads to reduced frictional resistance to sliding). To reduce the above eventualities, various embodiments correct both topography and overlay errors“in-air”.’
Claim 1 is directed towards a system claim. Sreenivasan ‘410 is capable of performing the method (or intended use) wherein a volatile lubricant is utilized during an alignment step. See MPEP 2114 and 2115, cited above.
In any event, Molnar discloses and makes obvious wherein a volatile lubricant is utilized during an alignment step. Molnar discloses a similar system (See Fig. 2, the system is shown.) comprising a first substrate (Fig. 2, workpiece 20, col. 2 ln. 43) and a second substrate (Fig. 2, finishing element 24, col. 2 In. 49), wherein a volatile lubricant (Fig. 2, lubricant 30, col. 7 In. 40; "As used herein, a lubricant is an agent that reduces friction between moving Surfaces. A hydrocarbon oil is a non limiting example.”, col. 5 In. 19-22;) is applied between the two substrates. See Figure 2, below:
PNG
media_image1.png
584
630
media_image1.png
Greyscale
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the filing of the invention to have combined the systems and teachings of Sreenivasan ‘410 and Molnar, in order to have reduced the amount of friction between the two substrates allowing alignment to be performed more accurately.
As to claim 2, Sreenivasan ‘410 is capable of being used with a material worked upon or method step wherein said first substrate is bonded to said second substrate using hybrid bonding. See MPEP 2114 and 2115, cited above.
As to claim 3, Sreenivasan ‘410 discloses further wherein at least one of said one or more deformable substrate chucks contains an array of piezo actuators (see paragraph 00110, disclosing “illustrated in Fig. 7, wafer chuck 700 could further have arrays of embedded z-actuators (piezo-electric, voice coil based, etc.) to change the topography of the wafer during a pick-and-place step”).
As to claim 4, Sreenivasan ‘410 is capable of being used with methods wherein said topography of said bonding surface on said first and second substrates is measured using one or more of the following: an air gage, a laser- based topography measurement technique and a tip-based topography measurement technique. See MPEP 2114 and 2115, cited above.
In any event, Sreenivasan ‘410 discloses further wherein said topography of said bonding surface on said first and second substrates is measured using one or more of the following: an air gage, a laser-based topography measurement technique (see paragraph 00095, disclosing “integration of an in-air overlay correction method, which additionally utilizes moire-based alignment metrology for nano-precise placement of circuit elements onto the product wafer to create a nano-meter precise assembly that is achieved by utilizing a variety of techniques”) and a tip-based topography measurement technique.
As to claim 5, Sreenivasan ‘410 discloses further wherein at least one of said one or more deformable substrate chucks contains actuators for overlay correction (see paragraph 00109, disclosing: “The thermal actuators could not only be used to maintain the chuck at a desired constant temperature, but also be used to intentionally vary the thermal profile to attain a specific distortion profile as illustrated in heating cooling elements 610” and paragraph 00111, disclosing: “In addition, during the placement step, there is reduced scope for in- liquid alignment to correct overlay errors due to topography mismatch (or other sources, for that matter), since 2D-dies/PFBs are held to the superstrate over significantly smaller areas in comparison to NIL templates (which leads to reduced frictional resistance to sliding). To reduce the above eventualities, various embodiments correct both topography and overlay errors“in-air’.”); the thermal actuators are shown to be used to provide overlay correction to the chuck.).
As to claim 6, Sreenivasan ‘410 discloses further wherein said actuators comprise thermal actuators (See paragraph 00109, disclosing “The thermal actuators could not only be used to maintain the chuck at a desired constant temperature, but also be used to intentionally vary the thermal profile to attain a specific distortion profile as illustrated in heating cooling elements 610”).
As to claim 7, the system of Sreenivasan ‘410 is capable of being used with methods wherein in-situ overlay metrology is performed using moir6-based techniques. See MPEP 2114 and 2115. Additionally, Sreenivasan ‘410 discloses further wherein in-situ overlay metrology is performed using moire-based techniques (see paragraph 00095, disclosing “integration of an in-air overlay correction method, which additionally utilizes moire- based alignment metrology for nano-precise placement of circuit elements onto the product wafer to create a nano-meter precise assembly that is achieved by utilizing a variety of techniques”).
As to claim 8, the system of Sreenivasan ‘410 is capable of being used with methods wherein said in-situ overlay metrology utilizes IR wavelengths. See MPEP 2114 and 2115, cited above.
As to claim 9, the system of Sreenivasan ‘410 is capable of being used with methods wherein said lubricant is dispensed using an inkjet- based method. See MPEP 2114 and 2115, cited above.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sreenivasan ‘410 (WO 2020051410 A1) in view of Sreenivasan ‘451 (WO 2018119451 A1)
As per claim 10, Sreenivasan ‘410 discloses an apparatus (Fig. 1, the system is shown.), comprising: a substrate (Fig. 4, source wafer 440, see paragraph 00106, cited above) with dies (see paragraph 00100, disclosing “As illustrated in Fig. 1, multiple different source wafers 110A-110N can include a variety of 2D dies that can be assembled using pick and place process 120 to create 3D IC 130”) assembled on top; a coating of a transparent material on said substrate (see paragraph 00110, disclosing “the wafer chucks could be made of transparent materials (in the relevant spectra)”); and ; ; adhesive drops (see paragraph 00110, disclosing “such as alumina and transparent SiC, to allow for metrology and adhesive-liquid curing from the bottom”) between said dies and said transparent material, (wherein said adhesive drops are inkjetted on said transparent material]; wherein said transparent material allows light to be coupled in from a substrate periphery (see paragraph 00110, disclosing “such as alumina and transparent SiC, to allow for metrology and adhesive-liquid curing from the bottom”).
Sreenivasan ‘410 does not disclose wherein said adhesive drops are inkjetted on said transparent material and wherein said drops are staggered to allow said dies to be exposed to said coupled in light.
However, Sreenivasan ‘451 discloses a similar system (Fig. 1, the system is shown.) teaching applying an adhesive using an inkjet (see paragraph 00117, disclosing “In step 2002, just before the placement step, an inkjet dispenses the second part of the adhesive 2103 at the specific location where elements 202 will be placed as shown in Figures 21A-21B”), wherein the drops are provided in a staggered arrangement (see paragraph 00120, disclosing “An alternative to the spin coating technique discussed above is to use two inkjets for concurrently dispensing the two components of the two-part adhesive. The inkjets could be programmed to dispense the two components in such a way that there is at least a partial overlap between the two drops. This overlap could happen prior to the assembly of the element, or the element assembly step could urge the drops to mix with each other.”)
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have utilized wherein said adhesive drops are inkjetted on said transparent material and wherein said drops are staggered to allow said dies to be exposed to said coupled in light as suggested by combining Sreenivasan ‘451 with Sreenivasan ‘410 in order to have provided a more efficient way of coupling substrates.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GEORGE R KOCH whose telephone number is (571) 272-5807. The examiner can also be reached by E-mail at george.koch@uspto.gov if the applicant grants written authorization for e-mails. Authorization can be granted by filling out the USPTO Automated Interview Request (AIR) Form.
The examiner can normally be reached M-F 10-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PHILIP C TUCKER can be reached at (571)272-1095. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GEORGE R KOCH/Primary Examiner, Art Unit 1745
GRK