DETAILED ACTION
Claims 1-5, 7-10, 12-15, 27-32, and 34 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 U.S.C. § 101
35 U.S.C. § 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
The invention, as taught in Claims 1-5, 7-10, 12-15, 27-32, and 34, is directed to “mental steps” and “mathematical steps” without significantly more.
The claims recite:
• determining, according to first training data for a current training round, a first target parameter
• first network parameter required by an embedding of the first training data
• determining a remaining storage slot in the target memory according to a first mapping relationship between a storage slot of the target memory and a network parameter
• adjusts the first network parameter according to the first training data
Claim 1
Step 1 inquiry: Does this claim fall within a statutory category?
The preamble of the claim recites “1. A method of training a deep learning model, comprising…” Therefore, it is a “method” (or “process”), which is a statutory category of invention. Therefore, the answer to the inquiry is: “YES.”
Step 2A (Prong One) inquiry:
Are there limitations in Claim 1 that recite abstract ideas?
YES. The following limitations in Claim 1 recite abstract ideas that fall within at least one of the groupings of abstract ideas enumerated in the 2019 PEG. Specifically, they are “mental steps” and “mathematical steps”:
• determining, according to first training data for a current training round, a first target parameter
• first network parameter required by an embedding of the first training data
• determining a remaining storage slot in the target memory according to a first mapping relationship between a storage slot of the target memory and a network parameter
• adjusts the first network parameter according to the first training data
Step 2A (Prong Two) inquiry:
Are there additional elements or a combination of elements in the claim that apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that it is more than a drafting effort designed to monopolize the exception?
Applicant’s claims contain the following “additional elements”:
(1) A target processor
(2) A target memory
(3) A deep learning model
(4) A writing, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory so that a computing core contained in the target processor
(1) A “target processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
This “target processor” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(2) A “target memory” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “target memory” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(3) A “deep learning model” is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f)(2) recites in part:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process.
Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
TLI Communications provides an example of a claim invoking computers and other machinery merely as a tool to perform an existing process. The court stated that the claims describe steps of recording, administration and archiving of digital images, and found them to be directed to the abstract idea of classifying and storing digital images in an organized manner. 823 F.3d at 612, 118 USPQ2d at 1747. The court then turned to the additional elements of performing these functions using a telephone unit and a server and noted that these elements were being used in their ordinary capacity (i.e., the telephone unit is used to make calls and operate as a digital camera including compressing images and transmitting those images, and the server simply receives data, extracts classification information from the received data, and stores the digital images based on the extracted information). 823 F.3d at 612-13, 118 USPQ2d at 1747-48. In other words, the claims invoked the telephone unit and server merely as tools to execute the abstract idea. Thus, the court found that the additional elements did not add significantly more to the abstract idea because they were simply applying the abstract idea on a telephone network without any recitation of details of how to carry out the abstract idea.
This “deep learning model” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(4) A “writing, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory so that a computing core contained in the target processor” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “writing, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory so that a computing core contained in the target processor” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
The answer to the inquiry is “NO”, no additional elements integrate the claimed abstract idea into a practical application.
Step 2B inquiry:
Does the claim provide an inventive concept, i.e., does the claim recite additional element(s) or a combination of elements that amount to significantly more than the judicial exception in the claim?
Applicant’s claims contain the following “additional elements”:
(1) A target processor
(2) A target memory
(3) A deep learning model
(4) A writing, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory so that a computing core contained in the target processor
(1) A “target processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2016.05(f) recites:
2106.05(f) Mere Instructions To Apply An Exception [R-10.2019]
Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”).
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process.
Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(2) A “target memory” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(3) A “deep learning model” is a broad term which is described at a high level.
Further, since the “deep learning model” is well understood, routine and conventional, simply using the “deep learning model” to produce a result is not eligible. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
Therefore, simply using the “deep learning model” to produce a result is not eligible.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(4) A “writing, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory so that a computing core contained in the target processor” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
Therefore, the answer to the inquiry is “NO”, no additional elements provide an inventive concept that is significantly more than the claimed abstract ideas the claimed abstract idea into a practical application.
Claim 1 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 2
Claim 2 recites:
2. The method of claim 1, further comprising:
allocating a storage slot in the remaining storage slot for the first target parameter in response to the remaining storage slot meeting the storage requirement of the first target parameter; and
updating the first mapping relationship according to an identification information of the storage slot allocated for the first target parameter and an identification information of the first target parameter,
wherein the writing the first target parameter into the target memory comprises: writing the first target parameter into the storage slot allocated for the first target parameter.
Applicant’s Claim 2 merely teaches generic memory allocation, updating of data (mapping relationship), and the writing operation for a mathematical parameter. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 2 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 3
Claim 3 recites:
3. The method of claim 1, wherein the determining a first target parameter required to be written into a target memory in a first network parameter required by an embedding of the first training data comprises:
determining the first network parameter required by the embedding of the first training data;
performing a de-duplication on the first network parameter so as to obtain a de-duplicated network parameter; and
determining, according to the first mapping relationship and an identification information of the de-duplicated network parameter, a network parameter not stored in the target memory in the de-duplicated network parameter as the first target parameter.
Applicant’s Claim 3 merely teaches determination of a network parameter, removing of duplicate parameters, and determination of a network parameter. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 3 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 4
Claim 4 recites:
4. The method of claim 1, further comprising:
determining a transferable network parameter in a network parameter stored in the target memory, in response to the remaining storage slot not meeting the storage requirement of the first target parameter;
transferring the transferable network parameter from the target memory to an internal memory; and
writing the first target parameter into the target memory in response to the transferable network parameter being transferred to the internal memory.
Applicant’s Claim 4 merely teaches determination of a transferable network parameter, transferring the mathematical parameter between memories, and writing to a generic memory. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 4 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 5
Claim 5 recites:
5. The method of claim 4, wherein the determining a transferable network parameter in network parameters stored in the target memory comprises:
determining, according to a second mapping relationship between a storage slot of the target memory and a parameter state of a network parameter stored in the storage slot, a network parameter of which the parameter state is a target state as the transferable network parameter,
wherein the parameter state comprises at least one of a reference state or a number of uses; the target state comprises at least one of: the reference state is not-referenced, or the number of uses is less than a number threshold;
the method further comprises:
allocating a remaining storage slot in the target memory for the first target parameter in response to the transferable network parameter being transferred to the internal memory; and
updating the second mapping relationship according to the storage slot allocated for the first target parameter and a storage slot in which parameters other than the first target parameter in the first network parameter are located, so as to update the parameter state of the first network parameter.
Applicant’s Claim 5 merely teaches determination of a network parameter, generic allocation of memory, and the updating of relationship data. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 5 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 7
Claim 7 recites:
7. The method of claim 4, wherein the transferring the transferable network parameter from the target memory to an internal memory comprises:
writing the transferable network parameter into a hard disk storage via the internal memory in response to a remaining storage space of the internal memory being less than a space threshold.
Applicant’s Claim 7 merely teaches the generic writing of data. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 7 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 8
Claim 8 recites:
8. The method of claim 1, further comprising:
determining, according to second training data for a next training round, a second target parameter required to be written into the target memory in a second network parameter required by an embedding of second training data, in response to the computing core training the first network parameter according to the first training data;
determining a remaining storage slot in the target memory according to the first mapping relationship between the storage slot of the target memory and the network parameter; and
writing the second target parameter into the target memory in response to the remaining storage slot meeting a storage requirement of the second target parameter.
Applicant’s Claim 8 merely teaches determining a parameter, determining a memory location, and writing to the generic memory location. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 8 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 9
Claim 9 recites:
9. The method of claim 1, wherein the target processor comprises a plurality of processors; the first training data comprises a plurality of batches of data respectively corresponding to the plurality of processors; and the writing the first target parameter into the target memory comprises:
for each processor in the plurality of processors, determining a specified parameter required by an embedding of a batch of data corresponding to the processor in the first target parameter;
replacing parameters other than the specified parameter in the first target parameter by a predetermined parameter value, so as to obtain a parameter to be written for the processor; and
writing the parameter to be written into the target memory contained in the processor, so that the computing core contained in the processor trains the specified parameter according to the batch of data corresponding to the processor.
Applicant’s Claim 9 merely teaches determination of a parameter, replacement of parameters, and writing to a generic memory. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 9 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 10
Claim 10 recites:
10. The method of claim 9, wherein for each batch of data in the plurality of batches of data, a number of network parameters required by the embedding of the batch of data is related to a storage capacity of the target memory in the processor corresponding to the batch of data.
Applicant’s Claim 10 merely teaches data relationships. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 10 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 12
Step 1 inquiry: Does this claim fall within a statutory category?
The preamble of the claim recites “12. A method of training a deep learning model, comprising…” Therefore, it is a “method” (or “process”), which is a statutory category of invention. Therefore, the answer to the inquiry is: “YES.”
Step 2A (Prong One) inquiry:
Are there limitations in Claim 12 that recite abstract ideas?
YES. The following limitations in Claim 12 recite abstract ideas that fall within at least one of the groupings of abstract ideas enumerated in the 2019 PEG. Specifically, they are “mental steps” and “mathematical steps”:
• determining,… according to first training data for a current training round, a first target parameter
• first network parameter required by an embedding of the first training data
• determining,…, a remaining storage slot in the target memory according to a first mapping relationship between a storage slot of the target memory and a network parameter
• adjusting,… in response to receiving the training task information, the first network parameter according to the first training data
Step 2A (Prong Two) inquiry:
Are there additional elements or a combination of elements in the claim that apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that it is more than a drafting effort designed to monopolize the exception?
Applicant’s claims contain the following “additional elements”:
(1) A “first processor”/ “second processor”/ “computing core of the second processor”
(2) A deep learning model
(3) A “written into a target memory”/ “target memory is a memory contained in a second processor”/ “writing, by using the first processor in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory”
(4) A transmitting a training task information to the second processor
(1) A “first processor”/ “second processor”/ “computing core of the second processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
This “first processor”/ “second processor”/ “computing core of the second processor” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(2) A “deep learning model” is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f)(2) recites in part:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process.
Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
TLI Communications provides an example of a claim invoking computers and other machinery merely as a tool to perform an existing process. The court stated that the claims describe steps of recording, administration and archiving of digital images, and found them to be directed to the abstract idea of classifying and storing digital images in an organized manner. 823 F.3d at 612, 118 USPQ2d at 1747. The court then turned to the additional elements of performing these functions using a telephone unit and a server and noted that these elements were being used in their ordinary capacity (i.e., the telephone unit is used to make calls and operate as a digital camera including compressing images and transmitting those images, and the server simply receives data, extracts classification information from the received data, and stores the digital images based on the extracted information). 823 F.3d at 612-13, 118 USPQ2d at 1747-48. In other words, the claims invoked the telephone unit and server merely as tools to execute the abstract idea. Thus, the court found that the additional elements did not add significantly more to the abstract idea because they were simply applying the abstract idea on a telephone network without any recitation of details of how to carry out the abstract idea.
This “deep learning model” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(3) A “written into a target memory”/ “target memory is a memory contained in a second processor”/ “writing, by using the first processor in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “written into a target memory”/ “target memory is a memory contained in a second processor”/ “writing, by using the first processor in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(4) A “transmitting a training task information to the second processor” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “transmitting a training task information to the second processor” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
The answer to the inquiry is “NO”, no additional elements integrate the claimed abstract idea into a practical application.
Step 2B inquiry:
Does the claim provide an inventive concept, i.e., does the claim recite additional element(s) or a combination of elements that amount to significantly more than the judicial exception in the claim?
Applicant’s claims contain the following “additional elements”:
(1) A “first processor”/ “second processor”/ “computing core of the second processor”
(2) A deep learning model
(3) A written into a target memory”/ “target memory is a memory contained in a second processor”/ “writing, by using the first processor in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory
(4) A transmitting a training task information to the second processor
(1) A “first processor”/ “second processor”/ “computing core of the second processor” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2016.05(f) recites:
2106.05(f) Mere Instructions To Apply An Exception [R-10.2019]
Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”).
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process.
Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(2) A “deep learning model” is a broad term which is described at a high level.
Further, since the “deep learning model” is well understood, routine and conventional, simply using the “deep learning model” to produce a result is not eligible. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
Therefore, simply using the “deep learning model” to produce a result is not eligible.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(3) A “written into a target memory”/ “target memory is a memory contained in a second processor”/ “writing, by using the first processor in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(4) A “transmitting a training task information to the second processor” is a broad term which is described at a high level. M.P.E.P. § 2106.05(d)(II) recites:
The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity.
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); …
Further, M.P.E.P. § 2106.05(d)(I)(2) recites in part:
2. A factual determination is required to support a conclusion that an additional element (or combination of additional elements) is well-understood, routine, conventional activity. Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018). However, this does not mean that a prior art search is necessary to resolve this inquiry. Instead, examiners should rely on what the courts have recognized, or those in the art would recognize, as elements that are well-understood, routine, conventional activity in the relevant field when making the required determination. For example, in many instances, the specification of the application may indicate that additional elements are well-known or conventional. See, e.g., Intellectual Ventures v. Symantec, 838 F.3d at 1317; 120 USPQ2d at 1359 ("The written description is particularly useful in determining what is well-known or conventional"); Internet Patents Corp. v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1418 (Fed. Cir. 2015) (relying on specification’s description of additional elements as "well-known", "common" and "conventional"); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 614, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (Specification described additional elements as "either performing basic computer functions such as sending and receiving data, or performing functions ‘known’ in the art.").
Merely using the conventional computer to receive data is well known, understood, and conventional. Thus, it adds nothing significantly more to the judicial exception.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
Therefore, the answer to the inquiry is “NO”, no additional elements provide an inventive concept that is significantly more than the claimed abstract ideas the claimed abstract idea into a practical application.
Claim 12 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 13
Claim 13 recites:
13. The method of claim 12, wherein the second processor comprises a plurality of processors; the first training data comprises a plurality of batches of data respectively corresponding to the plurality of processors; the writing the first target parameter into the target memory comprises:
for each processor in the plurality of processors, determining a specified parameter required by an embedding of a batch of data corresponding to the processor in the first target parameter;
replacing parameters other than the specified parameter in the first target parameter by a predetermined parameter, so as to obtain a parameter to be written for the processor; and
writing the parameter to be written into the target memory contained in the processor.
Applicant’s Claim 13 merely teaches determination of a parameter, replacement of parameters, and writing to a generic memory. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 13 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 14
Claim 14 recites:
14. The method of claim 13, wherein the plurality of processors are connected via Cache Coherency Interconnect Protocol to form a processor ring; the adjusting the first network parameter according to the first training data comprises:
performing, by the computing core of each processor in the plurality of processors, a forward calculation and a backward calculation according to the specified parameter and a batch of data corresponding to the processor, so as to obtain gradient data for the first network parameter; and
adjusting, by the processor, the first network parameter by using an Allreduce algorithm according to the gradient data for the first network parameter, the gradient data obtained by other processors in the plurality of processors, and the storage slot in which the first network parameter is located.
Applicant’s Claim 14 merely teaches performance of unspecified calculations and the adjustment of parameters. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 14 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 15
Claim 15 recites:
15. The method of claim 12, wherein the second processor comprises an artificial intelligence chip; and the artificial intelligence chip comprises a Kunlunxin2 chip.
Applicant’s Claim 15 merely teaches the use of an AI chip. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 15 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 27
Step 1 inquiry: Does this claim fall within a statutory category?
The preamble of the claim recites “27. A system of training a deep learning model, comprising a first processor and a second processor, wherein the second processor comprises a target memory and a computing core…” Therefore, it is a “system” (or “apparatus”), which is a statutory category of invention. Therefore, the answer to the inquiry is: “YES.”
Step 2A (Prong One) inquiry:
Are there limitations in Claim 27 that recite abstract ideas?
YES. The following limitations in Claim 27 recite abstract ideas that fall within at least one of the groupings of abstract ideas enumerated in the 2019 PEG. Specifically, they are “mental steps” and “mathematical steps”:
• determine, according to first training data for a current training round, a first target parameter
• first network parameter required by an embedding of the first training data
• determine a remaining storage slot in the target memory according to a first mapping relationship between a storage slot of the target memory and a network parameter
• adjust,…in response to receiving the training task information, the first network parameter according to the first training data
Step 2A (Prong Two) inquiry:
Are there additional elements or a combination of elements in the claim that apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that it is more than a drafting effort designed to monopolize the exception?
Applicant’s claims contain the following “additional elements”:
(1) A “first processor”/ “a second processor”/ “computing core”
(2) A “target memory”
(3) A “deep learning model”
(4) A write, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory
(5) A transmit a training task information to the second processor
(1) A “first processor”/ “a second processor”/ “computing core” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
This “first processor”/ “a second processor”/ “computing core” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(2) A “target memory” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “target memory” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(3) A “deep learning model” is a broad term which is described at a high level. M.P.E.P. § 2106.05 (f)(2) recites in part:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process.
Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
TLI Communications provides an example of a claim invoking computers and other machinery merely as a tool to perform an existing process. The court stated that the claims describe steps of recording, administration and archiving of digital images, and found them to be directed to the abstract idea of classifying and storing digital images in an organized manner. 823 F.3d at 612, 118 USPQ2d at 1747. The court then turned to the additional elements of performing these functions using a telephone unit and a server and noted that these elements were being used in their ordinary capacity (i.e., the telephone unit is used to make calls and operate as a digital camera including compressing images and transmitting those images, and the server simply receives data, extracts classification information from the received data, and stores the digital images based on the extracted information). 823 F.3d at 612-13, 118 USPQ2d at 1747-48. In other words, the claims invoked the telephone unit and server merely as tools to execute the abstract idea. Thus, the court found that the additional elements did not add significantly more to the abstract idea because they were simply applying the abstract idea on a telephone network without any recitation of details of how to carry out the abstract idea.
This “deep learning model” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(4) A “write, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “write, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
(5) A “transmit a training task information to the second processor” is a broad term which is described at a high level. M.P.E.P. § 2106.05(g) recites:
2106.05(g) Insignificant Extra-Solution Activity [R-10.2019]
Another consideration when determining whether a claim integrates the judicial exception into a practical application in Step 2A Prong Two or recites significantly more in Step 2B is whether the additional elements add more than insignificant extra-solution activity to the judicial exception. The term “extra-solution activity” can be understood as activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim. Extra-solution activity includes both pre-solution and post-solution activity.
This “transmit a training task information to the second processor” limitation does not integrate the additional element into a practical application and represents “insignificant extra-solution activity”. (See, M.P.E.P. § 2106.05(I)(A)).
The answer to the inquiry is “NO”, no additional elements integrate the claimed abstract idea into a practical application.
Step 2B inquiry:
Does the claim provide an inventive concept, i.e., does the claim recite additional element(s) or a combination of elements that amount to significantly more than the judicial exception in the claim?
Applicant’s claims contain the following “additional elements”:
(1) A “first processor”/ “a second processor”/ “computing core”
(2) A target memory
(3) A deep learning model
(4) A write, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory
(5) A transmit a training task information to the second processor
(1) A “first processor”/ “a second processor”/ “computing core” is a broad term which is described at a high level and includes general purpose computers. M.P.E.P. § 2016.05(f) recites:
2106.05(f) Mere Instructions To Apply An Exception [R-10.2019]
Another consideration when determining whether a claim integrates a judicial exception into a practical application in Step 2A Prong Two or recites significantly more than a judicial exception in Step 2B is whether the additional elements amount to more than a recitation of the words “apply it” (or an equivalent) or are more than mere instructions to implement an abstract idea or other exception on a computer. As explained by the Supreme Court, in order to make a claim directed to a judicial exception patent-eligible, the additional element or combination of elements must do “‘more than simply stat[e] the [judicial exception] while adding the words ‘apply it’”. Alice Corp. v. CLS Bank, 573 U.S. 208, 221, 110 USPQ2d 1976, 1982-83 (2014) (quoting Mayo Collaborative Servs. V. Prometheus Labs., Inc., 566 U.S. 66, 72, 101 USPQ2d 1961, 1965). Thus, for example, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible. Alice Corp., 573 U.S. at 223, 110 USPQ2d at 1983. See also 573 U.S. at 224, 110 USPQ2d at 1984 (warning against a § 101 analysis that turns on “the draftsman’s art”).
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process.
Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(2) A “target memory” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(3) A “deep learning model” is a broad term which is described at a high level.
Further, since the “deep learning model” is well understood, routine and conventional, simply using the “deep learning model” to produce a result is not eligible. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Further, M.P.E.P. § 2106.05(f)(2) recites:
(2) Whether the claim invokes computers or other machinery merely as a tool to perform an existing process. Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Similarly, “claiming the improved speed or efficiency inherent with applying the abstract idea on a computer” does not integrate a judicial exception into a practical application or provide an inventive concept. Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015). In contrast, a claim that purports to improve computer capabilities or to improve an existing technology may integrate a judicial exception into a practical application or provide significantly more. McRO, Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314-15, 120 USPQ2d 1091, 1101-02 (Fed. Cir. 2016); Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1688-89 (Fed. Cir. 2016). See MPEP §§ 2106.04(d)(1) and 2106.05(a) for a discussion of improvements to the functioning of a computer or to another technology or technical field.
Therefore, simply using the “deep learning model” to produce a result is not eligible.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(4) A “write, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory” is a broad term which is described at a high level. M.P.E.P. § 2106.05(f) recites:
For claim limitations that do not amount to more than a recitation of the words “apply it” (or an equivalent), such as mere instructions to implement an abstract idea on a computer, examiners should explain why they do not meaningfully limit the claim in an eligibility rejection. For example, an examiner could explain that implementing an abstract idea on a generic computer, does not integrate the abstract idea into a practical application in Step 2A Prong Two…
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
(5) A “transmit a training task information to the second processor” is a broad term which is described at a high level. M.P.E.P. § 2106.05(d)(II) recites:
The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity.
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); …
Further, M.P.E.P. § 2106.05(d)(I)(2) recites in part:
2. A factual determination is required to support a conclusion that an additional element (or combination of additional elements) is well-understood, routine, conventional activity. Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018). However, this does not mean that a prior art search is necessary to resolve this inquiry. Instead, examiners should rely on what the courts have recognized, or those in the art would recognize, as elements that are well-understood, routine, conventional activity in the relevant field when making the required determination. For example, in many instances, the specification of the application may indicate that additional elements are well-known or conventional. See, e.g., Intellectual Ventures v. Symantec, 838 F.3d at 1317; 120 USPQ2d at 1359 ("The written description is particularly useful in determining what is well-known or conventional"); Internet Patents Corp. v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1418 (Fed. Cir. 2015) (relying on specification’s description of additional elements as "well-known", "common" and "conventional"); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 614, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (Specification described additional elements as "either performing basic computer functions such as sending and receiving data, or performing functions ‘known’ in the art.").
Merely using the conventional computer to receive data is well known, understood, and conventional. Thus, it adds nothing significantly more to the judicial exception.
Therefore, the claim as a whole does not amount to significantly more than the exception itself (i.e., there is no inventive concept in the claim). (See, M.P.E.P. § 2106.05(II)).
Therefore, the answer to the inquiry is “NO”, no additional elements provide an inventive concept that is significantly more than the claimed abstract ideas the claimed abstract idea into a practical application.
Claim 27 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 28
Claim 28 recites:
28. The system of claim 27, wherein the second processor comprises a plurality of processors; the first training data comprises a plurality of batches of data respectively corresponding to the plurality of processors; the first processor is configured to write the first target parameter into the target memory by:
for each processor in the plurality of processors, determining a specified parameter required by an embedding of a batch of data corresponding to the processor in the first target parameter;
replacing parameters other than the specified parameter in the first target parameter by a predetermined parameter, so as to obtain a parameter to be written for the processor; and
writing the parameter to be written into the target memory contained in the processor.
Applicant’s Claim 28 merely teaches determination of a parameter, replacement of parameters, and writing to a generic memory. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 28 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 29
Claim 29 recites:
29. The system of claim 28, wherein the plurality of processors are connected via Cache Coherency Interconnect Protocol to form a processor ring; each processor is configured to adjust the first network parameter by:
performing, by the computing core, a forward calculation and a backward calculation according to the specified parameter and a batch of data corresponding to the processor, so as to obtain gradient data for the first network parameter; and
adjusting the first network parameter by using an Allreduce algorithm according to the gradient data for the first network parameter, the gradient data obtained by other processors in the plurality of processors, and the storage slot in which the first network parameter is located.
Applicant’s Claim 29 merely teaches performance of unspecified calculations and the adjustment of parameters. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 29 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 30
Claim 30 recites:
30. The system of claim 27, wherein the second processor comprises an artificial intelligence chip; and the artificial intelligence chip comprises a Kunlunxin2 chip.
Applicant’s Claim 30 merely teaches the use of an AI chip. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 30 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 31
Claim 31 recites:
31. An electronic device, comprising:
at least one processor; and
a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to, when executed by the at least one processor, cause the at least one processor to implement the method of claim 12.
Applicant’s Claim 31 merely teaches a generic processor coupled to a memory. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 31 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 32
Claim 32 recites:
32. A non-transitory computer-readable storage medium having computer instructions therein, wherein the computer instructions are configured to cause a computer to implement the method of claim 12.
Applicant’s Claim 32 merely teaches a generic computer readable medium. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 32 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim 34
Claim 34 recites:
34. An electronic device, comprising:
at least one processor, and
a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to, when executed by the at least one processor, cause the at least one processor to implement the method of claim 1.
Applicant’s Claim 34 merely teaches a generic processor coupled to a memory. It does not integrate the abstract idea to a practical application, nor is it anything significantly more than the abstract idea. (See, 2106.05(a)(II).)
Claim 34 is, therefore, NOT ELIGIBLE subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 U.S.C. § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 8, 12, 27, 31, 32, and 34 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Gerogiannis, et al., Deep Reinforcement Learning Acceleration for Real-Time Edge Computing Mixed Integer Programming Problems, IEEE Access, Vol. 10, 28 JAN 2022, pp. 18526-18543, in its entirety. Specifically:
Claim 1
Claim 1’s “determining, according to first training data for a current training round, a first target parameter required to be written into a target memory in a first network parameter required by an embedding of the first training data, wherein the target memory is a memory contained in a target processor” is anticipated by Gerogiannis, et al., page 18530, left column, first full paragraph, where it recites:
The designed Accelerator is suitable for algorithms employing Batch Gradient Descent (BGD) [21] as the learning algorithm, according to which the gradient values for a batch of training samples are accumulated. The learning update rule is given by
***
where dΘbatch denotes the sum of the gradient values for all the samples in the batch, Θ is the parameter to be updated (the network's weights) and a is the learning rate.
Note that the network weights are the “target parameter” to be stored.
Claim 1’s “determining a remaining storage slot in the target memory according to a first mapping relationship between a storage slot of the target memory and a network parameter; and” is anticipated by Gerogiannis, et al., page 18532, left column, first paragraph, where it recites:
In Fig. 7 the core blocks of the architecture are presented. There are two core modules, namely the Inference and Training Modules which operate in parallel. Since both operations are using the same weights, to avoid memory conflicts there are two weight memories one for inference and one for training. Additionally, since the training module is split into pipeline stages which operate simultaneously and both the FP and BP training computations access the same weights, the training weights memory consists of two replicas. There are two additional memories, the first of which accumulates the gradients dWi as described in sub-section IV.A. The role of the Updated Weights Memory (which also contains two replicas) will become clearer in sub-section B. All memory blocks, including the Replay Memory are implemented using on-chip Dual Port Block RAMs (BRAMs). Although the total memory requirements are increased by a factor of 3 in comparison with a serial CPU based implementation (serial execution of inference and training with no pipeline stages in training) which would use a single weight memory and a memory for accumulating the gradient values, the number of weights in the typical NN configurations for the applications of interest does not impose high memory requirements. Thus, all the weight memory blocks in our designed architecture can be effectively implemented and partitioned without utilizing a large percentage of the FPGA memory resources.
Claim 1’s “writing, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory so that a computing core contained in the target processor adjusts the first network parameter according to the first training data.” is anticipated by Gerogiannis, et al., page 18534, left column, last bullet point, where it recites:
• We assume that at an arbitrary timestep t all the weights are simultaneously updated. Since the pipeline is constantly fed with training samples and calculates the corresponding NN's gradient values, the calculations of the samples that were in the first three pipeline stages (FP stages) prior to the weights update that are now stored in the pipeline registers were conducted using the old weight values. However, in the following timesteps when those calculations propagate to the BP and GC stages the corresponding calculations will be conducted using the updated weight values.
Claim 2
Claim 2’s “allocating (e.g. partitioning) a storage slot in the remaining storage slot for the first target parameter in response to the remaining storage slot meeting the storage requirement of the first target parameter; and” is anticipated by Gerogiannis, et al., page 18532, left column, last full paragraph, where it recites:
When designing using High Level Synthesis, the tool will not treat functions that access the same memory locations as concurrent and therefore will not synthesize hardware modules operating in parallel. Thus, the usage of distinct memories which are appropriately partitioned is obligatory for the synthesis of parallel logic from HLS.
Claim 2’s “updating the first mapping relationship according to an identification information of the storage slot allocated for the first target parameter and an identification information of the first target parameter” is anticipated by Gerogiannis, et al., page 18532, left column, last full paragraph, where it recites:
When designing using High Level Synthesis, the tool will not treat functions that access the same memory locations as concurrent and therefore will not synthesize hardware modules operating in parallel. Thus, the usage of distinct memories which are appropriately partitioned is obligatory for the synthesis of parallel logic from HLS.
Claim 2’s “wherein the writing the first target parameter into the target memory comprises: writing the first target parameter into the storage slot allocated for the first target parameter.” is anticipated by Gerogiannis, et al., page 18534, left column, last bullet point, where it recites:
• We assume that at an arbitrary timestep t all the weights are simultaneously updated. Since the pipeline is constantly fed with training samples and calculates the corresponding NN's gradient values, the calculations of the samples that were in the first three pipeline stages (FP stages) prior to the weights update that are now stored in the pipeline registers were conducted using the old weight values. However, in the following timesteps when those calculations propagate to the BP and GC stages the corresponding calculations will be conducted using the updated weight values.
Claim 8
Claim 8’s “determining, according to second training data for a next training round, a second target parameter required to be written into the target memory in a second network parameter required by an embedding of second training data, in response to the computing core training the first network parameter according to the first training data” is anticipated by Gerogiannis, et al., page 18530, left column, first full paragraph, where it recites:
The designed Accelerator is suitable for algorithms employing Batch Gradient Descent (BGD) [21] as the learning algorithm, according to which the gradient values for a batch of training samples are accumulated. The learning update rule is given by
***
where dΘbatch denotes the sum of the gradient values for all the samples in the batch, Θ is the parameter to be updated (the network's weights) and a is the learning rate.
Note that the network weights are the “target parameter” to be stored.
Claim 8’s “determining a remaining storage slot in the target memory according to the first mapping relationship between the storage slot of the target memory and the network parameter; and” is anticipated by Gerogiannis, et al., page 18532, left column, first paragraph, where it recites:
In Fig. 7 the core blocks of the architecture are presented. There are two core modules, namely the Inference and Training Modules which operate in parallel. Since both operations are using the same weights, to avoid memory conflicts there are two weight memories one for inference and one for training. Additionally, since the training module is split into pipeline stages which operate simultaneously and both the FP and BP training computations access the same weights, the training weights memory consists of two replicas. There are two additional memories, the first of which accumulates the gradients dWi as described in sub-section IV.A. The role of the Updated Weights Memory (which also contains two replicas) will become clearer in sub-section B. All memory blocks, including the Replay Memory are implemented using on-chip Dual Port Block RAMs (BRAMs). Although the total memory requirements are increased by a factor of 3 in comparison with a serial CPU based implementation (serial execution of inference and training with no pipeline stages in training) which would use a single weight memory and a memory for accumulating the gradient values, the number of weights in the typical NN configurations for the applications of interest does not impose high memory requirements. Thus, all the weight memory blocks in our designed architecture can be effectively implemented and partitioned without utilizing a large percentage of the FPGA memory resources.
Claim 8’s “writing the second target parameter into the target memory in response to the remaining storage slot meeting a storage requirement of the second target parameter” is anticipated by Gerogiannis, et al., page 18534, left column, last bullet point, where it recites:
• We assume that at an arbitrary timestep t all the weights are simultaneously updated. Since the pipeline is constantly fed with training samples and calculates the corresponding NN's gradient values, the calculations of the samples that were in the first three pipeline stages (FP stages) prior to the weights update that are now stored in the pipeline registers were conducted using the old weight values. However, in the following timesteps when those calculations propagate to the BP and GC stages the corresponding calculations will be conducted using the updated weight values.
Claim 12
Claim 12’s “determining, by using a first processor according to first training data for a current training round, a first target parameter required to be written into a target memory in a first network parameter required by an embedding of the first training data, wherein the target memory is a memory contained in a second processor” is anticipated by Gerogiannis, et al., page 18530, left column, first full paragraph, where it recites:
The designed Accelerator is suitable for algorithms employing Batch Gradient Descent (BGD) [21] as the learning algorithm, according to which the gradient values for a batch of training samples are accumulated. The learning update rule is given by
***
where dΘbatch denotes the sum of the gradient values for all the samples in the batch, Θ is the parameter to be updated (the network's weights) and a is the learning rate.
Note that the network weights are the “target parameter” to be stored.
Claim 12’s “determining, by using the first processor, a remaining storage slot in the target memory according to a first mapping relationship between a storage slot of the target memory and a network parameter” is anticipated by Gerogiannis, et al., page 18532, left column, first paragraph, where it recites:
In Fig. 7 the core blocks of the architecture are presented. There are two core modules, namely the Inference and Training Modules which operate in parallel. Since both operations are using the same weights, to avoid memory conflicts there are two weight memories one for inference and one for training. Additionally, since the training module is split into pipeline stages which operate simultaneously and both the FP and BP training computations access the same weights, the training weights memory consists of two replicas. There are two additional memories, the first of which accumulates the gradients dWi as described in sub-section IV.A. The role of the Updated Weights Memory (which also contains two replicas) will become clearer in sub-section B. All memory blocks, including the Replay Memory are implemented using on-chip Dual Port Block RAMs (BRAMs). Although the total memory requirements are increased by a factor of 3 in comparison with a serial CPU based implementation (serial execution of inference and training with no pipeline stages in training) which would use a single weight memory and a memory for accumulating the gradient values, the number of weights in the typical NN configurations for the applications of interest does not impose high memory requirements. Thus, all the weight memory blocks in our designed architecture can be effectively implemented and partitioned without utilizing a large percentage of the FPGA memory resources.
Claim 12’s “writing, by using the first processor in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory, and transmitting a training task information to the second processor, wherein the training task information is based on the first training data; and” is anticipated by Gerogiannis, et al., page 18534, left column, last bullet point, where it recites:
• We assume that at an arbitrary timestep t all the weights are simultaneously updated. Since the pipeline is constantly fed with training samples and calculates the corresponding NN's gradient values, the calculations of the samples that were in the first three pipeline stages (FP stages) prior to the weights update that are now stored in the pipeline registers were conducted using the old weight values. However, in the following timesteps when those calculations propagate to the BP and GC stages the corresponding calculations will be conducted using the updated weight values.
Claim 12’s “adjusting, by using a computing core of the second processor in response to receiving the training task information, the first network parameter according to the first training data” is anticipated by Gerogiannis, et al., page 18534, left column, last bullet point, where it recites:
• We assume that at an arbitrary timestep t all the weights are simultaneously updated. Since the pipeline is constantly fed with training samples and calculates the corresponding NN's gradient values, the calculations of the samples that were in the first three pipeline stages (FP stages) prior to the weights update that are now stored in the pipeline registers were conducted using the old weight values. However, in the following timesteps when those calculations propagate to the BP and GC stages the corresponding calculations will be conducted using the updated weight values.
Claim 27
Claim 27’s “27. A system of training a deep learning model, comprising a first processor and a second processor, wherein the second processor comprises a target memory and a computing core” is anticipated by Gerogiannis, et al., page 18540, left column, last partial paragraph, where it recites:
VII. IMPLEMENTATION AND LATENCY-ENERGY
EVALUATION
The hardware implementation and performance evaluation was conducted using the Zynq UltrascaleC MPSoC ZCU104 Evaluation Kit, which features the XCZU7EV-2FFVC1156 MPSoC, a quad-core ARM Cortex-A53 processor and a dual-core Cortex-R5 processor. The designed Accelerator (on the available MPSoC FPGA) was used as a coprocessing element for the Cortex-A53 CPU. The performance of the designed…
Claim 27’s “the first processor is configured to” is anticipated by Gerogiannis, et al., page 18540, left column, last partial paragraph, where it recites:
VII. IMPLEMENTATION AND LATENCY-ENERGY
EVALUATION
The hardware implementation and performance evaluation was conducted using the Zynq UltrascaleC MPSoC ZCU104 Evaluation Kit, which features the XCZU7EV-2FFVC1156 MPSoC, a quad-core ARM Cortex-A53 processor and a dual-core Cortex-R5 processor. The designed Accelerator (on the available MPSoC FPGA) was used as a coprocessing element for the Cortex-A53 CPU. The performance of the designed…
Claim 27’s “determine, according to first training data for a current training round, a first target parameter required to be written into a target memory in a first network parameter required by an embedding of the first training data” is anticipated by Gerogiannis, et al., page 18530, left column, first full paragraph, where it recites:
The designed Accelerator is suitable for algorithms employing Batch Gradient Descent (BGD) [21] as the learning algorithm, according to which the gradient values for a batch of training samples are accumulated. The learning update rule is given by
***
where dΘbatch denotes the sum of the gradient values for all the samples in the batch, Θ is the parameter to be updated (the network's weights) and a is the learning rate.
Note that the network weights are the “target parameter” to be stored.
Claim 27’s “determine a remaining storage slot in the target memory according to a first mapping relationship between a storage slot of the target memory and a network parameter; and” is anticipated by Gerogiannis, et al., page 18532, left column, first paragraph, where it recites:
In Fig. 7 the core blocks of the architecture are presented. There are two core modules, namely the Inference and Training Modules which operate in parallel. Since both operations are using the same weights, to avoid memory conflicts there are two weight memories one for inference and one for training. Additionally, since the training module is split into pipeline stages which operate simultaneously and both the FP and BP training computations access the same weights, the training weights memory consists of two replicas. There are two additional memories, the first of which accumulates the gradients dWi as described in sub-section IV.A. The role of the Updated Weights Memory (which also contains two replicas) will become clearer in sub-section B. All memory blocks, including the Replay Memory are implemented using on-chip Dual Port Block RAMs (BRAMs). Although the total memory requirements are increased by a factor of 3 in comparison with a serial CPU based implementation (serial execution of inference and training with no pipeline stages in training) which would use a single weight memory and a memory for accumulating the gradient values, the number of weights in the typical NN configurations for the applications of interest does not impose high memory requirements. Thus, all the weight memory blocks in our designed architecture can be effectively implemented and partitioned without utilizing a large percentage of the FPGA memory resources.
Claim 27’s “write, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory, and transmit a training task information to the second processor, wherein the training task information is based on the first training data; and” is anticipated by Gerogiannis, et al., page 18534, left column, last bullet point, where it recites:
• We assume that at an arbitrary timestep t all the weights are simultaneously updated. Since the pipeline is constantly fed with training samples and calculates the corresponding NN's gradient values, the calculations of the samples that were in the first three pipeline stages (FP stages) prior to the weights update that are now stored in the pipeline registers were conducted using the old weight values. However, in the following timesteps when those calculations propagate to the BP and GC stages the corresponding calculations will be conducted using the updated weight values.
Claim 27’s “the second processor is configured to: adjust, by using a computing core in response to receiving the training task information, the first network parameter according to the first training data” is anticipated by Gerogiannis, et al., page 18534, left column, last bullet point, where it recites:
• We assume that at an arbitrary timestep t all the weights are simultaneously updated. Since the pipeline is constantly fed with training samples and calculates the corresponding NN's gradient values, the calculations of the samples that were in the first three pipeline stages (FP stages) prior to the weights update that are now stored in the pipeline registers were conducted using the old weight values. However, in the following timesteps when those calculations propagate to the BP and GC stages the corresponding calculations will be conducted using the updated weight values.
Claim 31
Claim 31’s “at least one processor; and” is anticipated by Gerogiannis, et al., page 18540, left column, last partial paragraph, where it recites:
VII. IMPLEMENTATION AND LATENCY-ENERGY
EVALUATION
The hardware implementation and performance evaluation was conducted using the Zynq UltrascaleC MPSoC ZCU104 Evaluation Kit, which features the XCZU7EV-2FFVC1156 MPSoC, a quad-core ARM Cortex-A53 processor and a dual-core Cortex-R5 processor. The designed Accelerator (on the available MPSoC FPGA) was used as a coprocessing element for the Cortex-A53 CPU. The performance of the designed…
Claim 31’s “a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to, when executed by the at least one processor, cause the at least one processor to implement the method of claim 12” is anticipated by Gerogiannis, et al., page 18532, right column, first partial paragraph, where it recites:
Operations that are vertically stacked are executed in parallel. The operations that appear in light color are performed in the same way in every operational cycle. The functionality of the operations appearing in dark color is determined by a Finite State Machine (FSM), namely the Bubble Shift Register (BSR), which is presented in subsection B. and controls the training pipeline and the weight updates. As an example, consider the UPD_W_INF operation. Since weights updates are performed once every timesteps (and consequently once every operational cycles), this operation is either performed or omitted. On the other hand, although the training operation is performed in every timestep, the functionality of the different stages is determined by the BSR.
Claim 32
Claim 32’s “32. A non-transitory computer-readable storage medium having computer instructions therein, wherein the computer instructions are configured to cause a computer to implement the method of claim 12. ” is anticipated by Gerogiannis, et al., page 18532, right column, first partial paragraph, where it recites:
Operations that are vertically stacked are executed in parallel. The operations that appear in light color are performed in the same way in every operational cycle. The functionality of the operations appearing in dark color is determined by a Finite State Machine (FSM), namely the Bubble Shift Register (BSR), which is presented in subsection B. and controls the training pipeline and the weight updates. As an example, consider the UPD_W_INF operation. Since weights updates are performed once every timesteps (and consequently once every operational cycles), this operation is either performed or omitted. On the other hand, although the training operation is performed in every timestep, the functionality of the different stages is determined by the BSR.
Claim 34
Claim 34’s “at least one processor, and” is anticipated by Gerogiannis, et al., page 18540, left column, last partial paragraph, where it recites:
VII. IMPLEMENTATION AND LATENCY-ENERGY
EVALUATION
The hardware implementation and performance evaluation was conducted using the Zynq UltrascaleC MPSoC ZCU104 Evaluation Kit, which features the XCZU7EV-2FFVC1156 MPSoC, a quad-core ARM Cortex-A53 processor and a dual-core Cortex-R5 processor. The designed Accelerator (on the available MPSoC FPGA) was used as a coprocessing element for the Cortex-A53 CPU. The performance of the designed…
Claim 34’s “a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to, when executed by the at least one processor, cause the at least one processor to implement the method of claim 1” is anticipated by Gerogiannis, et al., page 18532, right column, first partial paragraph, where it recites:
Operations that are vertically stacked are executed in parallel. The operations that appear in light color are performed in the same way in every operational cycle. The functionality of the operations appearing in dark color is determined by a Finite State Machine (FSM), namely the Bubble Shift Register (BSR), which is presented in subsection B. and controls the training pipeline and the weight updates. As an example, consider the UPD_W_INF operation. Since weights updates are performed once every timesteps (and consequently once every operational cycles), this operation is either performed or omitted. On the other hand, although the training operation is performed in every timestep, the functionality of the different stages is determined by the BSR.
Conclusion
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/WILBERT L STARKS/
Primary Examiner, Art Unit 2122
WLS
23 JUN 2026
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