DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/07/2026 has been entered.
Claim Status
This Office Action is in response to communications filed on 07/07/2026. Claims 1, 3, 9, 10-11 and 13 were amended. No claims were canceled. Claims 14-20 were newly added. Likewise, claims 1-20 are pending for examination.
Title 35, U.S. Code
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior office action.
Claim Rejections - 35 USC § 103
Claims 1-13 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (DE-112019003391) in view of Yamaha (JP 4178641 B2).
Regarding claim 1 (Currently Amended), Suzuki teaches a method for simultaneously controlling in real time a plurality of haptic actuators by a plurality of haptic controllers, each haptic controller being associated with one haptic actuator of the plurality of haptic actuators, the plurality of haptic controllers being integrated into a control device (Pg 7 middle thru Pg 10 second paragraph, ¶072; Figs 16 element 40; Fig 18 element 34A, decoder 3 comprises a computing device such as a CPU and a DSP, decodes the encoded data received through the network 4, and controls each of the tactile display devices 6 based on the decoded tactile signal), the method comprising
receiving, by the control device, a sampled digital signal emitted by an operating device, the digital signal comprising a plurality of samples, each sample comprising a control value per haptic controller of the plurality of haptic controllers (Fig 10, Pg. 7: ¶005 - ¶011; also see Fig 16; elements 2, 4, 3A, 40),
a data transfer between the operating device and the control device being of isochronous type (¶066-¶067; “to the internet” Examiner notes that an internet implementation is still functionally viable and/or relevant);
for each sample, simultaneously extracting, by each haptic controller, the corresponding control value included in the sample (Fig 18 element 34A);
controlling the plurality of haptic actuators by the plurality of haptic controllers, the controlling step comprising the following sub- steps for each haptic controller (Fig 18 element 6)
converting, by the haptic controller, the control value extracted into an activation signal for activating the corresponding haptic actuator (Fig 18 element 34A, 33, 32, 31);
transmitting the activation signal to the corresponding haptic actuator (Fig 18 elements 31, 6).
Suzuki does not explicitly mention so that the data is transferred at a periodic interval; Yamaha from an analogous data transfer art teaches the concept whereby an Isochronous transfer is described… as data transfer is performed periodically with 125μs as one cycle (¶014). A cycle start packet indicating the start of this cycle is transmitted from the manager/terminal thereby determining one cycle for performing isochronous transfer (¶014). In other words, the data is transferred at an exemplary125μ periodic interval. Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to combine Suzuki’s method of an isochronous internet so that the data is transferred at a periodic interval, as taught by Yamaha, in order to achieve real-time synchronized transfer of the data .
Regarding claim 2, Suzuki and Yamaha teach the method according to claim 1, and Suzuki teaches further comprising a step of storing the digital signal received in a buffer memory, performed prior to the extracting step (Fig 18; elements 43, 43A, Pg. 7: ¶009-¶010; a central processing unit (CPU) and digital signal processor (DSP) perform coding of one of each of the tactile sensors 5 output detection signal (tactile signal) according to a predetermined data format and transmits an encoded tactile signal, “encoded data”, via predetermined network 4, such as the Internet, to decoding device 3; Examiner notes claim 2 is implicit in the coding/transmiting over a network and decoding/receiving over sequential usage by user).
Regarding claim 3 (Currently Amended), Suzuki and Yamaha teach the method according to claim 2, and Suzuki teaches wherein the digital signal received is stored in the buffer memory in a form of frames with headers and data streams of the respective times which correspond to the samples and their respective haptic actuators each control value included in the digital signal received being stored per corresponding frame (see Fig 8, Pg 13: ¶003 - ¶006; data structure of a frame as shown). Suzuki does not expressly mention the forming of an array, with rows and columns. A person of ordinary skill in the art, upon reading the reference, would also have recognized the desirability of improved methods of forming of an array, with rows and columns for storing data whereby each row of which corresponds to a sample and each column of which corresponds to a haptic actuator, each control value included in the digital signal received being stored at the row and at the column of the corresponding array for location based haptics to occur. It would require no more than "ordinary skill and common sense," to use the forming of an array, with rows and columns representing encoded data. Thus, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to try using the forming of an array, with rows and columns representing encoded data, as a person with ordinary skill has good reason to pursue known options within his or her technical grasp.
Regarding claim 4, Suzuki and Yamaha teach the method according to claim 2. Suzuki is silent on wherein the step of controlling of the plurality of haptic actuators is performed only if the buffer comprises a number of data greater than or equal to a predetermined threshold. However, it had been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate that claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex. Parte Masham, 2 USPQ2d 1647 (1987).
Regarding claim 5, Suzuki and Yamaha teach the method according to claim 1. Suzuki is silent on further comprising a step of resampling the digital signal received, performed before the extracting step. However, it had been held that a recitation with respect to the manner in which a claimed method/apparatus is intended to be employed does not differentiate that claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex. Parte Masham, 2 USPQ2d 1647 (1987).
Regarding claim 6, Suzuki and Yamaha teach the method according to claim 5, Suzuki is silent on further wherein the resampling step is performed using a sampling ratio equal to the ratio of a sampling frequency of the digital signal received to an output sampling frequency. However, a person of ordinary skill in the art, upon reading the reference, would also have recognized the desirability of improved methods of a resampling step being performed using a sampling ratio of input signal vs an output signal. It would require no more than "ordinary skill and common sense," to use a sampling ratio equal to the ratio of a sampling frequency of the digital signal received to an output sampling frequency to down convert the data in the decoding process. Thus, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to try using a sampling ratio equal to a ratio of a sampling frequency of the digital signal received to an output sampling frequency, as a person with ordinary skill has good reason to pursue known options within his or her technical grasp.
Regarding claim 7, Suzuki and Yamaha teach the method according to claim 5, wherein when the digital signal is received according to a “internet” protocol (see claim 1). Suzuki is silent on a USB© protocol and the sampling ratio is recalculated after a defined period of time. However, a person of ordinary skill in the art would have had good reason to pursue the known options of using a USB protocol and the sampling ratio being recalculated after a defined period of time, giving the user control over selecting alternative communication protocols with locally positioned devices and the sampling ratio being recalculated after a defined period of time based on the alternative communication speed. It would require no more than "ordinary skill and common sense," to give the user control over selecting alternative communication protocols with locally positioned devices and the sampling ratio being recalculated after a defined period of time based on the alternative communication speed.
Thus, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to try giving the user control over selecting alternative communication protocols with locally positioned devices and the sampling ratio being recalculated after a defined period of time based on the alternative communication speed, as a person with ordinary skill has good reason to pursue known options within his or her technical grasp.
Regarding claim 8, Suzuki and Yamaha teach the method according to claim 1 and Suzuki further teaches wherein the digital signal received is a digital audio signal (Fig 16 element 2, Figs 8, 10, 13 & 14, also see Fig 18; elements 43, 43A, Pg. 7: ¶009-¶010; central processing unit (CPU) and digital signal processor (DSP) perform coding… encoded data is digital data).
Regarding claim 9 (Currently Amended), Suzuki and Yamaha teach the method according to claim 1, wherein the digital signal received is received according to an Ethernet© protocol.(i.e., internet; see claim 1) USB©, IEEE 1588, IEEE 802.1AS (optionally not selected by Examiner) or
Regarding claim 10 (Currently Amended), Suzuki teaches a haptic system comprising a control device comprising at least one microcontroller, (DSP) comprising at least one memory (see claims 1 & 2), a processor (CPU) and a plurality of haptic controllers, the at least one memory comprising instructions which, when the instructions are executed by the processor, cause the processor to implement a method for simultaneously controlling in real time a plurality of haptic actuators by the plurality of haptic controllers, each haptic controller being associated with one haptic actuator of the plurality of haptic actuators, the plurality of haptic controllers being integrated into the control device, the method comprising: receiving, by the control device, a sampled digital signal emitted by an operating device, the digital signal comprising a plurality of samples, each sample comprising a control value per haptic controller of the plurality of haptic controllers, a data transfer between the operating device and the control device being of isochronous type: for each sample, simultaneously extracting, by each haptic controller, the corresponding control value included in the sample; controlling the plurality of haptic actuators by the plurality of haptic controllers, the controlling comprising the following sub-steps for each haptic controller: converting, by the haptic controller, the control value extracted into an activation signal for activating the corresponding haptic actuator; transmitting the activation signal to the corresponding haptic actuator (Examiner notes: that claim 10 is interpreted and rejected the same as claim 1 above)
Regarding claim 11 (Currently Amended), Suzuki and Yamaha teach the haptic system of claim 10 comprising: the plurality of haptic actuators to be controlled (see claim 1 above); wherein the control device is configured to control the plurality of haptic actuators (see claim 1 above).
Regarding claim 12, Suzuki and Yamaha teach the haptic system according to claim 11, and Suzuki teaches further comprising an operating device configured to send the digital signal to the control device (Fig 16 element 2, Figs 8, 10, 13 and 14).
Regarding claim 13 (Currently Amended), Suzuki and Yamaha teach the non-transitory computer readable medium (claim 1: CPU w/ memory means) comprising instructions which, when the instructions are executed by a computer (claim 1: CPU), cause the same to implement a method for simultaneously controlling in real time a plurality of haptic actuators by the plurality of haptic controllers, each haptic controller being associated with one haptic actuator of the plurality of haptic actuators, the plurality of haptic controllers being integrated into a control device, the method comprising: receiving, by the control device, a sampled digital signal emitted by an operating device, the digital signal comprising a plurality of samples, each sample comprising a control value per haptic controller of the plurality of haptic controllers, a data transfer between the operating device and the control device being of isochronous type so that the data is transferred at a periodic interval;; for each sample, simultaneously extracting, by each haptic controller, the corresponding control value included in the sample; controlling the plurality of haptic actuators by the plurality of haptic controllers, the controlling comprising the following sub-steps for each haptic controller: converting, by the haptic controller, the control value extracted into an activation signal for activating the corresponding haptic actuator; transmitting the activation signal to the corresponding haptic actuator (Examiner notes: that claim 13 is interpreted and rejected the same as claim 1 above).
Regarding claim 14 (New), Suzuki and Yamaha teach the method according to claim 1, and Yamaha teaches wherein a protocol synchronizes the timing and bandwidth reservation (¶012; in isochronous transfer, a manager that manages data transfer assigns a channel number and a bandwidth to each piece of data to be transferred in advance, and instructs a device on the data transmission side to transmit a packet of that channel number. Instruct the receiving device to receive a packet with the channel number) of the data transfer between the operating device and the control device (¶014; receiving devices acquire data with a time stamp indicating the reproduction timing, and reproduce the data according to the time stamp. Thereby, the timing at which the audio data is output (performance timing… can be synchronized). Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to combine Suzuki’s method of an isochronous internet so that the data is transferred at a periodic interval, as taught by Yamaha, in order to achieve real-time synchronized transfer of the data.
Claims 15-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (DE-112019003391) in view of Yamaha (JP 4178641 B2) further in view of TANIGUCHI et al. (EP 4418602).
Regarding claim 15 (New), Suzuki and Yamaha teach the method according to claim 14, but both Suzuki and Yamaha are silent on the features of claim 15. TANIGUCHI from an analogous data transfer art teaches the concept wherein the protocol comprises an AVB Audio Video Bridging) protocol on an Ethernet network implementing time synchronization between nodes (Pg 2, Para. 005; US2016149692A1 discloses a method for providing time synchronization in a node connected to an Audio Video Bridging (AVB) Ethernet communication network includes steps of receiving static announcement messages from adjacent nodes and constituting a static grandmaster table, reselecting a grandmaster with reference to the static grandmaster table when a synchronization message timer expires, and updating the static grandmaster table according to reselection of the grandmaster). Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to further combine Suzuki’s method of an isochronous internet transfer wherein a protocol comprises an AVB Audio Video Bridging) protocol on an Ethernet network implementing time synchronization between nodes, as taught by TANIGUCHI, in order to achieve real-time synchronized transfer of the data.
Regarding claim 16 (New), Suzuki and Yamaha teach the method according to claim 14, but both Suzuki and Yamaha are silent on the features of claim 16. TANIGUCHI also teaches the concept wherein the protocol comprises a Time Sensitive Network (TSN) protocol ((Pg 1, Para. 002-003; In the industrial Ethernet network, standardization of TSN (Time Sensitive Networking) technology as a system to transfer control data in real time is in progress. TSN is technology to schedule traffic by making apparatuses time synchronize highly accurately with one another through a network switch (will be written as transfer apparatus below). As a type of TSN technology, there is highly accurate network time synchronization technology)) using an IEEE 1588 standard or an IEEE 802.1AS standard to define node synchronization (Pg 5; last Para.; description will be given using a PTP frame defined in IEEE802.1AS (gPTP). In the gPTP, a Pdelay_Req message, a Pdelay_Resp message, and a Pdelay_Resp_Follow_up message of a two-step system are used for the delay measurement, a Sync/Follow_up message of a two-step system is used for the time synchronization, and an Announce message is used for notification of time source information. As for a method of the delay measurement, however, the method is not limited in particular. For the time synchronization also, a case of a one-step system is also a target of the transfer apparatus 10, not limited to the two-step system. Not limited to the gPTP, as long as a time synchronization profile is a time synchronization profile that uses a PTP frame of IEEE 1588 or a time synchronization profile that uses a PTP frame of extended IEEE 1588, the time synchronization profile is regarded as a target of the transfer apparatus 10). Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to further combine Suzuki’s method of an isochronous internet transfer wherein the protocol comprises a Time Sensitive Network (TSN) protocol using an IEEE 1588 standard or an IEEE 802.1AS standard to define node synchronization, as taught by TANIGUCHI, in order to achieve real-time synchronized transfer of the data.
Regarding claim 19 (New), Suzuki and Yamaha teach the method according to claim 1, andTANIGUCHI also teaches the concept wherein the data transfer between the operating device and the control device is not communicated via the Internet (protocol comprises an AVB Audio Video Bridging) protocol on an Ethernet network implementing time synchronization between nodes (Pg 2, Para. 005);.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (DE-112019003391) in view of Yamaha (JP 4178641 B2) further in view of Ho et al. (U.S. Patent Application Pub. 2004/0240463).
Regarding claim 17 (New), Suzuki and Yamaha teach the method according to claim 1, but both Suzuki and Yamaha are silent on the features of claim 17. Ho from an analogous data transfer art teaches the concept wherein a latency time between emission of a signal by the operating device and reception of said signal by the control device is less than 20 milliseconds (¶032; access coordinator 302 has a processor 304 that is operable on quantities with latencies in the range of milliseconds and is associated with the MAC layer 202. Processor 304 cooperatively interacts with a MAC memory 306, in accordance with the present invention as described hereinafter, to determine whether a particular isochronous stream will be admitted in order to schedule access time within WLAN 102; Examiner interprets in the range of milliseconds as less than 10 milliseconds). Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to further combine Suzuki’s method of an isochronous internet transfer wherein a latency time between emission of a signal by the operating device and reception of said signal by the control device is less than 20 milliseconds, as taught by Ho, in order to achieve near real-time synchronized transfer of the data.
Regarding claim 18 (New), Suzuki and Yamaha teach the method according to claim 17, but both Suzuki and Yamaha are silent on the features of claim 18. Ho from an analogous data transfer art teaches the concept wherein a latency time between emission of a signal by the operating device and reception of said signal by the control device is less than 15 milliseconds (¶032; access coordinator 302 has a processor 304 that is operable on quantities with latencies in the range of milliseconds and is associated with the MAC layer 202. Processor 304 cooperatively interacts with a MAC memory 306, in accordance with the present invention as described hereinafter, to determine whether a particular isochronous stream will be admitted in order to schedule access time within WLAN 102; Examiner interprets in the range of milliseconds single digit milliseconds). Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to further combine Suzuki’s method of an isochronous internet transfer wherein a latency time between emission of a signal by the operating device and reception of said signal by the control device is less than 15 milliseconds, as taught by Ho, in order to achieve near real-time synchronized transfer of the data
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (DE-112019003391) in view of Yamaha (JP 4178641 B2) further in view of Ferguson et al. (U.S. Patent Application Pub. 2006/0036776).
Regarding claim 20 (New), Suzuki and Yamaha teach the method according to claim 1, but both Suzuki and Yamaha are silent on the features of claim 20. Ferguson from an analogous data transfer art teaches the concept wherein a data reception rate of the data transfer is 8192 bytes per millisecond (¶030; A Transfer Descriptor contains information necessary to describe the data packets to be transferred. The fields of a Transfer Descriptor include data toggle information, shared memory buffer location, and completion status codes. Each Transfer Descriptor contains information that describes one or more data packets….data buffer for each transfer descriptor ranges in size from 0 to 8192 bytes with a maximum of one physical page crossing. Transfer Descriptors are linked in a queue, and the first one queued is the first one processed; also see ¶025-¶027 & ¶032). Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing the invention to further combine Suzuki’s method of an isochronous internet transfer wherein a data reception rate of the data transfer is 8192 bytes per millisecond, as taught by Ferguson, in order to achieve near real-time synchronized transfer of the data
Response to Arguments
Applicant's arguments filed 07/07/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
[End of Arguments].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANCIL H LITTLEJOHN JR whose telephone number is (571)270-3718. The examiner can normally be reached M-F 8:30-5 (CST).
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/MANCIL LITTLEJOHN JR/Examiner, Art Unit 2685
/QUAN ZHEN WANG/Supervisory Patent Examiner, Art Unit 2685
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