Prosecution Insights
Last updated: October 01, 2026
Application No. 18/697,858

A Wirelessly Powered, Battery-Less Closed Loop Biopotential Recording IC for Implantable Medical Applications

Non-Final OA §102§103
Filed
Apr 02, 2024
Priority
Oct 04, 2021 — provisional 63/252,104 +1 more
Examiner
ZIMMERMAN, BRIAN A
Art Unit
2689
Tech Center
2600 — Communications
Assignee
The Regents of the University of California
OA Round
2 (Non-Final)
18%
Grant Probability
At Risk
2-3
OA Rounds
0m
Est. Remaining
37%
With Interview

Examiner Intelligence

Grants only 18% of cases
18%
Career Allowance Rate
6 granted / 33 resolved
-43.8% vs TC avg
Strong +18% interview lift
Without
With
+18.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
11 currently pending
Career history
40
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
60.8%
+20.8% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 33 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, filed 5/4/26, with respect to the rejection(s) of claim(s) under John have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejections are made as set forth below. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gazdzinski (20150208907). Regarding claim 1, Gazdzinski (20150208907) shows a sensing device, comprising: a wireless receiver configured to receive a first radio frequency (RF) signal; (RFID Tag in figure 17) one or more wireless transmitters, wherein at least one wireless transmitter is configured to transmit a second RF signal, and wherein the first RF signal and the second RF signal have different frequencies [0201]; and [0201] The process of "reading" and communicating with an RFID tag such as that used in the probe 1700 of FIG. 17 comprises bringing a RFID tag within proximity to an RFID sensor ("reader") 1750 which emanates a radio frequency wake-up field having a limited range. The RFID tag 1702 detects the presence of the wakeup field of the sensor 1750, and subsequently various forms or protocols of handshake occur between the tag 1702 and the sensor 1750 in order to exchange data. All of this communication between the tag and the sensor is performed using RF carriers of one or more prescribed frequencies. As is well known in the art, so-called "low-frequency" systems operate in the kHz to low-MHz range (unlicensed). Low frequency systems are generally low cost and complexity and have comparatively limited range, but are attractive since the low frequency energy tends to suffer low losses from materials like metal, polymers, tissue, and the like. High-frequency systems operate in the low-MHz to GHz range (often licensed). High-frequency systems in general have greater range, but are more directional. Additionally, the performance of these high frequency tags may be adversely affected by electromagnetic radiation or proximate metallic objects. a processing circuitry (520), comprising: a power harvesting circuit configured to harvest energy from the first RF signal (passive tags harvest energy from the rf signal); a clock recovery circuit configured to extract a clock signal from the first RF signal (740, [0148]); [0148] Similarly, it will be noted that the method of clocking signal recovery described in the above-referenced patent may be utilized in the present invention to obviate the clock 524 of FIG. 6. Specifically, the ac waveform transferred from the MCD remote unit 802 can be used to generate a clock signal prior to rectification by the diode stage 720 using a clock recovery circuit 740. This clock signal may then be used to drive those components requiring a clock signal, such as the CCD array 402, ADC 512, etc. at least one sensing electrode configured to record an electric signal as at least one selected from the group consisting of a voltage, a current, and an electric charge The sensing device measures voltage in order to determine pressure [337] and also measures current in order to determine the presence of target molecules [0372]; and an analog-to-digital converter (ADC) communicatively coupled to the clock recovery circuit, (ADC 512 and 3310) wherein the ADC is configured to convert the electric signal into a digital signal, [148] wherein the clock signal is used to synchronize at least one wireless transmitter with the conversion of the electric signal into the digital signal, and wherein output from the ADC is serialized and transmitted, by a transmitter using packetizing (figure 35b), to an external hub (804). [0202] Additionally, RFID tags are generally categorized as being "active" (i.e., carry an associated power source for operation of the on-tag integrated circuit, and are capable of spontaneous transmission after reader interrogation), or "passive" which utilizes incident RF energy (from the reader, for example) to generate electrical energy for use by the IC, and transmission. Passive tags are highly energy efficient, and require only a small amount of electrical power to function. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gazdzinski (20150208907) as applied to claim 1 above with additional explanation herein. Regarding claim 7, Gazdzinski (20150208907) does not discuss the particular frequencies being used as claimed, but Gazdzinski (20150208907) does discuss using multiple frequencies, and explains advantages and disadvantages of LF and HF options. discuss using multiple frequencies, and explains advantages and disadvantages of LF and HF options. See paragraph [0201]. [0201] The process of "reading" and communicating with an RFID tag such as that used in the probe 1700 of FIG. 17 comprises bringing a RFID tag within proximity to an RFID sensor ("reader") 1750 which emanates a radio frequency wake-up field having a limited range. The RFID tag 1702 detects the presence of the wakeup field of the sensor 1750, and subsequently various forms or protocols of handshake occur between the tag 1702 and the sensor 1750 in order to exchange data. All of this communication between the tag and the sensor is performed using RF carriers of one or more prescribed frequencies. As is well known in the art, so-called "low-frequency" systems operate in the kHz to low-MHz range (unlicensed). Low frequency systems are generally low cost and complexity and have comparatively limited range, but are attractive since the low frequency energy tends to suffer low losses from materials like metal, polymers, tissue, and the like. High-frequency systems operate in the low-MHz to GHz range (often licensed). High-frequency systems in general have greater range, but are more directional. Additionally, the performance of these high frequency tags may be adversely affected by electromagnetic radiation or proximate metallic objects. Therefore, it would have been obvious to one of ordinary skill in the art to have used the claimed frequencies for the advantages set forth by Gazdzinski (20150208907). Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gazdzinski as applied to claim 1 above, and further in view of Paidimarri (10949730). Regarding claim 9, in an analogous art, Paidimarri (10949730) teaches a multiple stage rectifier. This allows the device to step up input power which would be beneficial for a power harvesting system. [7:22-58] FIG. 4 is another diagram illustrating a tag circuitry in one embodiment. For instance, component 402 may be a specific embodiment of component 304 shown in FIG. 3; component 404 may be a specific embodiment of component 312 shown in FIG. 3. Power connection 418 may be implemented as described above with reference to 318 in FIG. 3. A tag may include multiple RF-to-DC converters (e.g., RF-to-DC converter 1 . . . RF-to-DC converter n) 402, 404. Each RF-to-DC converter has, or is connected, to an antenna interface or antenna 406, 408. Power received from each tag antenna can be combined, for example, directly using rectifiers. In another aspect, power can be combined using additional converter such as a DC-DC power converter. In some embodiments, the RF-to-DC converters 402, 404 are designed to add power and not have any loading when a given frequency is unavailable (for example, if that corresponding reader antenna is off, or if the channel characteristics have a higher loss). In some embodiments, an RF-to-DC converter 402 may include an N-stage rectifier 410. An example schematic of 1-stage of a multi-stage rectifier is shown in FIG. 8A, 802. In one aspect, an N-stage rectifier 410 has an open circuit voltage of N*Vin (input voltage), and an actual voltage is a function of parasitics and the loading from subsequent circuits. For instance, provided that an output voltage is less than N*Vin, an N-stage rectifier 410 can provide power in a system implementing the rectifiers (tag). “N” may be an integer greater than zero. For instance, if N=1, a one-stage rectifier circuit, e.g., shown in FIG. 8B at 804, can be used for the N-stage rectifier block 410, and if N>1, a multi-stage rectifier circuit can be used. An example of a 1-stage of a multi-stage rectifier circuit is shown in FIG. 8A, 802. Therefore, it would have been obvious to one of ordinary skill in the art to have a 5 (five) state passive rectifier in the Gazdzinski system in order to step up the harvested power. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gazdzinski as applied to claim 1 above, and further in view of Fabre (7034685). Regarding claim 11, in an analogous art, Fabre teaches an Interrogator mounted in a wearable device. Figure 2 and [1:57-65]. This provides portability for the interrogator. [1:57-65] These objects are attained by an interrogator device for identifying articles each provided with a transponder, comprising a radio-frequency (RF) interrogation system for obtaining identifying information on each of the articles. The RF interrogation system includes an RF antenna coupled to an electronic module for processing the identifying information from the transponders. The RF antenna is incorporated on two opposite ends of a garment wearable by an agent in charge of collecting loose articles arranged in a storage area, and connected to a electronic module wearable by the agent by communication lines incorporated in the garment. The electronic module includes a discrimination device for determining pertinent identifying information from the plurality of identifying information obtained from the transponders through said RF antenna. Therefore, it would have been obvious so one of ordinary skill in the art to have the interrogator in the Gazdzinski system be mounted on a wearable device in order to increase portability of the interrogator. Claim(s) 14,15,16,17,18,21,23,24,25,27,28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gazdzinski as applied to claim 1 above, and further in view of John (10348136). Regarding claim 14: wherein an adjustable parameter of the device is selected from the group consisting of its frequency of operation, power consumption, number of bits, and duty-cycle (col. 7, lines 3-29 of John described various power conversion process that includes bits and duty-cycle for the AC/DC conversion). This allows flexibility in the system so the user can ‘dial’ into the best solution for the RFID interrogator. Therefore, it would have been obvious to one of ordinary skill in the art to have adjusted the parameters of Gazdzinski to achieve the best solution for any particular application. Regarding claim 15: wherein the output from the ADC is serialized through parallel-to-serial (P2S) logic are considered as obvious inherent features of analog to digital power conversion). Regarding claim 16: further comprising a direct power oscillator and an LC oscillator (col. 26, lines 10-26 of John where John describes power conversion that includes oscillators). Regarding claim 17: as shown in figures 8a-8b of John further comprising: a power management unit (PMU) configured to set an operating mode and maintain a minimum voltage; and a receiver circuitry block configured to provide energy from the first RF signal to the power harvesting circuit (see associated descriptions for details). Regarding claim 18: as shown in element 224 of John wherein the wireless transmitter comprises a data modulator circuit, the data modulator circuit configured to generate the second RF signal using DC voltage received from the PMU . Regarding claim 21: as shown in element 28 of John wherein the PMU is configured to control the wireless transmitter to operate on a duty cycle based upon a current amount of energy stored in a storage capacitor (see associated descriptions for details). Regarding claim 23: as shown in figures 12b-12d of John wherein the clock extraction comprises: demodulating, the first RF signal to obtain an envelope signal, wherein the demodulation is performed using at least one of an envelope detector and a self-mixing principle; filtering, using a low pass filter, the envelope signal; recovering, using a comparator, one or more crossing points between the filtered envelope signal and a reference signal; and generating, using the comparator, a clock signal from the crossing points (see associated descriptions for details). Regarding claim 24: as shown in figure 12a of John wherein the clock extraction further comprises removing noise from the clock signal with a Schmitt trigger (see associated descriptions for details). Regarding claim 25: as shown in element 272 of figure 8b of John wherein the clock signal is used to set rates for at least one of acquiring signal samples and wirelessly receiving data transmissions (see associated descriptions for details). Regarding claim 27: wherein the transmitter using packetizing is configured to transmit data with an 8-bit preamble indicating a starting point of the data (col. 10, lines 28-36 of John). Regarding claim 28: wherein operating modes are selected based on the first RF signal (col. 10, lines 22-26 of John). Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gazdzinski and John as applied to claims 1 and 17 above, and further in view of Theus (5285169). Regarding claim 19, in an analogous art, Theus (5285169) teaches an N-well N-type Metal Oxide Semiconductor. [4:36-54] To avoid the undesired increases of the threshold voltages of the p-channel transistors t1 and t2 commonly associated with the usual connection of the n-wells of such transistors to the positive supply potential V, the n-wells of such transistors are instead tied to the common source potential of the transistors t1 and t2. This alternative connection for providing potential to the n-wells of the transistors also keeps the transconductance of the first transconductance amplifier tv independent of the DC level at the two inputs ip' and in'. For identical reasons, the n-wells of the p-channel transistors t16 and t7 are similarly connected to the common source potential of the transistors t16 and t7. This alternative connection is however only applicable if the paralleling stage p is activated as has been thus far described. Therefore, it would have been obvious to one of ordinary skill in the art to have the claimed N-Well NMOS transistor in the above modified system, to avoid undesired increases of the threshold voltages as taught by Theus. Allowable Subject Matter Claims 2-5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN A ZIMMERMAN whose telephone number is (571)272-3059. The examiner can normally be reached m,t,tr 6-4; w,f 6-noon. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN A ZIMMERMAN/Supervisory Patent Examiner, Art Unit 2686
Read full office action

Prosecution Timeline

Apr 02, 2024
Application Filed
Feb 04, 2026
Non-Final Rejection mailed — §102, §103
May 04, 2026
Response Filed
Jul 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12674691
SYSTEMS AND METHODS FOR A SPATIALLY AWARE CONTROL DEVICE
2y 5m to grant Granted Jul 07, 2026
Patent 12668340
MARINE VESSEL
3y 1m to grant Granted Jun 30, 2026
Patent 12612033
HITCH ASSIST TRAILER, COUPLER AND HITCHBALL DETECTION AND TRACKING METHOD
2y 1m to grant Granted Apr 28, 2026
Patent 12505731
METHOD AND A SYSTEM FOR IMPROVING ALARM RELIABILITY OF SMOKE FIRE DETECTOR
1y 6m to grant Granted Dec 23, 2025
Patent 12415534
VEHICLE SYSTEM AND STORAGE MEDIUM
1y 7m to grant Granted Sep 16, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
18%
Grant Probability
37%
With Interview (+18.5%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 33 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month