DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Pub. No.: US 20220399404 A1), hereinafter as Kim, in view of Park et al. (Pub. No.: US 20220130922 A1), hereinafter as Park.
[Polyanskiy ("Refractive index database") is utilized herein as evidence.]
PNG
media_image1.png
384
475
media_image1.png
Greyscale
Image A: close up of Kim Fig. 3, showcasing light-emitting area
PNG
media_image2.png
214
354
media_image2.png
Greyscale
Image B: close up of Kim Fig. 3, showcasing Source electrode and Drain electrode
With respect to claim 1, Kim teaches a display panel, comprising: a base substrate (see Kim Fig. 3, window WD); a plurality of light-emitting devices (see Kim Fig. 5, light emitting element OLED; and see Kim [0148]: “FIG. 4 is a plan view of the display panel according to an embodiment of the present disclosure. FIG. 5 is a cross-sectional view taken along the line II-II′ of FIG. 4. FIG. 4 illustrates six emission areas PXA-R, PXA-G, and PXA-B included in two pixel rows PXL as an example. In FIG. 5, the driving transistor T1 and the capacitor Cst illustrated in FIG. 3 are omitted for convenience of illustration.”) on a side of the base substrate (see Kim Fig. 3); wherein a surface of the light-emitting device facing the base substrate is a light exiting surface of the light-emitting device (see Kim [0095]: “In FIG. 3, a direction in which light generated from the light emitting element OLED is provided to the window WD is indicated by a bolded arrow.”); and a driving circuit layer (see Kim Fig. 3, circuit element layer DP-CL) between the base substrate and the plurality of light-emitting devices (see Kim Figs. 3&5); wherein, in an area corresponding to a light-emitting area of the light-emitting device (see Image A), the driving circuit layer comprises: a light-transmitting portion (see Kim Fig. 3, emission area PXA); the light-transmitting portion comprises a low-refractive-index light-transmitting insulating layer (silicon oxide layer in buffer layer 30, see Kim [0106]: “In some embodiments, in the buffer layer 30, a silicon oxide layer and a silicon nitride layer may be alternately laminated.”) and a high-refractive-index light-transmitting insulating layer (silicon nitride layer in buffer layer 30, see Kim [0106]: “In some embodiments, in the buffer layer 30, a silicon oxide layer and a silicon nitride layer may be alternately laminated.”) that are alternately stacked (see Kim Fig. 3, buffer layer 30; and see Kim [0106]: “In some embodiments, in the buffer layer 30, a silicon oxide layer and a silicon nitride layer may be alternately laminated.”); and a refractive index of the low-refractive-index light-transmitting insulating layer is smaller than a refractive index of the high-refractive-index light-transmitting insulating layer (let the silicon nitride layer be Si3N4, SiN (Silicon nitride), which has refractive index of 2.0458, and let the silicon oxide layer be SiO2 (Silicon dioxide, Silica, Quartz), which has refractive index of 1.4498, which is smaller than silicon nitride’s refractive index. See Polyanskiy.); wherein the driving circuit layer (see Kim Fig. 3, circuit element layer DP-CL) further comprises: a thin film transistor (see Kim Fig. 3, driving transistor T1); and the thin film transistor comprises: a gate electrode (see Kim Fig. 3, gate G1), and a source electrode (see Image B, Source electrode) and a drain electrode (see Image B, Drain electrode) on a side of the gate electrode facing away from the base substrate (see Kim Fig. 3); wherein the light-transmitting portion (see Kim Fig. 3, emission area PXA) comprises: a buffer layer (see Kim Fig. 3, passivation layer 20) between the base substrate and the gate electrode (see Kim Fig. 3); a first insulating layer (see Kim Fig. 3, intermediate insulating layer 50) between the gate electrode and the source electrode (see Kim Fig. 3); and a second insulating layer (see Kim Fig. 3, cover insulating layer 60) on a side, facing away from the base substrate, of the source electrode and the drain electrode (see Kim Fig. 3).
Kim does not teach that a refractive index of the first insulating layer is greater than a refractive index of the buffer layer, and the refractive index of the first insulating layer is greater than a refractive index of the second insulating layer, wherein the first insulating layer, the buffer layer and the second insulating layer comprise a same material.
Park teaches a refractive index of a first insulating layer (see Park Fig. 8, first interlayer insulating layer ILD1; and see Park [0155] and [0153]: “The first interlayer insulating layer ILD1 may include the same material as that of the gate insulating layer GI, or may include one or more materials selected from the materials illustrated as constituent materials of the gate insulating layer GI.”; “The gate insulating layer GI may be an inorganic insulating film including an inorganic material. For example, the gate insulating layer GI may include at least one of metal oxides or metal nitrides such as a silicon nitride (SiNx), a silicon oxide (SiOx), a silicon oxynitride (SiOxNy), and an aluminum oxide (AlOx).”; let the first insulating layer comprise of silicon nitride. Silicon nitride has the refractive index of 1.9827 according to Polyanski.) is greater than a refractive index of a buffer layer (see Park Fig. 8, buffer layer BFL; and see Park [0148] “The buffer layer BFL may be an inorganic insulating film including an inorganic material. The buffer layer BFL may include at least one of metal oxides such as a silicon nitride (SiNx), a silicon oxide (SiOx), a silicon oxynitride (SiOxNy), and an aluminum oxide (AlOx). The buffer layer BFL may be provided as a single film, but may be provided as a multifilm of at least double or more films. When the buffer layer BFL is provided as the multi-film, respective layers thereof may be made of the same material or different materials.”; let the buffer layer comprise of a layer of silicon nitride and a layer of silicon dioxide. The refractive index across both layers is 1.6734, which is less than silicon nitride’s refractive index. The following shows the derivation of the refractive index of a layer consisting of a silicon nitride layer and a silicon dioxide layer:
The refractive index formula is
n
=
c
v
or
n
v
=
c
, where c is the speed of light and v is the velocity of light through a medium. According to Polyanski,
n
S
i
O
2
=
1.4476
and
n
S
i
N
=
1.9827
. Let there be two layers, one comprising
S
i
O
2
and another
S
i
N
, with both layers being of similar thickness. In order to find the index of refraction across both layers, the average velocity is needed. For
S
i
O
2
,
v
1
≈
2.0724
×
10
8
m
s
. For
S
i
N
,
v
2
≈
1.5131
×
10
8
m
s
.
v
a
v
g
=
v
1
+
v
2
2
=
1.79275
×
10
8
m
s
n
t
o
t
a
l
=
c
v
a
v
g
=
1.6734
So, the refractive index across the two layers is roughly 1.6734.), and the refractive index of the first insulating layer is greater than a refractive index of a second insulating layer (see Park Fig. 8, second interlayer insulating layer ILD2; and see Park [0156]: “In some embodiments, the second interlayer insulating layer ILD2 may include the same material as the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto. The second interlayer insulating layer ILD2 may be provided as a single film, or may be provided as a multi-film of at least double or more films.”; see Park [0155] and [0153] for ILD1 materials. Let the second insulating layer comprise of a layer of silicon nitride and a layer of silicon dioxide. The refractive index across both layers is 1.6734 (see above derivation) which is less than silicon nitride’s refractive index.), wherein the first insulating layer (Park Fig. 8, first interlayer insulating layer ILD1), the buffer layer (Park Fig. 8, buffer layer BFL) and the second insulating layer (Park Fig. 8, second interlayer insulating layer ILD2) comprise a same material (See Park [0148], [0153], [0155], and [0156]. Earlier, the buffer and insulating layer were chosen to have at least one layer of silicon nitride, therefore all comprising a same material.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the materials of Kim with materials taught by Park in order to simplify the manufacturing process by having fewer materials for multiple layers.
With respect to claim 2, Kim and Park teach the display panel according to claim 1, wherein a difference between the refractive indexes of the low-refractive-index light-transmitting insulating layer (see Kim Fig. 3, silicon oxide layer in buffer layer 30, see Kim [0106]) and the high-refractive-index light-transmitting insulating layer (see Kim Fig. 3, silicon nitride layer in buffer layer 30, see Kim [0106]) which are adjacent is greater than 0.2 (Si3N4, SiN (Silicon nitride) has refractive index of 2.0458 and SiO2 (Silicon dioxide, Silica, Quartz) has refractive index of 1.4498. The difference between these two indexes is 0.596, which is greater than 0.2. See Polyanskiy.).
With respect to claim 3, Kim and Park teach the display panel according to claim 1, wherein the base substrate (see Kim Fig. 3, window WD) is adjacent to the low-refractive-index light-transmitting insulating layer (see Kim Fig. 3, silicon oxide layer in buffer layer 30, see Kim [0106]); and the refractive index of the low-refractive-index light-transmitting insulating layer adjacent to the base substrate is smaller than a refractive index of the base substrate (let the base substrate include PET film, see Kim [0091]-[0092]: “The window WD may include an optically transparent insulating material. For example, the window WD may include a glass substrate or a synthetic resin film. When the window WD includes the synthetic resin film, the window WD may include a polyimide (PI) film or a polyethylene terephthalate (PET) film.”, which has refractive index of 1.5605, and let the silicon oxide layer be SiO2 (Silicon dioxide, Silica, Quartz), which has refractive index of 1.4498, which is smaller than PET film’s refractive index. See Polyanskiy.).
With respect to claim 5, Kim and Park teach the display panel according to claim 1, wherein the refractive index of the buffer layer (see Park Fig. 8, buffer layer BFL; and see Park [0148]. Let the buffer layer comprise of a layer of silicon nitride and a layer of silicon dioxide. The refractive index across both layers is 1.6734 (see derivation from claim 1).) is equal to the refractive index of the second insulating layer (see Park Fig. 8, second interlayer insulating layer ILD2; and see Park [0156]. Let the second insulating layer comprise of a layer of silicon nitride and a layer of silicon dioxide. The refractive index across both layers is 1.6734 (see derivation from claim 1) which is the same as refractive index of the buffer layer.).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Park, and Lin, in view of Qu et al. (Pub. No.: CN 111463244 A), hereinafter as Qu.
With respect to claim 6, Kim and Park teach the display panel according to claim 1.
Kim and Park do not teach that a thickness of the first insulating layer is greater than a thickness of the buffer layer; and the thickness of the first insulating layer is greater than a thickness of the second insulating layer.
Qu teaches that a thickness (see Qu pg. 2-3: “The first gate insulating layer 4 located on the side of the active layer 15 away from the flexible substrate 2 can be silicon nitride or silicon oxide, or a double layer composed of a silicon nitride film and a silicon oxide film. Layer structure, wherein the thickness of the silicon nitride film can be 100-500nm, and the thickness of the silicon oxide film can be 400-1000nm;”, where one would choose the total thickness to be about 800nm.) of a first insulating layer (see Qu Fig. 1, first gate insulating layer 4) is greater than a thickness (see Qu pg. 6: “When the buffer layer 3 adopts a double-layer structure composed of a silicon nitride film and a silicon oxide film, a silicon nitride layer with a thickness of 50-300 nm is deposited first, and then a silicon dioxide layer with a thickness of 100-300 nm is deposited.”, where one would choose the total thickness to be about 350nm.) of a buffer layer (see Qu Fig. 1, buffer layer 3); and the thickness of the first insulating layer is greater than a thickness (see Qu pg. 5: “The interlayer insulating layer 6 located on the side of the second gate metal layer 20 away from the flexible substrate 2 can be silicon nitride or silicon oxide, or a double layer composed of a silicon nitride film and a silicon oxide film. The layer structure, wherein the thickness of the silicon nitride film can be 200-300nm, and the thickness of the silicon oxide film can be 150-200nm;”, where one would choose the total thickness to be about 350nm.) of a second insulating layer (see Qu Fig. 1, interlayer insulating layer 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to define the ranges of the thicknesses of the layers of the combined device of Kim and Park with the ranges taught by Qu in order to simplify the manufacture process by having the same thicknesses for like-material layers.
With respect to claim 7, Kim, Park, and Qu teach the display panel according to claim 6, wherein the thickness (about a total thickness of 350nm) of the buffer layer (see Kim Fig. 3, passivation layer 20) is equal to the thickness (about a total thickness of 350nm) of the second insulating layer (see Kim Fig. 3, cover insulating layer 60).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Park, in view of Joo et al. (Pub. No.: US 20230320162 A1), hereinafter as Joo.
With respect to claim 9, Kim and Park teach the display panel according to claim 1, wherein the base substrate (see Kim Fig. 3, window WD) further comprises: a layer (see Kim Fig. 3, light control pattern CCF) between the plurality of light-emitting devices (see Kim Fig. 3, light emitting element OLED) and the driving circuit layer (see Kim Fig. 3, circuit element layer DP-CL); wherein the layer comprises: a light-transmitting material (base resin, see Kim [0120] and [0125]), and scattering particles (scattering particles, see Kim [0120] and [0125]) dispersed in the light-transmitting material (see Kim [0120] and [0125]: “The light control pattern CCF may be a color conversion pattern ...” “The color conversion pattern may further include scattering particles mixed with the base resin, similar to the above-described transmission pattern. The scattering particles may include (e.g., may be) titanium oxide (TiO2) or silica-based nanoparticles.”).
Kim and Park do not teach that the layer is a planarization layer.
Joo teaches a planarization layer (see Joo Fig. 16, planarization layer PNL-E); wherein the planarization layer comprises: a light-transmitting material (see Joo [0234]: "The planarization layer PNL-E may be located between a circuit element layer DP-CL and a display element layer DP-OLED and cover the color filter layer CFL and the quantum dot layer QDL. In the embodiment, the planarization layer PNL-E may include an organic material and scattering agents SP dispersed in the organic material."), and scattering particles (see Joo [0234]) dispersed in the light-transmitting material (see Joo Fig. 16 and Joo [0234]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the layer of the combined device of Kim and Park with the planarization layer taught by Joo in order to simplify manufacturing by making the layer planar and allowing the layers above to form a uniform thickness more easily.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Park, and Joo, in view of Liao et al. (Pub. No.: US 20160190498 A1), hereinafter as Liao.
With respect to claim 10, the combined device of Kim, Park, and Joo teaches the display panel according to claim 9.
The combined device of Kim, Park, and Joo does not teach that a mass of the scattering particles is in a range of 5% to 10% of a total mass of the planarization layer.
Liao teaches that a planarization layer (see Liao Fig. 1, second scattering layer 15) comprises: a light-transmitting material (see Liao [0057]: “In an embodiment, the second polymer is made of a transparent material having a light transmittance greater than 80%. In a non-limiting embodiment, the second polymer is made of at least one selected from the group consisting of acrylic resin, epoxy resin, oxetane resin, silazane or siloxane resin, cyclic polyether compound, polymer with a hydroxyl group, and polyimide.”), and scattering particles (see Liao [0058]: “The second micro-particles are made of oxide compound or a material making up the third polymer, wherein the oxide compound may comprise silica, aluminum oxide, zirconium dioxide and titanium dioxide. The material of the third polymer may comprise poly methyl methacrylate.”) dispersed in the light-transmitting material (see Liao [0056]: “The second scattering layer 15 has a second polymer and a plurality of second micro-particles, the second micro-particles are 3 to 50 wt % of the second scattering layer.”), wherein a mass of the scattering particles is in a range of 5% to 10% of a total mass of the planarization layer (see Liao [0068]: “Subsequently, the polymer is applied on the transparent encapsulating material by the doctor blade method, to complete the formation of the second scattering layer having a film thickness ranged from 300 nm to 30 μm, wherein the silica micro-particles are in an amount of 9 wt % by the total weight of the second scattering layer. The amount of the silica micro-particles added in can be adjusted from 3 to 50 wt %.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a mass fraction of the scattering particles between 5% and 10% of the total weight of the planarization layer. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Lin (Pub. No.: US 20220037415 A1), in further view of Park et al. (Pub. No.: US 20220130922 A1), hereinafter as Park.
With respect to claim 11, Kim teaches a method of manufacturing a display panel, comprising: forming a driving circuit layer (see Kim Fig. 3, circuit element layer DP-CL) on a side of a base substrate (see Kim Fig. 3, window WD); wherein the driving circuit layer comprises: a light-transmitting portion (see Kim Fig. 3, emission area PXA); the light-transmitting portion comprises a low-refractive-index light-transmitting insulating layer (see Kim Fig. 3, silicon oxide layer in buffer layer 30) and a high-refractive-index light-transmitting insulating layer (silicon nitride layer in buffer layer 30) that are alternately stacked (see Kim Fig. 3, buffer layer 30; and see Kim [0106]: “In some embodiments, in the buffer layer 30, a silicon oxide layer and a silicon nitride layer may be alternately laminated.”); and a refractive index of the low-refractive-index light-transmitting insulating layer is smaller than a refractive index of the high-refractive-index light-transmitting insulating layer (let the silicon nitride layer be Si3N4, SiN (Silicon nitride), which has refractive index of 2.0458, and let the silicon oxide layer be SiO2 (Silicon dioxide, Silica, Quartz), which has refractive index of 1.4498, which is smaller than silicon nitride’s refractive index. See Polyanskiy.); and forming a plurality of light-emitting devices (see Kim Fig. 5, light emitting element OLED; and see Kim [0148]: “FIG. 4 is a plan view of the display panel according to an embodiment of the present disclosure. FIG. 5 is a cross-sectional view taken along the line II-II′ of FIG. 4. FIG. 4 illustrates six emission areas PXA-R, PXA-G, and PXA-B included in two pixel rows PXL as an example. In FIG. 5, the driving transistor T1 and the capacitor Cst illustrated in FIG. 3 are omitted for convenience of illustration.”) on a side of the driving circuit layer facing away from the base substrate (see Kim Fig. 3); wherein a surface of the light-emitting device facing the base substrate is a light exiting surface of the light-emitting device (see Kim [0095]: “In FIG. 3, a direction in which light generated from the light emitting element OLED is provided to the window WD is indicated by a bolded arrow.”); and the light-transmitting portion corresponds to a light-emitting area of the light-emitting device (see Kim Fig. 3); wherein the forming the driving circuit layer (see Kim Fig. 3, circuit element layer DP-CL) on the side of the base substrate (see Kim Fig. 3, window WD), specifically comprises: forming a buffer layer (see Kim Fig. 3, passivation layer 20) on the side of the base substrate (see Kim Fig. 3); forming a first insulating layer (see Kim Fig. 3, intermediate insulating layer 50) on a side of the buffer layer facing away from the base substrate (see Kim Fig. 3); and forming a second insulating layer (see Kim Fig. 3, cover insulating layer 60) on a side of the first insulating layer facing away from the base substrate (see Kim Fig. 3).
Kim does not teach that a refractive index of the buffer layer is smaller than a refractive index of the base substrate; wherein a refractive index of the first insulating layer is greater than the refractive index of the buffer layer; wherein a refractive index of the second insulating layer is smaller than the refractive index of the first insulating layer; wherein the first insulating layer, the buffer layer and the second insulating layer comprise a same material.
Park teaches that a refractive index of a first insulating layer (see Park Fig. 8, first interlayer insulating layer ILD1; and see Park [0155] and [0153]: “The first interlayer insulating layer ILD1 may include the same material as that of the gate insulating layer GI, or may include one or more materials selected from the materials illustrated as constituent materials of the gate insulating layer GI.”; “The gate insulating layer GI may be an inorganic insulating film including an inorganic material. For example, the gate insulating layer GI may include at least one of metal oxides or metal nitrides such as a silicon nitride (SiNx), a silicon oxide (SiOx), a silicon oxynitride (SiOxNy), and an aluminum oxide (AlOx).”; let the first insulating layer comprise of silicon nitride. Silicon nitride has the refractive index of 1.9827 according to Polyanski.) is greater than a refractive index of a buffer layer (see Park Fig. 8, buffer layer BFL; and see Park [0148] “The buffer layer BFL may be an inorganic insulating film including an inorganic material. The buffer layer BFL may include at least one of metal oxides such as a silicon nitride (SiNx), a silicon oxide (SiOx), a silicon oxynitride (SiOxNy), and an aluminum oxide (AlOx). The buffer layer BFL may be provided as a single film, but may be provided as a multifilm of at least double or more films. When the buffer layer BFL is provided as the multi-film, respective layers thereof may be made of the same material or different materials.”; let the buffer layer comprise of a layer of silicon nitride and a layer of silicon dioxide. The refractive index across both layers is 1.6734, which is less than silicon nitride’s refractive index. The following shows the derivation of the refractive index of a layer consisting of a silicon nitride layer and a silicon dioxide layer:
The refractive index formula is
n
=
c
v
or
n
v
=
c
, where c is the speed of light and v is the velocity of light through a medium. According to Polyanski,
n
S
i
O
2
=
1.4476
and
n
S
i
N
=
1.9827
. Let there be two layers, one comprising
S
i
O
2
and another
S
i
N
, with both layers being of similar thickness. In order to find the index of refraction across both layers, the average velocity is needed. For
S
i
O
2
,
v
1
≈
2.0724
×
10
8
m
s
. For
S
i
N
,
v
2
≈
1.5131
×
10
8
m
s
.
v
a
v
g
=
v
1
+
v
2
2
=
1.79275
×
10
8
m
s
n
t
o
t
a
l
=
c
v
a
v
g
=
1.6734
So, the refractive index across the two layers is roughly 1.6734.); wherein a refractive index of a second insulating layer (see Park Fig. 8, second interlayer insulating layer ILD2; and see Park [0156]: “In some embodiments, the second interlayer insulating layer ILD2 may include the same material as the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto. The second interlayer insulating layer ILD2 may be provided as a single film, or may be provided as a multi-film of at least double or more films.”; see Park [0155] and [0153] for ILD1 materials. Let the second insulating layer comprise of a layer of silicon nitride and a layer of silicon dioxide. The refractive index across both layers is 1.6734 (see above derivation).) is smaller than the refractive index of the first insulating layer (the refractive index 1.6734 is less than silicon nitride’s refractive index.); wherein the first insulating layer (Park Fig. 8, first interlayer insulating layer ILD1), the buffer layer (Park Fig. 8, buffer layer BFL) and the second insulating layer (Park Fig. 8, second interlayer insulating layer ILD2) comprise a same material (See Park [0148], [0153], [0155], and [0156]. Earlier, the buffer and insulating layer were chosen to have at least one layer of silicon nitride, therefore all comprising a same material.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the materials of Kim with materials taught by Park in order to simplify the manufacturing process by having fewer materials for multiple layers.
However, Kim and Park do not teach that a refractive index of the buffer layer is smaller than a refractive index of the base substrate.
Lin teaches a refractive index (see Lin [0032]: "The material of the substrate 102 may include, for example, glass, ceramic, quartz, sapphire, ... , other suitable materials or combinations thereof, but not limited thereto.", where one would choose sapphire, which has a refractive index of 1.7390 (see Polyanski).) of a base substrate (see Lin Fig. 1, substrate 102).
Together, Kim, Park, and Lin teach a refractive index (the refractive index across both layers is 1.6734 (see above derivation)) of the buffer layer (see Kim Fig. 3, passivation layer 20) is smaller than a refractive index (sapphire has a refractive index of 1.7390, which is greater than the buffer layer’s refractive index of 1.6734.) of the base substrate (see Kim Fig. 3, window WD).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the material used for the substrate of the combined device of Kim and Park with the material taught by Lin in order to utilize sapphire’s strong dielectric properties, remarkable thermal stability, and resistance to chemical attack (see Polyanski, Additional Information About Aluminum sesquioxide).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Park, and Lin, in view of Joo et al. (Pub. No.: US 20230320162 A1), hereinafter as Joo.
With respect to claim 14, Kim, Park, and Lin teach the method according to claim 11, wherein before forming the plurality of light-emitting devices (see Kim Fig. 5, light emitting element OLED; and see Kim [0148]), the method further comprises: forming a planarization layer (see Kim Fig. 3, light control pattern CCF) on the side of the driving circuit layer (see Kim Fig. 3, circuit element layer DP-CL) facing away from the base substrate (see Kim Fig. 3, window WD); wherein the planarization layer comprises: a light-transmitting material (base resin, see Kim [0120] and [0125]), and scattering particles (scattering particles, see Kim [0120] and [0125]) dispersed in the light-transmitting material (see Kim [0120] and [0125]: “The light control pattern CCF may be a color conversion pattern ...” “The color conversion pattern may further include scattering particles mixed with the base resin, similar to the above-described transmission pattern. The scattering particles may include (e.g., may be) titanium oxide (TiO2) or silica-based nanoparticles.”).
Kim, Park, and Lin do not teach that the layer is a planarization layer.
Joo teaches a planarization layer (see Joo Fig. 16, planarization layer PNL-E); wherein the planarization layer comprises: a light-transmitting material (see Joo [0234]: "The planarization layer PNL-E may be located between a circuit element layer DP-CL and a display element layer DP-OLED and cover the color filter layer CFL and the quantum dot layer QDL. In the embodiment, the planarization layer PNL-E may include an organic material and scattering agents SP dispersed in the organic material."), and scattering particles (see Joo [0234]) dispersed in the light-transmitting material (see Joo Fig. 16 and Joo [0234]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention modify the layer of the combined device of Kim, Park, and Lin with the planarization layer taught by Joo in order to simplify manufacturing by making the layer planar and allowing the layers above to form a uniform thickness more easily.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (Pub. No.: US 20220077256 A1), hereinafter as Lim, in view of Kim and Park.
With respect to claim 15, Lim teaches a display apparatus comprising a display panel (see Lim Fig. 1, display device 10; and see Lim [0063]: “The display device 10 according to an embodiment includes the display panel 100, a display driving circuit 200, a circuit board 300, and a touch driving circuit 400.”).
Lim does not teach the display panel according to claim 1.
Kim and Park teach the display panel according to claim 1 (see above claim 1 rejection).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the display panel of Lim with the display panel taught by the combined device of Kim and Park in order to minimize the number of layers needed and simplify the manufacturing process.
Allowable Subject Matter
Claim 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not teach or render obvious forming silicon oxide as the buffer layer on the side of the base substrate by using a chemical vapor deposition process under a condition that a ratio of silane to nitrous oxide is a first preset ratio; wherein the forming the first insulating layer on the side of the buffer layer facing away from the base substrate, specifically comprises: forming silicon oxide as the first insulating layer on the side of the buffer layer facing away from the base substrate by using the chemical vapor deposition process under a condition that a ratio of silane to nitrous oxide is a second preset ratio; wherein the first preset ratio is greater than the second preset ratio; wherein the forming the second insulating layer on the side of the first insulating layer facing away from the base substrate, specifically comprises: forming silicon oxide as the second insulating layer on the side of the first insulating layer facing away from the base substrate by using the chemical vapor deposition process under the condition that the ratio of silane to nitrous oxide is the first preset ratio as claimed.
Response to Arguments
Applicant's arguments filed 9/01/2026 have been fully considered but they are not persuasive.
Applicant argues that “the second interlayer insulating layer ILD2 is located on a side, facing the substrate SUB, of the source electrode SE and the drain electrode DE. However, unlike Park, in claim 1, a second insulating layer is on a side, facing away from the base substrate, of the source electrode and the drain electrode. Therefore, the second interlayer insulating layer ILD2 in Park cannot be regarded as the second insulating layer of claim 1.” This is not found persuasive because the vertical surfaces of Park’s first terminal SE and second terminal DE can be considered as “a side, facing away from the base substrate, of the source electrode and the drain electrode” wherein Park’s second interlayer insulating layer ILD2 is on and so continues to read on the limitation.
Applicant argues that “Park merely lists candidate materials that may be used for the buffer layer BFL, the first interlayer insulating layer ILD 1 and the second interlayer insulating layer ILD2, without specifying any particular assignment of those materials to individual layers. Park provides no teaching or suggestion to arrange these layers such that the refractive index of the first interlayer insulating layer ILD 1 is greater than the refractive indexes of the buffer layer BFL and the second interlayer insulating layer ILD2.” This is not found persuasive because it is unnecessary for prior art to further assign specific materials to a layer when said materials are already stated in a finite list for said layer. While Park may not specify the refractive index for each material, evidence is supplied through Polyanski’s database for refractive indexes of various materials.
Applicant argues that “nowhere does Park teach or suggest that the buffer layer BFL, the first interlayer insulating layer ILD 1 and the second interlayer insulating layer ILD2 include the same material.” This is not found persuasive because, again, it is unnecessary for prior art to further assign specific materials to a layer when said materials are already stated in a finite list for said layer. One of ordinary skill in the art would choose to use the least amount of different materials used in order to keep the process of manufacturing simple and cost-effective.
As the arguments are not found persuasive, the rejections are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EKATERINA T BIRCH whose telephone number is (571)272-8676. The examiner can normally be reached Mon-Fri, 8am-4pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at 5712721657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights