DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Claims 1-30 filed on April 03, 2024 are pending, claims 16-30 are new and claims 1-15 are canceled.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d) and certified copy of paper required by 37 CFR 1.55 is received.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 03, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and an initialed and dated copy of the Applicant’s IDS form 1449 is attached to the instant Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "said protocol" in line 4. There is insufficient antecedent basis for this limitation in the claim. It is not clear said protocol referring to a standard communication protocol in line 1 or a different protocol. Claims 17-30 are similarly rejected based upon claim dependency to claim 16.
Claim 1 recites the limitation "the " in line . There is insufficient antecedent basis for this limitation in the claim. Claim 25 is similarly rejected based upon claim dependency to claim 18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-22 and 25-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zakrzewski (US 2011/0255528 A1, hereinafter "Zakrzewski") in view of Sela et al. (US 2021/0392065 A1, hereinafter "Sela") .
Regarding claim 16, Zakrzewski discloses a device for wireless communication according to a standard communication protocol, said device being adapted to operate at the Physical layer and/or Medium Access Control layer of said protocol, and comprising a Wireless Network Interface Controller, abbreviated WNIC, said WNIC (Fig. AP [0049] processor 62 and handle wireless communication between the AP 32 and the sensors 34-36) comprising:
a transmitter adapted to transmit wireless signals according to said standard communication protocol (Zakrzewski, Fig. 2B a transceiver 64 [0049] communicate with one or more of the sensors 34-36);
a receiver adapted to receive wireless signals according to said standard communication protocol (Zakrzewski, Fig. 2B a transceiver 64 [0049] communicate with one or more of the sensors 34-36);
a WNIC clock, implementing a local timer according to said standard communication protocol, said WNIC clock (Zakrzewski, [0040] the clock values sent from the central node) being adapted to generate a clock time based on a reference time and a clock frequency (Zakrzewski, [0040] Based on the clock values sent from the central node, the internal clocks of the sensors may be synchronized through clock adjustment) and comprising a counter (Zakrzewski, [0061] the flow chart 130 begins at a step 132 where a counter, C, is initialized to one), and said device further comprising: an offset correction unit adapted to correct said reference time of said WNIC clock based on said offset correction information (Zakrzewski, claim 16 executable code that determines a relative clock offset of the first wireless device and the second wireless device using a set of timestamps including the first timestamp, the second timestamp, the third timestamp and the fourth timestamp); Zakrzewski discloses clock drift rate (i.e. skew) but does not explicitly disclose an interface adapted to receive offset correction information and skew correction information from one or more protocol layers higher than said Medium Access Control layer, said skew correction information comprising a skew correction value and a skew correction unit adapted to correct said frequency of said WNIC clock based on said skew correction information, by periodically adjusting said counter of said WNIC clock based on said skew correction value.
Sela from the same field of endeavor discloses an interface adapted to receive offset correction information and skew correction information from one or more protocol layers higher than said Medium Access Control layer, said skew correction information comprising a skew correction value (Sela, [0059] the functionality of the network device 12 and the host computer 14 may be combined in any suitable network device, for example, a network switch including a CPU which runs PTP software (i.e. higher than MAC) As well as Fig. 1 18) and a skew correction unit adapted to correct said frequency of said WNIC clock based on said skew correction information, by periodically adjusting said counter of said WNIC clock based on said skew correction value (Sela, [0056] Block lock is defined as completing a linkup process, which may include locking onto to an incoming bit stream, align to where a block starts and ends, and de-skewing over several lanes).
It would have been obvious for one with ordinary skill in the art before the effective filing date of the claimed invention to have modified Synchronizing disclosed by Zakrzewski and timestamp accuracy disclosed by Sela with a motivation to make this modification in order to remove errors and increase accuracy (Sela, [0047]).
Regarding claim 17, Zakrzewski discloses wherein said device is adapted to generate a clock time being corrected for offset and skew, while only relying on said WNIC clock, without using any dedicated hardware clock (Zakrzewski, [0008] the relative clock offsets of the wireless devices determined by the access point).
Regarding claim 18, Zakrzewski discloses wherein said standard communication protocol is a Wi-Fi protocol defined by the IEEE 802.11 standard, and said WNIC clock is the Time Synchronization Function clock, abbreviated TSF clock, defined by said IEEE 802.11 standard and embedded in a Wi-Fi WNIC (Zakrzewski, [0005] in the IEEE 802.11 standard, the time synchronization function (TSF) provides synchronization in connection with beacon messages transmitted periodically by a single node).
Regarding claim 19, Zakrzewski discloses wherein said device comprises a timestamping unit for hardware timestamping, said timestamping unit being adapted to generate a timestamp upon receipt of a data packet by said receiver and/or upon transmission of a data packet by said transmitter (Zakrzewski, [0010] the first timestamp, the second timestamp, and a third timestamp corresponding to the sending of the synchronization response by the second wireless device).
Regarding claim 20, Zakrzewski discloses wherein said offset correction information and said skew correction information are values resulting from a clock synchronization algorithm implemented at said one or more higher protocol layers (Zakrzewski, [0011] a computer readable storage medium stores computer software that synchronizes a first wireless device and a second wireless device, the computer software including executable code that sends a synchronization message from the first wireless device to the second wireless device, wherein the synchronization message includes a first timestamp generated by the first wireless device), and said device comprises a second interface, adapted to return timestamps generated by said timestamping unit to said one or more higher protocol layers, for use by said clock synchronization algorithm (Zakrzewski, [0011] Executable code may be provided that receives the synchronization message at the second wireless device, wherein the second wireless device records a second timestamp corresponding to the synchronization message that is received).
Regarding claim 21, Zakrzewski does not explicitly disclose wherein said clock synchronization algorithm is defined by a Precision Time Protocol, abbreviated PTP.
Sela from the same field of endeavor discloses wherein said clock synchronization algorithm is defined by a Precision Time Protocol, abbreviated PTP (Sela, [0003] The Precision Time Protocol (PTP) was conceived as a solution to this problem. This protocol enables network nodes).
It would have been obvious for one with ordinary skill in the art before the effective filing date of the claimed invention to have modified Synchronizing disclosed by Zakrzewski and timestamp accuracy disclosed by Sela with a motivation to make this modification in order to remove errors and increase accuracy (Sela, [0047]).
Regarding claim 22, Zakrzewski discloses wherein said skew correction value corresponds to a limit duration upon which said timer of said WNIC clock is adjusted (Zakrzewski, [0040] Those clock values may then be used in connection with the timing of data acquisition commands sent to the sensors. Based on the clock values sent from the central node, the internal clocks of the sensors may be synchronized through clock adjustment).
Regarding claim 25, Zakrzewski discloses wherein said Wi-Fi WNIC comprises an adjustment unit adapted to adjust said reference time of said TSF clock according to the TSF standard (Zakrzewski, [0005] in the IEEE 802.11 standard, the time synchronization function (TSF) provides synchronization in connection with beacon messages transmitted periodically by a single node), and said device is adapted to correct said reference time of said WNIC clock by providing said offset correction information as an input to said adjustment unit (Zakrzewski, [0040] the internal clocks of the sensors may be synchronized through clock adjustment and/or the data acquisition commands may be sent to different sensor devices specifying different starting times according to the calculated relative offsets of the different sensor devices in a way that causes the different sensor devices to act at the same physical time instant).
Regarding claim 26, Zakrzewski does not explicitly disclose wherein said skew correction unit is implemented by means of a Field-Programmable Gate Array, abbreviated FPGA.
Sela from the same field of endeavor discloses wherein said skew correction unit is implemented by means of a Field-Programmable Gate Array, abbreviated FPGA (Sela, [0058] The computer system 10 includes a network device 12 ( e.g., a NIC)… These physical components may comprise hard-wired or programmable devices, or a combination of the two).
It would have been obvious for one with ordinary skill in the art before the effective filing date of the claimed invention to have modified Synchronizing disclosed by Zakrzewski and timestamp accuracy disclosed by Sela with a motivation to make this modification in order to remove errors and increase accuracy (Sela, [0047]).
Regarding claim 27, Zakrzewski discloses a device according to claim 19;
but does not explicitly disclose a processor adapted to operate at one or more protocol layers higher than said Medium Access Control layer, said processor implementing computer-executable instructions for causing said apparatus to perform clock synchronization with respect to a master clock, said clock synchronization comprising:
instructing said transmitter and receiver to perform a two-way packet exchange with another apparatus, said other apparatus comprising said master clock, while timestamping transmitted and received packets by said timestamping unit;
calculating said offset correction information and said skew correction information from timestamps generated by said timestamping unit;
transmitting said offset correction information and said skew correction information to said device through said interface.
Sela from the same field of endeavor discloses a processor adapted to operate at one or more protocol layers higher than said Medium Access Control layer, said processor implementing computer-executable instructions for causing said apparatus to perform clock synchronization with respect to a master clock (Sela, [0062] The hardware clock 26 is configured to maintain a clock value, according to any suitable time standard, such as Coordinated Universal Time (UTC)), said clock synchronization comprising:
instructing said transmitter and receiver to perform a two-way packet exchange with another apparatus, said other apparatus comprising said master clock, while timestamping transmitted and received packets by said timestamping unit (Sela, );
calculating said offset correction information and said skew correction information from timestamps generated by said timestamping unit (Sela, [0003] using messaging between the nodes and a master device, to determine the offset of their respective clocks to levels of accuracy in the nanosecond range… accuracy in measuring the clock offsets, hardware-based time stamping is generally used);
transmitting said offset correction information and said skew correction information to said device through said interface (Sela, [0059] the functionality of the network device 12 and the host computer 14 may be combined in any suitable network device, for example, a network switch including a CPU which runs PTP software (i.e. higher than MAC) As well as Fig. 1 18).
It would have been obvious for one with ordinary skill in the art before the effective filing date of the claimed invention to have modified Synchronizing disclosed by Zakrzewski and timestamp accuracy disclosed by Sela with a motivation to make this modification in order to remove errors and increase accuracy (Sela, [0047]).
Regarding claim 28, Zakrzewski does not explicitly disclose wherein said clock synchronization is defined by a Precision Time Protocol, abbreviated PTP, and said apparatus is adapted to obtain a PTP synchronized clock time while only relying on said WNIC clock.
Sela from the same field of endeavor discloses wherein said clock synchronization is defined by a Precision Time Protocol, abbreviated PTP, and said apparatus is adapted to obtain a PTP synchronized clock time while only relying on said WNIC clock (Sela, [0058] The computer system 10 includes a network device 12 ( e.g., a NIC) connected to a host computer 14. The host computer 14 includes a processor 16 to perform various processing tasks, optionally including running PTP software).
It would have been obvious for one with ordinary skill in the art before the effective filing date of the claimed invention to have modified Synchronizing disclosed by Zakrzewski and timestamp accuracy disclosed by Sela with a motivation to make this modification in order to remove errors and increase accuracy (Sela, [0047]).
Regarding claim 29, Zakrzewski does not explicitly disclose wherein said apparatus contains two different hardware clocks, corresponding to a system clock and said WNIC clock respectively, and said apparatus does not contain a dedicated PTP hardware clock for providing a synchronized time.
Sela from the same field of endeavor discloses wherein said clock synchronization is defined by a Precision Time Protocol, abbreviated PTP, and said apparatus is adapted to obtain a PTP synchronized clock time while only relying on said WNIC clock (Sela, [0090] The processor 16 (FIG. 1) of the host computer 14 is configured to run software instructions of the PTP software 18 to: receive (block 132) time synchronization message(s); compute (block 134) an adjustment 138 to the clock value (e.g., drift) of the hardware clock 26 responsively to the time synchronization message(s)).
It would have been obvious for one with ordinary skill in the art before the effective filing date of the claimed invention to have modified Synchronizing disclosed by Zakrzewski and timestamp accuracy disclosed by Sela with a motivation to make this modification in order to remove errors and increase accuracy (Sela, [0047]).
Regarding claim 30, Zakrzewski discloses providing an apparatus according to claim 27;
initiating a two-way packet exchange by said transmitter and receiver, said two-way packet exchange being performed with another apparatus comprising said master clock, while timestamping transmitted and received packets by said timestamping unit (Zakrzewski, [0008] In response to a request from the access point, each of the wireless devices sends a response to the access point that includes the timestamps corresponding to the reference messages received at each of the wireless device);
transmitting timestamps generated by said timestamping unit to a clock synchronization algorithm implemented at said one or more higher protocol layers (Zakrzewski, [0011] a computer readable storage medium stores computer software that synchronizes a first wireless device and a second wireless device, the computer software including executable code that sends a synchronization message from the first wireless device to the second wireless device, wherein the synchronization message includes a first timestamp generated by the first wireless device);
calculating said offset correction information and said skew correction information by said clock synchronization algorithm, comprising calculating said skew correction value (Zakrzewski, [0091] the clock drift rate (i.e. skew) may be estimated in addition to the instantaneous clock offset using known clock drift estimating techniques based on a number of individual clock offset observations; claim 16 executable code that determines a relative clock offset of the first wireless device and the second wireless device using a set of timestamps including the first timestamp, the second timestamp, the third timestamp and the fourth timestamp).
Zakrzewski does not explicitly disclose transmitting said offset correction information, and said skew correction information comprising said skew correction value, to said device through said interface;
correcting said reference time of said WNIC clock, by said offset correction unit, based
on said offset correction information;
correcting said frequency of said WNIC clock by said skew correction unit based on said skew correction information, by periodically adjusting said counter of said WNIC clock based on said skew correction value;
obtaining a synchronized clock time from said WNIC clock.
Sela from the same field of endeavor discloses transmitting said offset correction information, and said skew correction information comprising said skew correction value, to said device through said interface; correcting said reference time of said WNIC clock, by said offset correction unit, based on said offset correction information (Sela, [0059] the functionality of the network device 12 and the host computer 14 may be combined in any suitable network device, for example, a network switch including a CPU which runs PTP software (i.e. higher than MAC) As well as Fig. 1 18) and correcting said frequency of said WNIC clock by said skew correction unit based on said skew correction information, by periodically adjusting said counter of said WNIC clock based on said skew correction value; obtaining a synchronized clock time from said WNIC clock (Sela, [001856] the receive PHY pipeline circuitry is configured to compute the adjustment responsively to the counter value multiplied by a symbol period of the symbolsBlock lock is defined as completing a linkup process, which may include locking onto to an incoming bit stream, align to where a block starts and ends, and de-skewing over several lanes).
It would have been obvious for one with ordinary skill in the art before the effective filing date of the claimed invention to have modified Synchronizing disclosed by Zakrzewski and timestamp accuracy disclosed by Sela with a motivation to make this modification in order to remove errors and increase accuracy (Sela, [0047]).
Claim(s) 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zakrzewski (US 2011/0255528 A1, hereinafter "Zakrzewski") in view of Sela et al. (US 2021/0392065 A1, hereinafter "Sela") as applied to claim above, and further in view of Aweya (WO 2015/087024 A1, hereinafter "Aweya").
Regarding claim 23, Zakrzewski in view of Sela discloses skew correction but does not explicitly disclose wherein said skew correction unit comprises a Skew Correction Counter adapted to increment with said counter of said WNIC clock, and to overflow upon reaching said skew correction value, and wherein said skew correction unit is adapted to adjust said counter of said WNIC clock upon overflow of said Skew Correction Counter.
Aweya from the same field of endeavor discloses a Skew Correction Counter adapted to increment with said counter of said WNIC clock, and to overflow upon reaching said skew correction value, and wherein said skew correction unit is adapted to adjust said counter of said WNIC clock upon overflow of said Skew Correction Counter (Aweya, pg. 25 line 4-9 The skew-adjusted free-running counter 34 output can be used to schedule a pulse at a precise future time, for example, for event scheduling. It can also be used to generate a pulse train as illustrated in Figure 14 and Figure 15).
It would have been obvious for one with ordinary skill in the art before the effective filing date of the claimed invention to have to include the teachings of Aweya’s system for linear synchronization process into Zakrzewski’s synchronization process as modified by Sela with a motivation to make this modification in order to improve performance compared to other existing algorithm (Aweya, pg. 4).
Regarding claim 24, Zakrzewski in view of Sela discloses skew correction but does not explicitly disclose wherein said skew correction unit comprises a Skew Correction Register adapted to load said skew correction value.
Aweya from the same field of endeavor discloses wherein said skew correction unit comprises a Skew Correction Register adapted to load said skew correction value (Aweya, pg. 25 line 9-15 Particularly, the skew-adjusted free-running counter 34 output can be used to output a digitally synthesized clock signal at a programmable frequency for telecom systems. PDH/SDH reference frequencies are not integral factors of 125 MHz, thus requiring the counter clock signal to be synthesized using a host processor-programmable event period register 53 programmed with the correct period of the telecom clock signal. The event period register 53 indicates when to issue the clock pulse from a starting point determined by scheduled event register 51).
It would have been obvious for one with ordinary skill in the art before the effective filing date of the claimed invention to have to include the teachings of Aweya’s system for linear synchronization process into Zakrzewski’s synchronization process as modified by Sela with a motivation to make this modification in order to improve performance compared to other existing algorithm (Aweya, pg. 4).
Conclusion
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/LUNA WEISSBERGER/Examiner, Art Unit 2415