DETAILED ACTION
This office action is responsive to application 18/699,397 filed on April 8, 2024. Claims 1-28 are pending in the application.
Election/Restrictions
Applicant’s election without traverse of Species 1 (claims 1-27) in the reply filed on January 2, 2026 is acknowledged.
Claim 28 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 2, 2026.
Information Disclosure Statement
The Information Disclosure Statements (IDS) filed on 4/08/2024, 4/26/2024 and 11/21/2025 were received and have been considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-15 and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “the high capacitive element holds the voltage generated by a highest high conversion efficiency among the plurality of conversion efficiencies, and the low capacitive element holds the voltage generated by a conversion efficiency lower than the high conversion efficiency among the plurality of conversion efficiencies” at lines 7-10 thereof. It is unclear if “the high conversion efficiency” is referring to the “highest high conversion efficiency” or a different high conversion efficiency. As such, claim 2 is deemed indefinite by the Examiner. Claim 2 may be amended to instead recite “the high capacitive element holds the voltage generated by a highest high conversion efficiency among the plurality of conversion efficiencies, and the low capacitive element holds the voltage generated by a conversion efficiency lower than the highest high conversion efficiency among the plurality of conversion efficiencies” in order to overcome this rejection.
Claims 3-14 are indefinite as depending from claim 2 and not remedying the deficiencies of claim 2.
Claim 15 recites “the previous-stage circuit holds the reset level in one of the first and second capacitive elements within an exposure period of one of the pair of frames and then holds the signal level in the other of the first and second capacitive elements, and holds the reset level in the other of the first and second capacitive elements within an exposure period of the other of the pair of frames and then holds the signal level in one of the first and second capacitive elements”. However, based upon the claim construction of claim 1, the “previous-stage circuit” and the “plurality of capacitive elements” are separate elements. The plurality of capacitive elements are not recited as being part of the previous-stage circuit. As such, it is unclear how the previous-stage circuit can hold signals in the first and second capacitive elements. Therefore, claim 15 is deemed indefinite by the Examiner.
Claim 27 recites “the second exposure period” at lines 3 and 4 thereof. However, no second exposure period is previously recited in claim 27 or parent claim 1. As such, it is unclear what this recitation is referring to. Therefore, claim 27 is deemed indefinite by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 16, 17, 25 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Milkov et al. (US 2019/0327432).
Consider claim 1, Milkov et al. teaches:
A solid-state imaging element (see figures 1 and 7), comprising:
a previous-stage circuit (figure 1) that converts charges into a voltage using each of a plurality of conversion efficiencies (The first layer (i.e. previous-stage circuit) shown in figure 1 converts charges into a voltage using a first conversion efficiency when a low-gain select transistor (Mlg) is not activated and a second conversion efficiency when the low-gain select transistor (Mlg) is activated, paragraphs 0026, 0027 and 0029.) and outputs it to a previous-stage node (output node, 16, paragraph 0027);
a plurality of capacitive elements (sampling capacitors Cr_hg and Cs_lg, figure 7, paragraph 0063) whose one ends are connected to the previous-stage node in common (Node 30 in figure 7 is coupled to the previous-stage node (16), paragraph 0063. The left ends of Cr_hg and Cs_lg are connected to node 30 in common via sampling switches 72 and 82, respectively, figure 7, paragraphs 0063 and 0064.);
a selection circuit (HG select switch, 78, LG select switch, 88, figure 7) that connects the other end of one of the plurality of capacitive elements (Cr_hg, Cs_lg) to a subsequent-stage node (read node, 77, see figure 7, paragraphs 0063 and 0064); and
a subsequent-stage circuit (source follower, 42, row select switch, 46, figure 7) that reads the voltage via the subsequent-stage node (77, see figure 7, paragraphs 0063 and 0066).
Consider claim 16, and as applied to claim 1 above, Milkov et al. further teaches an analog-to-digital converter that converts the output voltage into a digital signal (“a column-parallel single-slope ADC” paragraph 0052).
Consider claim 17, and as applied to claim 16 above, Milkov et al. further teaches the analog-to-digital converter includes a comparator that compares a level of a vertical signal line for transmitting the voltage with a predetermined ramp signal and outputs a comparison result, and a counter that counts a count value over a period until the comparison result is inverted, and outputs the digital signal indicating the count value (“Alternatively, it may be a part of a column-parallel single-slope ADC, wherein the HG and LG outputs are fed to two different comparators such that the HG and LG pixel outputs are compared against a ramp voltage. A selection is made between the HG and LG comparator outputs depending on the time at which each comparator trips. The selected comparator output is used to latch the value of a counter, which is a digital representation of the HG or LG pixel output.” paragraph 0052).
Consider claim 25, and as applied to claim 1 above, Milkov et al. further teaches that the voltage includes a first reset level generated immediately before end of a first exposure period, a first signal level generated at the end of the first exposure period (see “HG signal and reset levels”, paragraph 0063), a second reset level generated immediately before end of a second exposure period, and a second signal level generated at the end of the second exposure period (see “LG signal and reset levels”, see paragraph 0063), the plurality of capacitive elements include a first capacitive element that holds the first reset level (Cr_hg, figure 7), a second capacitive element that holds the first signal level (Cs_hg, figure 7), a third capacitive element that holds the second reset level (Cr_lg, figure 7), and a fourth capacitive element that holds the second signal level (Cs_lg, figure 7), the second exposure period is started immediately after the end of the first exposure period (see paragraph 0063, figure 2), and the subsequent-stage circuit (42, 46) reads the voltage while avoiding a sample-and-hold period of the voltage (see paragraphs 0063 and 0066).
Consider claim 27, and as applied to claim 1 above, Milkov et al. further teaches that the voltage includes a first reset level generated immediately before end of a first exposure period and a first signal level generated at the end of the first exposure period (see “HG signal and reset levels”, paragraph 0063), and a second signal level generated at end of the second exposure period (see “LG signal levels”, paragraph 0063), the plurality of capacitive elements include a first capacitive element that holds the first reset level (Cr_hg, figure 7), a second capacitive element that holds the first signal level (Cs_hg, figure 7), and a third capacitive element that holds the second signal level (Cs_lg, figure 7), the second exposure period is started immediately after the end of the first exposure period (see paragraph 0063, figure 2), and the subsequent-stage circuit (42, 46) reads the voltage while avoiding a sample-and-hold period of the voltage (see paragraphs 0063 and 0066).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Milkov et al. (US 2019/0327432) in view of Kaizu et al. (US 2012/0287294).
Consider claim 15, and as applied to claim 1 above, Milkov et al. further teaches that the plurality of capacitive elements include first and second capacitive elements (sampling capacitors Cr_hg and Cs_lg, figure 7, paragraph 0063), the voltage includes a reset level and a signal level, and the previous-stage circuit holds the reset level in one of the first and second capacitive elements within an exposure period of one of the pair of frames and then holds the signal level in the other of the first and second capacitive elements (see “HG signal and reset levels”, paragraph 0063), and holds the reset level in the other of the first and second capacitive elements within an exposure period of the other of the pair of frames and then holds the signal level in one of the first and second capacitive elements (see “LG signal and reset levels”, see paragraph 0063).
Milkov et al. does not explicitly teach a digital signal processing unit that adds a pair of consecutive frames.
Kaizu et al. similarly teaches an image pickup apparatus (figure 1) including an imaging element (image sensor, 102, paragraph 0009), and outputting a high sensitivity image (105) and a low sensitivity image (106), paragraph 0009.
However, Kaizu et al. further teaches a digital signal processing unit (HDR processing unit, 107) that adds a pair of consecutive frames (see paragraphs 0009 and 0010).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the imaging element taught by Milkov et al. include a digital signal processing unit as taught by Kaizu et al. for the benefit of enabling generation of an image with wide dynamic range (Kaizu et al., paragraph 0001).
Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Milkov et al. (US 2019/0327432) in view of Sakaguchi (US 2015/0341582).
Consider claim 20, and as applied to claim 1 above, Milkov et al. further teaches that a vertical scanning circuit that controls the previous-stage circuit to set a conversion efficiency (The conversion efficiency is set by applying a control signal (lgb) to a low-gain select transistor (Mlg), paragraph 0007. The application of the control signal (lgb) necessarily requires a vertical scanning circuit.), and the voltage includes a reset level and a signal level according to an exposure amount (“HG signal and reset levels”, “LG signal and reset levels”, paragraph 0063).
However, Milkov et al. does not explicitly teach that capacitance values of the plurality of capacitive elements are the same.
Sakaguchi similarly teaches an imaging element (figure 4) with a plurality of capacitive elements (231, 232, 233, 234, paragraph 0099).
However, Sakaguchi additionally teaches that capacitance values of the plurality of capacitive elements (231, 232, 233, 234) are the same (e.g. “equal to a value five times the capacitance value of the charge holding unit” paragraph 0099).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the capacitance values of the plurality of capacitive elements taught by Milkov et al. be the same as taught by Sakaguchi for the benefit of reducing an influence of signal deterioration due to a leak current (Sakaguchi, paragraph 0099).
Consider claim 21, and as applied to claim 20 above, Milkov et al. further teaches that the vertical scanning circuit sets one of the plurality of conversion efficiencies (The conversion efficiency is set by applying a control signal (lgb) to a low-gain select transistor (Mlg), paragraph 0007.), holds the reset (“reset”) level in half of the plurality of capacitive elements, and holds the signal level (“HG” or “LG”) in the other half of the plurality of capacitive elements (see paragraph 0063).
Allowable Subject Matter
Claims 18, 19, 22-24, 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2-14 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and upon remedying the 35 USC 112 rejection of claim 2 in the manner suggested herein by the Examiner.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 2, the prior art of record does not teach nor reasonably suggest that the plurality of capacitive elements include a high capacitive element whose capacitance value is higher than a predetermined value, and a low capacitive element whose capacitance value is lower than the predetermined value, the high capacitive element holds the voltage generated by a highest high conversion efficiency among the plurality of conversion efficiencies, and the low capacitive element holds the voltage generated by a conversion efficiency lower than the highest high conversion efficiency among the plurality of conversion efficiencies, in combination with the other elements recited in parent claim 1.
Claims 3-14 contain allowable subject matter as depending from claim 2.
Consider claim 18, the prior art of record does not teach nor reasonably suggest that the comparator includes a comparison device that compares levels of a pair of input terminals and outputs comparison results, and an input-side selector that selects either the vertical signal line or a node of a predetermined reference voltage and connects it to one of the pair of input terminals, and the ramp signal is input to one of the pair of input terminals, in combination with the other elements recited in parent claims 1, 16 and 17.
Claim 19 contains allowable subject matter as depending from claim 18.
Consider claim 22, the prior art of record does not teach nor reasonably suggest that the plurality of capacitive elements include a plurality of first capacitive elements, a plurality of second capacitive elements, and a plurality of third capacitive elements, and the vertical scanning circuit sets one of the plurality of conversion efficiencies, holds the reset level in half of the plurality of first capacitive elements, and holds the signal level in the plurality of second capacitive elements, in combination with the other elements recited in parent claims 1 and 20.
Consider claim 23, the prior art of record does not teach nor reasonably suggest that the plurality of capacitive elements include a plurality of first capacitive elements, a plurality of second capacitive elements, a plurality of third capacitive elements, and a plurality of fourth capacitive elements, and the vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies, holds the reset level generated by a higher one of the two conversion efficiencies in the plurality of first capacitive elements, holds the signal level generated by the higher one of the two conversion efficiencies in the plurality of second capacitive elements, holds the reset level generated by a lower one of the two conversion efficiencies in the plurality of third capacitive elements, and holds the signal level generated by the lower one of the two conversion efficiencies in the plurality of fourth capacitive elements, in combination with the other elements recited in parent claims 1 and 20.
Consider claim 24, the prior art of record does not teach nor reasonably suggest that the plurality of capacitive elements include a plurality of first capacitive elements, a plurality of second capacitive elements, a predetermined number of third capacitive elements smaller than the number of first capacitive elements, and the predetermined number of fourth capacitive elements, and the vertical scanning circuit sequentially sets two of the plurality of conversion efficiencies, holds the reset level generated by a higher one of the two conversion efficiencies in the plurality of first capacitive elements, holds the signal level generated by the higher one of the two conversion efficiencies in the plurality of second capacitive elements, holds the reset level generated by a lower one of the two conversion efficiencies in the predetermined number of third capacitive elements, and holds the signal level generated by the lower one of the two conversion efficiencies in the predetermined number of fourth capacitive elements, in combination with the other elements recited in parent claims 1 and 20.
Consider claim 26, the prior art of record does not teach nor reasonably suggest that the voltage further includes a third reset level generated immediately before end of a third exposure period and a third signal level generated at the end of the third exposure period, the plurality of capacitive elements further include a fifth capacitive element that holds the third reset level and a sixth capacitive element that holds the third signal level, and the third exposure period is started immediately after the end of the second exposure period, in combination with the other elements recited in parent claims 1 and 25.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miyauchi et al. (US 2023/0156369) teaches an imaging element having a plurality of capacitors which are respectively connected to selection circuits (see figure 21).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637