Prosecution Insights
Last updated: October 02, 2026
Application No. 18/699,668

SENSOR CHIP

Non-Final OA §103§112§DOUBLEPATENT
Filed
Apr 09, 2024
Priority
Aug 31, 2023 — nonprovisional of PCTCN2023116194
Examiner
MERCADO, ALEXANDER A
Art Unit
2855
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Beijing Boe Technology Development Co., Ltd.
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
426 granted / 614 resolved
+1.4% vs TC avg
Strong +20% interview lift
Without
With
+19.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
36 currently pending
Career history
646
Total Applications
across all art units

Statute-Specific Performance

§101
3.5%
-36.5% vs TC avg
§103
47.8%
+7.8% vs TC avg
§102
13.7%
-26.3% vs TC avg
§112
32.1%
-7.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 614 resolved cases

Office Action

§103 §112 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Subspecies 1.a. 2.a. and 3.a. in the reply filed on 9 May 2026 is acknowledged. Claims 9 – 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Specifically, Claim 9 (and as a result dependent Claims 10 and 11) are withdrawn as they pertains to Subspecies 2.c., Claim 12 is withdrawn as it pertains to Subspecies 2.d., 2.e., 3.b., and 3.c., Claim 13 is withdrawn as it pertains to Subspecies 2.e. and 3.c., Claim 14 (and as a result dependent Claims 15 – 17) are withdrawn as they pertain to Subspecies 1.c, 2.f. and 3.d., and Claim 18 (and as a result dependent Claims 19 and 20) are withdrawn as they pertain to Subspecies 2.g. and 3.e. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1 – 8 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1 - 5 of copending Application No. US 18/689,819 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because: Regarding Claim 1, all of the limitations are found in Claim 1 of the US application. Regarding Claim 2, all of the limitations are found in Claim 1 of the US application. Regarding Claim 3, all of the limitations are found in Claim 1 of the US application. Regarding Claim 4, all of the limitations are found in Claim 2 of the US application. Regarding Claim 5, all of the limitations are found in Claim 3 of the US application. Regarding Claim 6, all of the limitations are found in Claim 3 of the US application. Regarding Claim 7, all of the limitations are found in Claim 4 of the US application. Regarding Claim 8, all of the limitations are found in Claim 5 of the US application. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 7 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding Claim 7, the claim recites “the two piezoresistors”. Claim 1 sets forth a single piezoresistor. As such, it is unclear as to if the claim intends to introduce an additional piezoresistor or if the limitation pertains to the piezoresistor of Claim 1, thus rendering the claim indefinite. Claims dependent upon a rejected claim are therefore rejected as well. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 – 3, 5, 7, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fei et al. (CN 112798158), in view of Zook et al. (US 5275055). Citations pertaining to Fei refer to the attached English translation. Regarding Claim 1, Fei discloses a sensor chip, in at least Figure 1, comprising: a first base substrate (10); a piezoresistor (21) on the first base substrate (Figure 1); a second base substrate (30) on a side of the piezoresistor away from the first base substrate (Figure 1); a metal wire bond (61, 63) extending through the second base substrate (Figure 1); and a pressure reference chamber (1a) between the first base substrate and the second base substrate (Figure 1). Fei fails to expressly disclose the first base substrate and the second base substrate encapsulate at least a portion of the piezoresistor inside the pressure reference chamber as there is dielectric layer (40) between the first base substrate and pressure reference chamber. Zook teaches a piezoresistor (134) placed inside of a pressure reference chamber (126). As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the applicant’s invention that there is no need for a dielectric layer separating the piezoresistor from the pressure reference chamber and could be removed i.e. modifying Fei so that the first base substrate and the second base substrate encapsulate at least a portion of the piezoresistor inside the pressure reference chamber and would have been obvious for the benefit of reducing the thickness of the diaphragm (element 12 in Fei) allowing for better sensing of lower pressures and better sensitivity overall. Regarding Claim 2, Fei discloses a resistor lead (22) on the first base substrate (Figure 1); wherein the resistor lead is connected to the piezoresistor, and is connected to the metal wire bond (Figure 1). Regarding Claim 3, Fei discloses a redistribution layer (62) on a side of the second base substrate away from the first base substrate (Figure 1); wherein the redistribution layer is connected to the metal wire bond (Figure 1). Regarding Claim 5, Fei discloses a via extending through the second base substrate (via in which 61 lies) (Figure 1); wherein the metal wire bond is at least partially in the via (Figure 1). Regarding Claim 7, Fei discloses a pressure sensing layer configured to convert a pressure signal into a deformation signal [n0029]; wherein the pressure sensing layer comprises a portion of the first base substrate between the two piezoresistors (21 and other 21 to the right) (Figure 1); and the piezoresistor is configured to convert the deformation signal into an electrical signal [n0031]. Regarding Claim 8, Fei fails to expressly disclose a surface of the portion of the first base substrate between the two piezoresistors is exposed to the pressure reference chamber as there is dielectric layer (40) between the first base substrate and the pressure reference chamber. Zook teaches a first substrate surface (surface of 122) exposed to a pressure reference chamber (126). As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the applicant’s invention that there is no need for a dielectric layer separating the first substrate surface from the pressure reference chamber and could be removed i.e. modifying Fei so a surface of the portion of the first base substrate between the two piezoresistors is exposed to the pressure reference chamber and would have been obvious for the benefit of reducing the thickness of the diaphragm (element 12 in Fei) allowing for better sensing of lower pressures and better sensitivity overall. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fei et al. (CN 112798158), in view of Zook et al. (US 5275055), in further view of Tsai et al. (US 2021/0172813). Regarding Claim 4, Fei discloses a solder on a side away from the second base substrate (via 62) (Figure 1). Nevertheless, the combination fails to expressly disclose an under bump metallization on a side of the second base substrate away from the first base substrate; and a solder on a side of the under bump metallization away from the second base substrate and connected to the under bump metallization. Tsai teaches an under bump metallization (414) on a side of a second base substrate (104) away from a first base substrate (111) (Figure 4); and a solder (415) on a side of the under bump metallization away from the second base substrate and connected to the under bump metallization (Figure 4). As such, it would have been obvious to one of ordinary skill in the art to modify the combination so that an under bump metallization is on a side of the second base substrate away from the first base substrate; and a solder is on a side of the under bump metallization away from the second base substrate and connected to the under bump metallization for the benefit of maintaining signal integrity and longevity of the sensor. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fei et al. (CN 112798158), in view of Zook et al. (US 5275055), in further view of Lyu et al. (CN 115403005). Citations pertaining to Lyu refer to the attached English translation. Regarding Claim 6, the combination fails to expressly disclose the via has a trapezoidal shape with an included angle between a top side and a lateral side; and the included angle is in a range of 80 degrees to 90 degrees. Lyu teaches a via (501) has a trapezoidal shape with an included angle between a top side and a lateral side (Figure 6). As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the applicant’s invention to modify the combination so that the via has a trapezoidal shape with an included angle between a top side and a lateral side for the benefit of utilizing a known method of forming vias, as taught by Lyu [n0082]. Nevertheless, the combination fails to expressly disclose the angle is in a range of 80 to 90 degrees, however, one of ordinary skill in the art would have been motivated to select and angle, including 80 to 90 degrees to ensure adequate seed layer coverage. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER MERCADO whose telephone number is (571)270-7094. The examiner can normally be reached Monday - Thursday 9am - 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Laura Martin can be reached at (571) 272-2160. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. ALEXANDER A. MERCADO Primary Examiner Art Unit 2855 /ALEXANDER A MERCADO/ Primary Examiner, Art Unit 2855
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Prosecution Timeline

Apr 09, 2024
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §103, §112, §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
89%
With Interview (+19.6%)
2y 11m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 614 resolved cases by this examiner. Grant probability derived from career allowance rate.

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