DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant's election with traverse of claims 1-11 in the reply filed on 04/24/2026 is acknowledged. The traversal is on the ground(s) that claim 11 is readable in Embodiment 1. Claims 1-11 are examined.
Claim 12 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention (structure of semiconductor unit, fig.9), there being no allowable generic or linking claim. Examiner advise applicants to show claim 12 as “cancelled” (non-elected invention) in response to this office action.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102 a(1) as being anticipated by Matsubara et al. (Pub. No.: US 2019/0296568 A1 and Matsubara hereinafter).
As to claim 1, A motor control device comprising
a plurality of semiconductor units each including a semiconductor device and a battery, the semiconductor device driving a motor, the battery providing DC power to the semiconductor device, wherein
semiconductor devices of the respective semiconductor units are electrically connected in parallel to the motor.
(As to claim 1, Matsubara teaches (figs.1-11) A motor control system (see figs.1-2, para. [0020]-[0021]) comprising
a plurality of semiconductor units [inverter units 12, 14] each including a semiconductor device [IGBT switches] (of inverter units 12, 14, see fig.1, para’s [0037]-[0038]-[0039]) and a battery 18, 22, the semiconductor device [IGBT Switches] (of inverter units 12, 14, fig.1) driving a motor 10, the battery 18, 22 respectively providing DC power to the semiconductor device [IGBT switches] (of respective inverter units 12, 14, see fig.1, para’s [0010], [0038]), wherein semiconductor devices [IGBT switches] of the respective semiconductor units [inverter units 12, 14] are electrically connected in parallel (see fig.1) to the motor 10.
Claim(s) 1 is also rejected under 35 U.S.C. 102(a1) as being anticipated by Mikulec et al. (Pub.No.: US 2016/0001674 A1) and Mikulec hereinafter).
(As to claim 1, teaches (see figs.2-6, para’s [0002], [0038] thru [0045] & par’s [0046] thru [0050])
A motor drive control apparatus 2 (figs.4, 6) comprising
a plurality of semiconductor units [converter sub modules 40] (see figs.4-6, para’s [0041]-[0043]) each including a semiconductor device [inverter 23] (includes Mosfets, see para. [0043]) and a battery 13 (see figs.4-5, para. [0039]), the semiconductor device [inverter 23] driving a motor 30, the battery 13 providing DC power to the semiconductor device [inverter 23], wherein
semiconductor devices [inverters 23] of the respective semiconductor units [converter modules 40] are electrically connected in parallel to the motor 30 (see figs.4, 6)).
Claim(s) 11 is rejected under 35 U.S.C. 102(a1) as being anticipated by KAI et al. (Pub.No.: US 2008/0050645 A1 and KAI hereinafter).
As to claim 11, A semiconductor unit comprising:
a semiconductor device; and
a battery that provides DC power to the semiconductor device, wherein the semiconductor device is mounted on the battery.
(As to claim 11, KAI teaches (figs.1-20) a semiconductor unit 80 (cell controller 80, see figs.10-11, para’s [0072]-[0073], para. [0001], [0060], [0062]) comprising:
a semiconductor device [IC’s 1-12] (have FET switches S1-S4/S5-S8/S45-S48, see fig.11); and
a battery 9 (via cell pack 19 [AB1/AB2/AB12], see figs.2, 8, 11, 17, para’s [0039], [0064], [0163]) that provides DC power to the semiconductor device [IC’s 1-12] (includes FET switches S1-S4/S5-S8/S45-S48, see fig.11), wherein the semiconductor device [IC’s 1-12] (included in semiconductor unit(s) 80) is mounted on the battery 9 (see fig.17, para’s [0062], [0158]).
Claim(s) 11 is also rejected under 35 U.S.C. 102(a1) as being anticipated by Asao et al. (Pub.No.: US 2004/0251858 A1 and Asao hereinafter).
As to claim 11, A semiconductor unit comprising:
a semiconductor device; and
a battery that provides DC power to the semiconductor device, wherein the semiconductor device is mounted on the battery.
(As to claim 11, Asao teaches (figs.1-9, para. [0002], [0025]) A semiconductor unit [inverter unit 400] (figs.1-2) comprising:
a semiconductor device [inverter body 401] (see figs.1-8, para. [0028]); and
a battery 6 that provides DC power (via dc wire lines 81, 82) to the semiconductor device [inverter body 401] (of inverter unit 400, see para. [0025], [0033], [0054]), wherein the semiconductor device [inverter body 401] is mounted on the battery 6 (see fig.1).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Matsubara (Pub. No.: US 2019/0296568 A1) in view of Kawamura (Pub. No.: US 2013/0147407 A1).
As to claim 4, The motor control device according to claim 1, wherein the plurality of semiconductor units each include a control device that controls the semiconductor device, the semiconductor device is an inverter circuit, the semiconductor device includes a voltage sensor that measures an output voltage of the battery, and the control device controls a switching element forming the inverter circuit based on the output voltage of the battery measured by the voltage sensor.
(As to claim 4, Matsubara teaches (figs.1-11) A motor control system (see figs.1-2, para. [0020]-[0021]), wherein the plurality of semiconductor units [inverter units 12, 14] each include a control device [first inverter control unit 46], [second inverter control unit 48)] (see fig.2, of control unit 24, see figs.1-2, para’s [0041],[0048]-[0051]) that controls the semiconductor device [IGBT switches] (of inverter units 12, 14, fig.1), the semiconductor device [IGBT switches] is an inverter circuit 12,16/14, 20 (fig.1, para. [0037]).
Matsubara teaches the control device [control unit 24] (via first inverter control unit 46, second inverter control unit 48)] (see figs.1-2) controls a switching element [IGBT] (fig.1) forming the inverter circuit 12, 16/14, 20 based on the output voltage VB1/VB2 of the battery 18/22 (see fig.2, para. [0045]-[0048]).
Matsubara do not mention the semiconductor device includes a voltage sensor that measures an output voltage of the battery, and the control device controls a switching element forming the inverter circuit based on the output voltage of the battery measured by the voltage sensor.
Kawamura teaches a motor control system (see fig.1), wherein the semiconductor device [semiconductor circuit module 3, 5] (see fig.1, para. [0018]-[0019]) includes a voltage sensor 9 that measures an output voltage of the battery 1 (see fig.1, para. [0025]), and the control device 6 (fig.1) controls a switching element [Q1-Q6] forming the inverter circuit (see fig.1, para. [0018]) based on the output voltage of the battery 1 measured by the voltage sensor 9 (see fig.1, para. [0028]-[0029]).
It would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have the semiconductor device includes a voltage sensor that measures an output voltage of the battery, and the control device controls a switching element forming the inverter circuit based on the output voltage of the battery measured by the voltage sensor of Kawamura in the system of Matsubara because a motor control device reliably protect the semiconductor device from overheating (see Kawamura, Para. [0003]-[0007]).
9. Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara (Pub. No.: US 2019/0296568 A1) in view of Tatematsu et al. (Pub.No.: US 2009/0242286 A1 and Tatematsu hereinafter).
As to claim 8, The motor control device according to claim 1, wherein the motor is a motor that causes a vehicle to travel, and the plurality of semiconductor units are mounted on a chassis of the vehicle.
(As to claim 8, Matsubara teaches (figs.1-11) A motor control system (see figs.1-2, para. [0020]-[0021]) wherein the motor 10 (fig.1) is a motor 10 that causes a vehicle to travel (see para. [0036]).
Matsubara do not mention semiconductor units are mounted on a chassis of the vehicle.
Tatematsu teaches a motor control device 100 (figs.1-5), wherein semiconductor units [inverter units 14, 22] are mounted on a chassis/case [102-104] (figs.2, 5, para. [0003]) of the vehicle 1000.
It would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have semiconductor units are mounted on a chassis of the vehicle of Tatematsu in the system of Matsubara because size reduction of the device can be attained (see Tatematsu, para. [0006]).
As to claim 9, The motor control device according to claim 8, wherein the motor is mounted on an axle of at least one of a front wheel and a rear wheel of the vehicle or in the front wheel and the rear wheel.
(As to claim 9, Matsubara do not mention the motor is mounted on an axle of at least one of a front wheel and a rear wheel of the vehicle.
Tatematsu teaches a motor control device 100 (figs.1-5), wherein the motor [MG1/MG2] is mounted on an axle 20 (figs.1-2, para. [0044], [0085]) of at least on a front wheel WH (fig.1, para. 0032]) of the vehicle 1000.
It would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have the motor is mounted on an axle of at least on a front wheel of the vehicle of Tatematsu in the system of Matsubara because size reduction of the device can be attained (see Tatematsu, para. [0006]) and capable of absorbing vibration of the motor driving system (see Tatematsu, Para. [0011]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Matsubara in view of INADA et al. (Pub.No.: US 2016/0311462 A1 and INADA hereinafter).
As to claim 10, The motor control device according to claim 1, further comprising a switch that individually interrupts electrical connections between semiconductor devices of the respective semiconductor units and the motor.
(As to claim 10, Matsubara do not mention a switch that individually interrupts electrical connections between semiconductor devices of the respective semiconductor units and the motor.
INADA teaches (figs.1-2) a motor control device [motor controller 20] further comprising a current cut off switch 33A/33B (fig.2) that individually cut off electrical connections between semiconductor devices [Q1-Q6] of the respective semiconductor units [first inverter circuit 42A, second inverter circuit 42B] and the motor 12 (due to abnormality, see para’s [0047], [0049], [0050]-[0051], [0053] & [00556]).
It would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have a switch that individually interrupts electrical connections between semiconductor devices of the respective semiconductor units and the motor of INADA in the system of Matsubara because a disconnection of motor is performed based on abnormality detection (open and short circuit failure detection of FETs [Q1-Q6], see para. [0047]).
Allowable Subject-Matter
Claims 2-3, and 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, the prior art of records (closest prior arts, Matsubara, Mikulec, Asao, Kawamura, Tatematsu and INADA et al.) fails to teach the control device estimates a temperature of the battery based on the temperature of the switching element measured by the temperature sensor and controls the switching element based on the temperature of the battery.
As to claim 3, the prior art of records (closest prior arts Matsubara, Mikulec, Asao, Kawamura, Tatematsu and INADA et al.) fails to teach a thermal resistance of the switching element is multiplied by a power loss of the switching element to calculate a change in temperature of the switching element, and the change in temperature is subtracted from the temperature of the switching element to estimate the temperature of the battery.
As to claim 5, the prior art of records (closest prior arts Matsubara, Mikulec, Asao, Kawamura, Tatematsu and INADA et al.) fails to teach the control device compares a reference voltage input from a higher level control device and the output voltage of the battery and controls, when the output voltage of the battery is higher than the reference voltage, the switching element so that the amount of discharge from the battery is increased.
Claims 6-7, depend on allowable claim 5.
Citation of pertinent Prior art
a) Kojima et al. (EP 2706650 A2, prior art of record, figs.1-8, abstract) teaches a power conversion system (fig.1, para. [0015]-[0021], [0043]) including power converters 108, 208 each including a battery 100, 200, dc to AC inverters 102, 202, controller 107, 207, for powering a load 300.
b) Azuma et al., (Pub. No. 2011/0051371) teaches (figs.1-22, abstract, para. [0001]) a power conversion device using the semiconductor device.
c) SUZUKI KENTARO (prior art of record JP 2007104822 A) teaches (figs.1-14, abstract) parallelization system of power converter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONY M PAUL whose telephone number is (571)270-1608. The examiner can normally be reached M-F 8 am to 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Eduardo Colon Santana can be reached at 571-272-2060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTONY M PAUL/
Primary Examiner of Art Unit 2837
Prosecution Insights