CTNF 18/701,618 CTNF 98678 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment The response filed 04/16/2024 is accepted, in which, claims 3, 7, 8, 15, and 18 are amended and claims 19-20 are newly added. Claims 1 and 10 are independent with claims 1-20 awaiting an action on the merits as follows. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 17 is rejected for indefiniteness. Regarding claim 17, the claim recites, "the quantum well." There is insufficient antecedent basis for this element since claim 10 does not include a quantum well. To further prosecution, Examiner will assume the claim should read, "a quantum well." proper correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-6 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Gao (US 20210104585 A1) . Regarding claim 1, Gao teaches a display substrate (Fig 2; display substrate, [Abs.]) , comprising: a driving backplane (BP: layers 60 and below, down to and including substrate 10 including transistors 50) and a light-emitting device layer (LED: layers 31/32/331/20/40) located on (shown on) a side (top) of the driving backplane (BP) , wherein the light-emitting device layer (LED) includes: a plurality of light-emitting units (P) ; a plurality of transparent electrodes (331) located on (shown on) surfaces of the plurality of light-emitting units (P) away (shown away) from the driving backplane (BP) and electrically connected (shown electrically connected) to the plurality of light-emitting units (P) ; and a first bonding pattern (40) located at least between (shown between) the plurality of transparent electrodes (331) ; the first bonding pattern (40) being electrically connected (shown electrically connected) to at least one transparent electrode (331) . Regarding claim 2, Gao teaches the display substrate of claim 1 and goes on to teach wherein the first bonding pattern (40, Fig 2) is further located around (shown around, Fig 3C) the plurality of transparent electrodes (331) . Regarding claim 3, Gao teaches the display substrate of claim 2 and goes on to teach wherein the first bonding pattern (40, Fig 2) has a plurality of openings (43) , an opening (43) is provided with (shown with) at least one transparent electrode (331) therein, and the at least one transparent electrode (331) located in (shown in, Fig 2) the opening (43) is electrically connected (shown electrically connected) to a wall (W: vertical sidewall of opening corresponding to sidewall of layers 32/331) of the opening (43) . Regarding claim 4, Gao teaches the display substrate of claim 1 and goes on to teach wherein the first bonding pattern (40, Fig 2) includes a first pattern layer (P1: 40 is comprised of 2 subparts: P1 is the lower section located horizontally between layers 32/331 with top surface even with the top surface of 331, while P2 is the top portion above P1 that contacts the top surface of 331; please see annotated figure below) and a second pattern layer (P2) that are stacked (shown stacked) , and the second pattern layer (P2) is located on a side (P1top: top surface of P1) of the first pattern layer (P1) away (shown away) from the driving backplane (BP) . PNG media_image1.png 366 694 media_image1.png Greyscale Regarding claim 5, Gao teaches the display substrate of claim 4 and goes on to teach wherein a material of the first pattern layer (P1, Fig 2) includes a first metal material (copper, [0052]) , and a material of the second pattern layer (P2) includes a second metal material (silver, [0052]; there is no specific limitation on the material of the cathode conducting wire 40, [0052]) ; and a melting point (1085 C; well known in the art) of the first metal material (copper) is higher (higher; well known in the art) than a melting point (961.8 C; well known in the art) of the second metal material (silver) . Regarding claim 6, Gao teaches the display substrate of claim 4 and goes on to teach wherein a size (W2: maximum horizontal width of P2, Fig 2) of the second pattern layer (P2) is larger (shown larger) than a size (W1: maximum horizontal width of P1) of the first pattern layer (P1) . 07-15-03-aia AIA Claim s 10-11, and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Uchida (US 20240196714 A1) . Regarding claim 10, Uchida teaches an encapsulation substrate (ESub: layers 17/18/134/19/23, Fig 5) , including: a substrate (Sub: layers 19 and 23) ; an electrode connection layer (134) located on (shown on) a side (B1: bottom of 19) of the substrate (Sub) ; and a second bonding pattern (18) located on (shown on) a side (B2: bottom of 134) of the electrode connection layer (134) away (shown away) from the substrate (Sub) and exposing (shown exposing) at least part of the electrode connection layer (134) . Regarding claim 11, Uchida teaches the encapsulation substrate of claim 10 and goes on to teach wherein the second bonding pattern (18, Fig 5) includes a third pattern layer (P3: second bonding pattern 18 is comprised of two subparts, P3 is the bottom two thirds, while P4 is the top third) and a fourth pattern layer (P4) , and the third pattern layer (P3) is located on (shown on) a side (B3: bottom of P3) of the fourth pattern layer (P4) away (shown away) from the substrate (Sub) . Regarding claim 13, Uchida teaches the encapsulation substrate of claim 11 and goes on to teach wherein a size (H1: height of bottom two thirds of 18) of the third pattern layer (P3) is larger (shown larger) than a size (H2: height of top third of 18) of the fourth pattern layer (P4) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 20210104585 A1) as applied to claims 1-6 above, in view of Lin (US 20090140645 A1), and further in view of Rivera (US 12072543 B1) . Regarding claim 7, Gao teaches the display substrate of claim 1 and goes on to teach a light-emitting unit (P, Fig 2). Gao fails to explicitly teach wherein a light-emitting unit includes: at least two stacked vertical light-emitting diodes; and a connection layer located between two adjacent vertical light-emitting diodes in the at least two stacked vertical light-emitting diodes; wherein the vertical light-emitting diodes each include an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer; and in the two adjacent stacked vertical light-emitting diodes, an N-type semiconductor layer of a vertical light-emitting diode and a P-type semiconductor layer of another vertical light-emitting diode are electrically connected by the connection layer. However, Rivera teaches a quantum well layer (QW: active region may contain quantum wells, [Col 19, Ln 57-60]). Lin teaches a light-emitting unit includes: at least two stacked vertical light-emitting diodes (20; shown as 20.1 and 20.2, Fig 2) ; and a connection layer (30.1) located between (shown between) two adjacent vertical light-emitting diodes (20.1 and 20.2) in the at least two stacked vertical light-emitting diodes (20) ; wherein the vertical light-emitting diodes (20) each include an N-type semiconductor layer (25; N-type, [0023]) , a quantum well layer and a P-type semiconductor layer (21; P-type, [0022]) ; and in the two adjacent stacked vertical light-emitting diodes (20) , an N-type semiconductor layer (25.1) of a vertical light-emitting diode (20.1) and a P-type semiconductor layer (21.2) of another vertical light-emitting diode (20.2) are electrically connected (shown electrically connected) by the connection layer (30.1) . Gao, Lin, and Rivera are considered analogous to the claimed invention because all are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Gao with the features of Lin and Rivera to create a display substrate wherein a light-emitting unit includes: at least two stacked vertical light-emitting diodes; and a connection layer located between two adjacent vertical light-emitting diodes in the at least two stacked vertical light-emitting diodes; wherein the vertical light-emitting diodes each include an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer; and in the two adjacent stacked vertical light-emitting diodes, an N-type semiconductor layer of a vertical light-emitting diode and a P-type semiconductor layer of another vertical light-emitting diode are electrically connected by the connection layer which increases the luminous efficiency under the same current density, and reduces the required operation voltage (Lin, [0007]) and for reducing light reflection at the edges of waveguides by absorbing and converting light incident on edges of the waveguide into electric power, thereby improving the quality of the displayed image and efficiency (Rivera, [Col 1, Ln 47-51]). Regarding claim 8, the combination of Gao, Lin, and Rivera discloses the display substrate of claim 7. Lin teaches the at least two stacked vertical light-emitting diodes (20, Fig 2). Gao goes on to teach a reflective electrode layer (31, Fig 2) located between (shown between) the at least two stacked vertical light-emitting diodes and the driving backplane (BP) . Regarding claim 9, the combination of Gao, Lin, and Rivera discloses the display substrate of claim 7. Gao goes on to teach further comprising: an insulation structure (20, Fig 2) located between (shown between) the plurality of light-emitting units (P) and between (shown between) the first bonding pattern (40) and the driving backplane (BP) . 07-22-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US 20240196714 A1) as applied to claim s 10-11, and 13 above, and further in view of Shi (US 20240038697 A1) . Regarding claim 12, Uchida teaches the encapsulation substrate of claim 11 the fourth pattern layer (P4), and goes on to teach wherein a material of the third pattern layer (P3, Fig 5) includes a third metal material (metal element, [0113]) , and a material of the fourth pattern layer (P4) includes a fourth metal material (metal element, [0113]). Uchida fails to explicitly teach a melting point of the fourth metal material is higher than a melting point of the third metal material. However, Shi teaches a melting point of the fourth metal material is higher (higher; because the melting point of the second metal layer 32 is relatively low, it will melt first in the heating process, and the melted second metal layer 32 will undergo eutectic bonding reaction with the first metal layer. This is analogous to the third pattern layer of encapsulation substrate of Uchida bonding to the second pattern layer of the display substrate of Gao to connect the encapsulation substrate to the display substrate without destroying the first or fourth pattern layers.) than a melting point of the third metal material. Uchida and Shi are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Uchida with the features of Shi to create an encapsulation substrate wherein a melting point of the fourth metal material is higher than a melting point of the third metal material that can realize the firm connection while keeping the small width of the bonding structure (Shi, [0004]) for display characteristics of high brightness, strong environmental adaptability, long service life (Shi, [0002]) . 07-22-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US 20240196714 A1) as applied to claim s 10-11, and 13 above, and further in view of Choi (US 20160043145 A1) . Regarding claim 14, Uchida teaches the encapsulation substrate of claim 10, the substrate (Sub, Fig 5), the electrode connection layer (134) , and the second bonding pattern (134). Uchida fails to explicitly teach a plurality of lenses located between the substrate and the electrode connection layer, wherein the second bonding pattern is at least located between the plurality of lenses. However, Choi teaches a plurality of lenses (500, Fig 1) located between (shown between) the substrate and the electrode connection layer , wherein the second bonding pattern is at least located between (between; when combined, the second blocking pattern of Uchida vertically overlaps the first bonding pattern of Gao, which is between light-emitting regions in a non-emitting region between subpixels. Choi's light block units 430 would overlap the bonding patterns in the non-emitting regions, so when Choi is added to the combination the second bonding pattern of Uchida would be between the lenses of Choi.) the plurality of lenses (500) . Uchida and Choi are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Uchida with the features of Choi to create an encapsulation substrate with a plurality of lenses located between the substrate and the electrode connection layer, wherein the second bonding pattern is at least located between the plurality of lenses so that the efficiency of the organic light emitting devices may be generally improved, and the viewing angles may also be improved (Choi, [0060]) . 07-22-aia AIA Claim s 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US 20240196714 A1) as applied to claim s 10-11, and 13 above, and further in view of Li (US 8947619 B2) . Regarding claim 15, Uchida teaches the encapsulation substrate of claim 10 and goes on to teach wherein the substrate (Sub, Fig 5) includes: a color filter layer (23) …; and the encapsulation layer (19) is disposed closer (shown closer) to the electrode connection layer (134) than the color filter layer (23) . Uchida fails to explicitly teach a base; and a color filter layer located on a side of the base. However, Li teaches a base (122, Fig 1) ; a color filter layer located on a side (B4: bottom of base 122) of the base (122). Uchida goes on to teach an encapsulation layer (19) located on (shown on) a side (B5: bottom of color filter 23) of the color filter layer (23) away (away; when combined, the encapsulation layer of Uchida would be away from the base of Li) from the base . Uchida and Li are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Uchida with the features of Li to create an encapsulation substrate with a base; and a color filter layer located on a side of the base that is low cost, with high energy conversion efficiency, which enables images with a high brightness and a spectacular, vivid range of colors (Li, [Col 4, Ln 17-18 and 20-22]). Regarding claim 16, the combination of Uchida and Li discloses the encapsulation substrate of claim 15. Uchida teaches the second bonding pattern (134) and goes on to teach wherein the color filter layer (23, Fig 5) includes a plurality of color filter portions (23G/B/R). Li goes on to teach a light-shielding pattern (138, Fig 1) located between (shown between) adjacent color filter portions ; and an orthographic projection of the second bonding pattern on the base (122) at least partially overlaps (overlaps; when combined, the light-shielding pattern of Li would overlap the second bonding pattern of Uchida) with an orthographic projection of the light-shielding pattern (138) on the base (122) . 07-21-aia AIA Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US 20240196714 A1), in view of Li (US 8947619 B2), and further in view of Rivera (US 12072543 B1) . Regarding claim 17, the combination of Uchida and Li discloses the encapsulation substrate of claim 16. The combination fails to explicitly teach a quantum well layer. However, Rivera teaches the quantum well layer (quantum well, [Col 19, Ln 57-60]). Li goes on to teach wherein a color filter portion (112) includes a color film layer (136) and a quantum dot layer (128) that are stacked (shown stacked) , wherein the color film layer (136) is disposed closer (closer; when combined the quantum well layer of Rivera would be within the stack of comprising the light-emitting unit of Uchida which would be lower than the color film layer of Li such that the color film layer is closer to the base than the quantum well layer) to the base (122) than the quantum well layer. Uchida, Li, and Rivera are considered analogous to the claimed invention because all are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Uchida and Li with the features of Rivera to create an encapsulation substrate with a quantum well layer that meets the limitations of claim 17 for reducing light reflection at the edges of waveguides by absorbing and converting light incident on edges of the waveguide into electric power, thereby improving the quality of the displayed image and efficiency (Rivera, [Col 1, Ln 47-51]) . 07-22-aia AIA Claim s 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (US 20210104585 A1) , as applied to claim s 1-6 above, and further in view of Uchida (US 20240196714 A1) . Regarding claim 18, Gao teaches the display substrate of claim 1, the first bonding pattern (40), the plurality of transparent electrodes (331), and goes on to teach a display apparatus (D: display apparatus, [0017]) , comprising: the display substrate (Fig 2; display substrate, [Abs.]) according to claim 1; the first bonding pattern (40) in the display substrate (Fig 2) … Gao fails to explicitly teach an encapsulation substrate including: a substrate; an electrode connection layer located on a side of the substrate; and a second bonding pattern located on a side of the electrode connection layer away from the substrate and exposing at least part of the electrode connection layer, wherein the first bonding pattern in the display substrate is bonded to the second bonding pattern in the encapsulation substrate, so that the plurality of transparent electrodes in the display substrate are in contact with the electrode connection layer in the encapsulation substrate. However, Uchida teaches an encapsulation substrate (ESub: layers 17/18/134/19/23, Fig 5) including: a substrate (Sub: layers 19 and 23) ; an electrode connection layer (134) located on (shown on) a side (B1: bottom of 19) of the substrate (Sub) ; and a second bonding pattern (18) located on (shown on) a side (B2: bottom of 134) of the electrode connection layer (134) away (shown away) from the substrate (Sub) and exposing (shown exposing) at least part of the electrode connection layer (134). Gao goes on to teach the first bonding pattern (40) in the display substrate (Fig 2) is bonded (bonded; in combination, the first bonding pattern 40 of Gao would bond to the second bonding pattern 18 of Uchida) to the second bonding pattern in the encapsulation substrate , so that the plurality of transparent electrodes (331) in the display substrate (Fig 2) are in contact (shown in contact) with the electrode connection layer in the encapsulation substrate. Gao and Uchida are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Gao with the features of Uchida to create an encapsulation substrate including: a substrate; an electrode connection layer located on a side of the substrate; and a second bonding pattern located on a side of the electrode connection layer away from the substrate and exposing at least part of the electrode connection layer, wherein the first bonding pattern in the display substrate is bonded to the second bonding pattern in the encapsulation substrate, so that the plurality of transparent electrodes in the display substrate are in contact with the electrode connection layer in the encapsulation substrate for improvement in terms of suppressing damage to an organic light emitting layer due to a gas or the like at the time of processing and improving the reliability of a light emitting state of a pixel (Uchida, [0005]). Regarding claim 19, the combination of Gao and Uchida discloses the display apparatus of claim 18. Uchida goes on to teach wherein the second bonding pattern (18, Fig 5) includes a third pattern layer (P3: second bonding pattern 18 is comprised of two subparts, P3 is the bottom two thirds, while P4 is the top third) and a fourth pattern layer (P4) , and the third pattern layer (P3) is located on (shown on) a side (B3: bottom of P3) of the fourth pattern layer (P4) away (shown away) from the substrate (Sub) . Regarding claim 20, the combination of Gao and Uchida discloses the display apparatus of claim 19. Uchida goes on to teach wherein a material of the third pattern layer (P3, Fig 5) includes a third metal material (metal element, [0113]) , and a material of the fourth pattern layer (P4) includes a fourth metal material (metal element, [0113]) ; and/or a size (H1: height of bottom two thirds of 18) of the third pattern layer (P3) is larger (shown larger) than a size (H2: height of top third of 18) of the fourth pattern layer (P4) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim (US 20230420423 A1) - Different melting point metals to prevent diffusion. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 18/701,618 Page 2 Art Unit: 2897 Application/Control Number: 18/701,618 Page 3 Art Unit: 2897 Application/Control Number: 18/701,618 Page 4 Art Unit: 2897 Application/Control Number: 18/701,618 Page 5 Art Unit: 2897 Application/Control Number: 18/701,618 Page 6 Art Unit: 2897 Application/Control Number: 18/701,618 Page 7 Art Unit: 2897 Application/Control Number: 18/701,618 Page 8 Art Unit: 2897 Application/Control Number: 18/701,618 Page 9 Art Unit: 2897 Application/Control Number: 18/701,618 Page 10 Art Unit: 2897 Application/Control Number: 18/701,618 Page 11 Art Unit: 2897 Application/Control Number: 18/701,618 Page 12 Art Unit: 2897 Application/Control Number: 18/701,618 Page 13 Art Unit: 2897 Application/Control Number: 18/701,618 Page 14 Art Unit: 2897 Application/Control Number: 18/701,618 Page 15 Art Unit: 2897 Application/Control Number: 18/701,618 Page 16 Art Unit: 2897 Application/Control Number: 18/701,618 Page 17 Art Unit: 2897
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