CTNF 18/701,757 CTNF 101887 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Examiner notes the preliminary amendment filed on April 16 th , 2024; therefore, originally filed claims 1-2, 4-5, 7-8, and 12 , and currently amended claims 3, 6, 9-11, 13-19 are subject to examination. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. More specifically, the foreign priority to JP2021-183513 with a priority date of November 10 th , 2021, is acknowledged. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application. Information Disclosure Statement The information disclosure statement (IDS) filed on April 16 th , 2024, is being considered by the Examiner. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature as described in Claims 13 and 16 (i.e., a plurality of insulating substrates being covered by a single conductor pattern) must be shown or the feature(s) canceled from the claim(s). Presently, the Figures only disclose a plurality of insulating substrates accompanied by a plurality of conductor patterns. No new matter should be entered. Additionally, the feature as described in Claim 6 (i.e., a sixth semiconductor element having more adjacent semiconductor elements than the fifth semiconductor element while having less adjacent semiconductor elements than the fourth semiconductor element) must be shown or the feature(s) be canceled from the claim(s). Presently, the Figures only disclose a sixth semiconductor element having the same number of adjacent semiconductor elements as the fourth semiconductor element. No new matter should be entered. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-16 AIA Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided. Claim Objections Claims 4-6 are objected for the following reasons. Regarding said claims, they are independent from Claim 1, and introduce a plurality of semiconductor elements. However, upon naming individual semiconductor elements, they begin with “ fourth semiconductor element ” into “ fifth semiconductor element ” and end with “ sixth semiconductor element ” without introducing a first, second, or third semiconductor element. This can lead to confusion, as Examiner is unsure whether applicant is intending for there to be a first, second, and third identified semiconductor element, or if applicant was attempting to avoid confusion with the first independent claim grouping. For the purposes of compact prosecution, the Examiner is interpreting the fourth, fifth, and sixth semiconductor elements as the first, second, and third semiconductor elements of the device for independent claim group two (i.e., Claims 4-6 ). Appropriate correction is required. Claims 7-10 are objected for the following reasons. Regarding said claims, they are independent from Claims 1 and 4, and introduce a plurality of semiconductor elements. However, upon naming individual semiconductor elements, they begin with “ seventh semiconductor element ” into “ eighth semiconductor element ” and end with “ ninth semiconductor element ” without introducing a first, second, third, fourth, fifth, or sixth semiconductor element. This can lead to confusion, as Examiner is unsure whether applicant is intending for there to be a first, second, third, fourth, fifth, and sixth identified semiconductor element, or if applicant was attempting to avoid confusion with the first and second independent claim grouping. For the purposes of compact prosecution, the Examiner is interpreting the seventh, eighth, and ninth semiconductor elements as the first, second, and third semiconductor elements of the device for independent claim group three (i.e., Claims 7-10 ). Appropriate correction is required. Applicant is advised that should Claim 13 be found allowable, Claim 16 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m) . More specifically, Claim 16 recites the word-for-word limitations of Claim 13 , and both claims are dependent upon Claim 1 and is deemed to be a duplicate thereof. Claim Rejections - 35 USC § 112 07-31-01 Claim 6 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. More specifically, regarding Claim 6 , it states, “ the plurality of semiconductor elements include a sixth semiconductor element having a number of adjacent semiconductor elements smaller than that of the fourth semiconductor element and larger than that of the fifth semiconductor element, … ”. However, the Specification is silent as to how a grouping of semiconductor elements, arranged as described within the same and in Figs. 1, 2, and 8-11, can have a sixth (or third using the interpretation as stated in the above Claim Objections section) semiconductor element that has less adjacent semiconductor elements than the fourth (or first using the interpretation as stated in the above Claim Objections section) semiconductor element. It is not described in the specification, nor is it shown in any Figure provided that a sixth semiconductor element as described can have adjacencies less than the number of adjacencies for the center semiconductor element while having more adjacencies than the end semiconductor element. Appropriate clarification is deemed to be required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: a) Determining the scope and contents of the prior art. b) Ascertaining the differences between the prior art and the claims at issue. c) Resolving the level of ordinary skill in the pertinent art. d) Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akagawa, et al. (JP 2005136229 A; hereinafter referred to as Akagawa), and further in view of Saggio, et al. (US 20210399089 A1; hereinafter referred to as Saggio) . PNG media_image1.png 567 751 media_image1.png Greyscale Regarding Claim 1 , Akagawa discloses a semiconductor device (semiconductor device 10 or semiconductor device 30) comprising: an insulating substrate (substrate 11 or 31, [0023], Figs. 1 and 3; “the plurality of semiconductor elements 14 or 22 are arranged on the ceramic insulating substrate”) ; a conductor pattern formed on the insulating substrate (heat spreader 12 or 32, [0002, 0013], Figs. 1 and 3) ; and a plurality of semiconductor elements provided on the conductor pattern and electrically connected in parallel (semiconductor elements 14 or 34, [0002, 0013], Figs. 1 and 3; “each semiconductor element 34 is wire-bonded to the electrode 33 by a wire 35 and connected in parallel to the electrode 33”) , wherein the conductor pattern has a minimum rectangular region surrounding the plurality of semiconductor elements in plan view (see Annotated Akagawa Fig. 3 above) , the plurality of semiconductor elements include: a first semiconductor element located nearest to a center of gravity of the rectangular region (first semiconductor element, see Annotated Akagawa Fig. 3 above) ; and a second semiconductor element located farther from the center of gravity of the rectangular region (second semiconductor element, see Annotated Akagawa Fig. 3 above) . Akagawa fails to disclose that each semiconductor element of the plurality of semiconductor elements has an epitaxial layer of a first conductivity type. However, in analogous art, Saggio discloses that each semiconductor element of the plurality of semiconductor elements has an epitaxial layer of a first conductivity type (Saggio: [0027, 0028]; “a semiconductor body 102, of semiconductor material (which includes, for example, a substrate and, optionally, one or more epitaxial layers)”). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the semiconductor elements by introducing an epitaxial layer of a first conductivity type between the semiconductor elements and the conductor pattern as taught by Saggio. One would be motivated to do so as introducing said epitaxial layer provides a layer to apply a doping concentration to in order to modulate the conduction threshold voltage and saturation currents of the associated semiconductor elements to the users desired range (Saggio: [Abstract, 0045-0046]). Additionally, Akagawa fails to disclose a first impurity concentration in the epitaxial layer of the first semiconductor element is higher than a second impurity concentration in the epitaxial layer of the second element. However, Saggio discloses a first impurity concentration in the epitaxial layer of the first semiconductor element is higher than a second impurity concentration in the epitaxial layer of the second element (Saggio: [0045]; sub-region 121 is analogous to the epitaxial layer of the first semiconductor element and sub-region 123 is analogous to the epitaxial layer of the second semiconductor element). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, having the teachings of Akagawa and Saggio before them, to modify the teachings of a semiconductor device as taught by Akagawa and to include the teachings of a semiconductor device having different conduction threshold voltages and different saturation currents as taught by Saggio since this provides for reduced heating through the device by limiting the high breakdown current and voltage damage (Saggio: [0007]). Regarding Claim 2 , Akagawa/Saggio discloses the semiconductor device as claimed in claim 1, wherein the first impurity concentration is highest among the plurality of semiconductor elements (Saggio: [0045]) , and the second impurity concentration is lowest among the plurality of semiconductor elements (Saggio: [0045]) . Regarding Claim 3 , Akagawa/Saggio discloses the semiconductor device of claim 1, wherein the plurality of semiconductor elements include a third semiconductor element that is farther from the center of gravity of the rectangular region than the first semiconductor element is from the center of gravity of the rectangular region and nearer to the center of gravity of the rectangular region than the second semiconductor element is to the center of gravity of the rectangular region (third semiconductor element, see Annotated Akagawa Fig. 3 above) , and a third impurity concentration in the epitaxial layer of the third semiconductor element is higher than the second impurity concentration and lower than the first impurity concentration (Saggio: [0045]; the third semiconductor element is located between the first and second semiconductor element and, therefore, would be analogous to sub-region 123 when comparing the impurity concentrations of the epitaxial layers of the first and third semiconductor elements and would be analogous to sub-region 121 when comparing the impurity concentrations of the epitaxial layers of the second and third semiconductor elements) . Regarding Claim 4 , Akagawa/Saggio discloses a semiconductor device comprising: an insulating substrate (Akagawa: substrate 11 or 31, [0023], Figs. 1 and 3) ; a conductor pattern formed on the insulating substrate (Akagawa: heat spreader 12 or 32, [0002, 0013], Figs. 1 and 3) ; and a plurality of semiconductor elements provided on the conductor pattern and electrically connected in parallel (Akagawa: semiconductor elements 14 or 34, [0002, 0013], Figs. 1 and 3; “each semiconductor element 34 is wire-bonded to the electrode 33 by a wire 35 and connected in parallel to the electrode 33”) , wherein each semiconductor element of the plurality of semiconductor elements has an epitaxial layer of a first conductivity type (Saggio: [0027, 0028]; “a semiconductor body 102, of semiconductor material (which includes, for example, a substrate and, optionally, one or more epitaxial layers)”) , the plurality of semiconductor elements include: a fourth semiconductor element having a largest number of semiconductor elements adjacent to each other (first semiconductor element, see Annotated Akagawa Fig. 3; has two adjacent semiconductor elements in the horizontal direction which is the largest number in the set) ; and a fifth semiconductor element having a smallest number of semiconductor elements adjacent to each other (second semiconductor element, see Annotated Akagawa Fig. 3; only has one adjacent semiconductor element while all others have two) , and a fourth impurity concentration in the epitaxial layer of the fourth semiconductor element is higher than a fifth impurity concentration in the epitaxial layer of the first semiconductor element ([0045]; sub-region 121 is analogous to the epitaxial layer of the first semiconductor element and sub-region 123 is analogous to the epitaxial layer of the second semiconductor element) . Regarding Claim 5 , Akagawa discloses the semiconductor device as claimed in claim 4, wherein the fourth impurity concentration is highest among the plurality of semiconductor elements (Saggio: [0045]) , and the fifth impurity concentration is lowest among the plurality of semiconductor elements (Saggio: [0045]) . Regarding Claim 6 , Akagawa/Saggio discloses the semiconductor device as claimed in claim 4, wherein the plurality of semiconductor elements include a sixth semiconductor element having a number of adjacent semiconductor elements smaller than that of the fourth semiconductor element and larger than that of the first semiconductor element (third semiconductor element, see Annotated Akagawa Fig. 3 above; see 112(a) Rejection above) , and a sixth impurity concentration in the epitaxial layer of the sixth semiconductor element is higher than the fifth impurity concentration and lower than the fourth impurity concentration (Saggio: [0045]; the third semiconductor element is located between the first and second semiconductor element and, therefore, would be analogous to sub-region 123 when comparing the impurity concentrations of the epitaxial layers of the first and third semiconductor elements and would be analogous to sub-region 121 when comparing the impurity concentrations of the epitaxial layers of the second and third semiconductor elements) . Regarding Claim 7 , Akagawa/Saggio discloses a semiconductor device comprising: an insulating substrate (Akagawa: substrate 11 or 31, [0023], Figs. 1 and 3) ; a conductor pattern formed on the insulating substrate (Akagawa: heat spreader 12 or 32, [0002, 0013], Figs. 1 and 3) ; and a plurality of semiconductor elements provided on the conductor pattern and electrically connected in parallel (Akagawa: semiconductor elements 14 or 34, [0002, 0013], Figs. 1 and 3; “each semiconductor element 34 is wire-bonded to the electrode 33 by a wire 35 and connected in parallel to the electrode 33”) , wherein each semiconductor element of the plurality of semiconductor elements has an epitaxial layer of a first conductivity type (Saggio: [0027, 0028]; “a semiconductor body 102, of semiconductor material (which includes, for example, a substrate and, optionally, one or more epitaxial layers)”) , the plurality of semiconductor elements include: a seventh semiconductor element having a highest temperature during operation (Akagawa: [0015]) ; and an eighth semiconductor element having a lowest temperature during operation (Akagawa: [0015]) , and a seventh impurity concentration in the epitaxial layer of the seventh semiconductor element is higher than that of an eighth impurity concentration in the epitaxial layer of the eighth semiconductor element ([0045]; sub-region 121 is analogous to the epitaxial layer of the first semiconductor element and sub-region 123 is analogous to the epitaxial layer of the second semiconductor element) . Regarding Claim 8 , Akagawa/Saggio discloses the semiconductor device of claim 7, wherein the seventh impurity concentration is highest among the plurality of semiconductor elements (Saggio: [0045]) , and the eighth impurity concentration is lowest among the plurality of semiconductor elements (Saggio: [0045]) . Regarding Claim 9 , Akagawa/Saggio discloses the semiconductor device of claim 7, wherein the plurality of semiconductor elements include a ninth semiconductor element having a temperature during operation lower than that of the seventh semiconductor element and higher than that of the eighth semiconductor element (third semiconductor element, see Annotated Akagawa Fig. 3 above, [0015]) , and a ninth impurity concentration in the epitaxial layer of the ninth semiconductor element is higher than the eighth impurity concentration and lower than the seventh impurity concentration (Saggio: [0045]; the third semiconductor element is located between the first and second semiconductor element and, therefore, would be analogous to sub-region 123 when comparing the impurity concentrations of the epitaxial layers of the first and third semiconductor elements and would be analogous to sub-region 121 when comparing the impurity concentrations of the epitaxial layers of the second and third semiconductor elements) . Regarding Claim 10 , Akagawa/Saggio discloses the semiconductor device of claim 7, wherein the plurality of semiconductor elements are arranged in a line (Akagawa: Figs. 1-3) , the seventh semiconductor element (first semiconductor element, Annotated Akagawa Fig. 3) is a semiconductor element disposed at a center (see Annotated Akagawa Fig. 3 above) , and the eighth semiconductor element (second semiconductor element, Annotated Akagawa Fig. 3) is a semiconductor element disposed at an end portion (see Annotated Akagawa Fig. 3 above) . Regarding Claim 11 , Akagawa/Saggio discloses the semiconductor device of claim 1, wherein the epitaxial layer is formed of a wide bandgap semiconductor material (Saggio: [0028]; “the semiconductor body 102 is made of silicon carbide (SiC)” wherein the semiconductor body includes the epitaxial layer and it is known in the art that silicon carbide is a wide bandgap semiconductor material) . Regarding Claim 12 , Akagawa/Saggio discloses the semiconductor device of claim 1, wherein the wide bandgap semiconductor material is silicon carbide, or gallium nitride, or gallium oxide (Saggio: [0028]; “the semiconductor body 102 is made of silicon carbide (SiC)” wherein the semiconductor body includes the epitaxial layer) . Regarding Claim 13 , Akagawa/Saggio discloses the semiconductor device of claim 1. The combination of Akagawa/Saggio fails to explicitly disclose a plurality of the insulating substrates, wherein the conductor pattern is formed on each insulating substrate of the plurality of insulating substrates, and the plurality of semiconductor elements are provided on the conductor pattern. However, this limitation is considered obvious under MPEP 2144.04(VI)(B) , Duplication of Parts. The introduction of a plurality of insulating substrates to the semiconductor device for which the conductor patterns are formed upon does not create a new or unexpected result for the semiconductor device. Furthermore, the applicant has not presented persuasive evidence in the instant Specification, paragraphs [0070-0077], that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Regarding Claim 14 , Akagawa/Saggio discloses the semiconductor device as claimed in claim 1. The combination of Akagawa/Saggio fails to explicitly disclose a plurality of the conductor patterns, wherein the plurality of semiconductor elements are provided on the plurality of conductor patterns, respectively. However, this limitation is considered obvious under MPEP 2144.04(VI)(B) , Duplication of Parts. The introduction of a plurality of conductor patterns to the semiconductor device for which the semiconductor elements are formed upon does not create a new or unexpected result for the semiconductor device. Furthermore, the applicant has not presented persuasive evidence in the instant Specification, paragraphs [0078-0079], that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Regarding Claim 15 , Akagawa/Saggio discloses the semiconductor device as claimed in claim 1. The combination of Akagawa/Saggio fails to explicitly disclose a plurality of the insulating substrates, wherein a plurality of the conductor patterns are formed on each insulating substrate of the plurality of insulating substrates, and the plurality of semiconductor elements are provided on the plurality of conductor patterns, respectively. However, this limitation is considered obvious under MPEP 2144.04(VI)(B) , Duplication of Parts. The introduction of a plurality of insulating substrates and a plurality of conductor patterns to the semiconductor device for which the plurality of semiconductor elements are formed upon does not create a new or unexpected result for the semiconductor device. Furthermore, the applicant has not presented persuasive evidence in the instant Specification, paragraphs [0080-0098], that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Regarding Claim 16 , --- Akagawa/Saggio discloses the semiconductor device as claimed in claim 1. The combination of Akagawa/Saggio fails to explicitly disclose a plurality of the insulating substrates, wherein the conductor pattern is formed on each insulating substrate of the plurality of insulating substrates, and the plurality of semiconductor elements are provided on the conductor pattern. However, this limitation is considered obvious under MPEP 2144.04(VI)(B) , Duplication of Parts. The introduction of a plurality of insulating substrates to the semiconductor device for which the conductor patterns are formed upon does not create a new or unexpected result for the semiconductor device. Furthermore, the applicant has not presented persuasive evidence in the instant Specification, paragraphs [0070-0077], that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Regarding Claim 17 , Akagawa/Saggio discloses the semiconductor device as claimed in claim 1, wherein the plurality of semiconductor elements include a field effect transistor (Akagawa: [0013]; Examiner notes that a “field effect transistor” is analogous to “MOS-FET” and would be covered under Akagawa) . Regarding Claim 18 , Akagawa/Saggio discloses the semiconductor device as claimed in claim 1, wherein the plurality of semiconductor elements include an insulated gate bipolar transistor (Akagawa: [0013]). Regarding Claim 19 , Akagawa/Saggio discloses the semiconductor device as claimed in claim 1, wherein the plurality of semiconductor elements include a Schottky barrier diode (Saggio: [0010]) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (a) Echigoya, et al. (US 20160093691 A1); discloses semiconductor elements arranged in a line separated apart for better thermal protection while introducing a doped epitaxial wide bandgap layer between the insulating substrate and the semiconductor elements. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge , can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000. /Noah C. Robertson/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/701,757 Page 2 Art Unit: 2812 Application/Control Number: 18/701,757 Page 3 Art Unit: 2812 Application/Control Number: 18/701,757 Page 4 Art Unit: 2812 Application/Control Number: 18/701,757 Page 5 Art Unit: 2812 Application/Control Number: 18/701,757 Page 6 Art Unit: 2812 Application/Control Number: 18/701,757 Page 7 Art Unit: 2812 Application/Control Number: 18/701,757 Page 8 Art Unit: 2812 Application/Control Number: 18/701,757 Page 9 Art Unit: 2812 Application/Control Number: 18/701,757 Page 10 Art Unit: 2812 Application/Control Number: 18/701,757 Page 11 Art Unit: 2812 Application/Control Number: 18/701,757 Page 12 Art Unit: 2812 Application/Control Number: 18/701,757 Page 13 Art Unit: 2812 Application/Control Number: 18/701,757 Page 14 Art Unit: 2812
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