DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, and 5-7 are pending in this application.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 11/25/2025 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Response to Amendment
Claims 1, 2, 5, and 6 are amended. Claims 3, 4, and 8 are canceled.
Response to Arguments
Applicant's arguments filed 04/06/2026 have been fully considered but they are not persuasive. Applicant argues that Kaeriyama et al. U.S. Patent Application 2019/0204889 (hereinafter “Kaeriyama”) does not teach “(i) a configuration in which a measured voltage is directly used to determine a short circuit condition and to initiate an immediate protection operation, (ii) a filter unit specifically configured to balance rapid response and switching noise immunity, and (iii) a comparison unit that directly controls the switch based on the determination result.” However, Kaeriyama does teach a configuration in which a measured voltage is used to initiate an immediate protection operation. In figure 2 of Kaeriyama, the voltage VDsen goes through filter SAC, amplifier AMP 1, and comparator CMP1, this output of CMP1 is then OR’ed with the output of CMP2 and AND’ed with the gate signal to create the signal Fdet. This signal is then output to the MCU which then turns off the driving transistor (refer to [0051]) thereby effecting immediate protection. Kaeriyama does not teach the measured voltage directly used to determine a short circuit condition; however, the claim does not require the measured voltage directly used to determine short circuit condition. The claim includes the limitation “device for detecting a short circuit of a switch”. The device is equated to the circuit shown in figure 2 of Kaeriyama in the Non-Final Rejection mailed 01/06/2026. The circuit of figure 2 does detect a short circuit condition (refer to CMP2 and [0048]). There is no limitation in the claim that requires the voltage measurement unit to detect the short circuit. Therefore, this is not persuasive. Kaeriyama does not teach “a filter unit specifically configured to balance rapid response and switching noise immunity; however this is also not claimed in the claim. Therefore, this is not persuasive. Kaeriyama does not teach “a comparison unit that directly controls the switch based on the determination result”; however, this is not claimed in the claim. The claim language requires a control unit to control the gate driving unit to turn on or turn off the switch “according to an output of the comparison unit” as stated above, the MCU turns off the driving transistor through signal PWMi which is output to the gate driver DRV when the signal FO is received. The signal FO is based on the output of CMP1 and, therefore, is output “according to the output of the comparison unit. Thus the gate driving unit is controlled to turn on or turn off the switch according to the output of the comparison unit. Therefore, this is not persuasive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaeriyama et al. U.S. Patent Application 2019/0204889 (hereinafter “Kaeriyama”), and further in view of Liu et al. Chinese Patent Document CN 211930607 U (hereinafter “Liu”).
Regarding claim 1, Kaeriyama teaches a device (refer to fig.2) for detecting a short circuit (refer to [0048]) of a switch (i.e. driving transitor4 TRd)(fig.2) and protecting the switch (refer to [0048] and [0051]), the device comprising: a voltage measurement unit (refer to clamping transistor TRclp and VDsen)(fig.2)(refer also to voltage limiter LMT)(fig.1) configured to measure an output voltage of the switch and output the output voltage as a measured voltage (refer to VDsen)(fig.2); a filter unit (i.e. surge absorption circuit SAC)(fig.2)(refer also to SACa)(fig.5)(refer also to [0065]) configured to filter the measured voltage to a bandwidth (refer to [0065]) and output the filtered voltage as a first voltage (implicit); an amplifying unit (i.e. amplifier circuit AMP1)(fig.2) configured to amplify the first voltage with a gain (implicit) and output the amplified first voltage as a second voltage (implicit) in order to adjust a margin between the first voltage and a reference voltage (implicit); a comparison unit (i.e. comparator CMP1)(fig.2) configured to compare the second voltage with the reference voltage (refer to [0045] and [0046]); a gate driving unit (i.e. driver DRV)(fig.2) configured to supply driving power to a gate of the switch (refer to [0035]); and a control unit (i.e. control device MCU)(fig. 2) configured to control the gate driving unit to turn on or turn off the switch according to an output of the comparison unit (refer to [0051]); however, Kaeriyama does not teach wherein the voltage measurement unit comprises: a diode in which a cathode is connected to an output terminal of the switch; a first resistor in which one end is connected to an anode of the diode; and a second resistor connecting the other end of the first resistor to a power supply, and wherein the voltage measurement unit is configured to output a voltage at the other end of the first resistor as the measured voltage. However, Liu teaches wherein the voltage measurement unit comprises: a diode (i.e. diode D1)(fig.2) in which a cathode is connected to an output terminal of the switch (implicit)(refer to IGBT Q1)(fig.2); a first resistor (i.e. resistor R4)(fig.2) in which one end is connected to an anode of the diode (implicit); and a second resistor (i.e. resistor R3)(fig.2) connecting the other end of the first resistor to a power supply (implicit)(refer to VDD)(fig.2), and wherein the voltage measurement unit is configured to output a voltage at the other end of the first resistor as the measured voltage (implicit)(refer to Desat)(fig.2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kaeriyama to include the voltage measurement circuit of Liu to provide the advantage of using a simple well-known circuit for sensing voltage having a low stray capacitance so that noise coupling and switching delays are reduced.
Regarding claim 2, Kaeriyama and Liu teach the device of claim 1, wherein the filter unit comprises: one or more of a band-pass filter configured to pass only a pre-determined frequency range and a low-pass filter configured to filter components at or above a pre-determined frequency (refer to Kaeriyama [0065]).
Regarding claim 5, Kaeriyama and Liu teach the device of claim 1, wherein the filter unit comprises: a third resistor (i.e. Kaeriyama resistor R)(fig.5)(i.e. Liu resistor R2)(fig.2) in which one end is connected to the other end of the first resistor (implicit)(refer to Liu resistors R2 and R4)(fig.2); and a capacitor (i.e. Kaeriyama capacitor C)(fig.5)(i.e. Liu capacitor C1)(fig.2) connecting the other end of the third resistor to a ground (refer to Kaeriyama capacitor C and GND)(fig.5)(refer to Liu GND)(fig.2), and wherein the filter unit is configured to output a voltage applied to the capacitor as the first voltage (refer to Kaeriyama terminal opposite VDsen)(fig.5)(refer to Liu Desat)(fig.2).
Regarding claim 7, Kaeriyama and Liu teach the device of claim 1, wherein the switch is a power switch (implicit)(refer to Kaeriyama driving transistor TRd)(fig.1)(refer also to Kaeriyama power transistor PTR)(fig.2), and the output voltage is a drain voltage of the power switch (implicit)(refer to Kaeriyama drain voltage VD)(fig.2).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaeriyama and Liu as applied to claim 5 above, and further in view of Norling et al. U.S. Patent Application 2019/0074827 (hereinafter “Norling”).
Regarding claim 6, Kaeriyama and Liu teach the device of claim 5, wherein the amplifying unit comprises: an amplifier (i.e. Kaeriyama amplifier circuit AMP1)(fig.2) in which the other end of the third resistor is a first input terminal (+) of the amplifier (implicit)(refer to Kaeriyama SAC and AMP1+)(fig.2), wherein the amplifying unit is configured to output an voltage at an output terminal of the amplifier as the second voltage (implicit)(refer to Kaeriyama AMP1)(fig.2); however, Kaeriyama and Liu do not teach a fourth resistor connecting an output terminal of the amplifier to a second input terminal (-) of the amplifier; and a fifth resistor connecting the second input terminal (-) of the amplifier to the ground. However, Norling teaches a fourth resistor (i.e. resistor Rg2)(fig.15) connecting an output terminal of the amplifier to a second input terminal (-) of the amplifier (implicit)(refer to operational amplifier 1502)(fig.15); and a fifth resistor (i.e. resistor Rg1)(fig.15) connecting the second input terminal (-) of the amplifier to the ground (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kaeriyama and Liu to include the amplifier circuit of Norling to provide the advantage of allowing for more precise control of the gain of the amplifier circuit.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST.
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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