DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-8 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 04/17/2024 and 11/03/2025 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 5 is objected to because of the following informalities: Claim 5 recites the limitation “unitoutputs” in line 6 of the claim. This appears to mean “unit outputs”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaeriyama et al. U.S. Patent Application 2019/0204889 (hereinafter “Kaeriyama”).
Regarding claim 1, Kaeriyama teaches a device (refer to fig.2) for detecting and protecting a short circuit (refer to [0048]) of a switch (i.e. driving transitor4 TRd)(fig.2) the device comprising: a voltage measurement unit (refer to clamping transistor TRclp and VDsen)(fig.2)(refer also to voltage limiter LMT)(fig.1) configured to measure an output voltage of the switch and output the output voltage as a measured voltage (refer to VDsen)(fig.2); a filter unit (i.e. surge absorption circuit SAC)(fig.2)(refer also to SACa)(fig.5)(refer also to [0065]) configured to filter the measured voltage to a specified bandwidth (refer to [0065]) and output the filtered voltage as a first voltage (implicit); and a comparison unit (i.e. comparator CMP1)(fig.2) configured to compare the first voltage with a specified reference voltage (refer to [0046]).
Regarding claim 2, Kaeriyama teaches the device of claim 1, wherein the filter unit comprises: one or more of a band-pass filter capable of passing only a specified frequency range and a low-pass filter capable of filtering components equal to or greater than a specified bandwidth (refer to [0065]).
Regarding claim 3, Kaeriyama teaches the device of claim 1, further comprising: an amplifying unit (i.e. amplifier circuit AMP1)(fig.2) configured to amplify the first voltage with a pre-specified gain (implicit) and output the amplified voltage as a second voltage (implicit) in order to adjust a margin between the first voltage and the reference voltage (implicit), wherein the comparison unit compares the second voltage with the reference voltage (refer to [0045] and [0046]).
Regarding claim 7, Kaeriyama teaches the device of claim 1, wherein the switch is a power switch (implicit)(refer to driving transistor TRd)(fig.1)(refer also to power transistor PTR)(fig.2), and the output voltage is a drain voltage of the power switch (implicit)(refer to drain voltage VD)(fig.2).
Regarding claim 8, Kaeriyama teaches the device of claim 7, further comprising: a gate driving unit (i.e. driver DRV)(fig.2) configured to supply driving power to a gate of the power switch (refer to [0035]); and a control unit (i.e. control device MCU)(fig. 2) configured to control the gate driving unit to turn on or turn off the power switch according to an output of the comparison unit (refer to [0051]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaeriyama as applied to claim 3 above, and further in view of Liu et al. Chinese Patent Document CN 211930607 U (hereinafter “Liu”).
Regarding claim 4, Kaeriyama teaches the device of claim 3; however, Kaeriyama does not teach wherein the voltage measurement unit comprises: a diode in which a cathode is connected to an output terminal of the switch; a first resistor in which one end is connected to an anode of the diode; and a second resistor connecting the other end of the first resistor to a pre-determined power supply, Vg, and wherein the voltage measurement unit outputs a voltage at the other end of the first resistor as the measured voltage. However, Liu teaches wherein the voltage measurement unit comprises: a diode (i.e. diode D1)(fig.2) in which a cathode is connected to an output terminal of the switch (implicit)(refer to IGBT Q1)(fig.2); a first resistor (i.e. resistor R4)(fig.2) in which one end is connected to an anode of the diode (implicit); and a second resistor (i.e. resistor R3)(fig.2) connecting the other end of the first resistor to a pre-determined power supply, Vg (implicit)(refer to VDD)(fig.2), and wherein the voltage measurement unit outputs a voltage at the other end of the first resistor as the measured voltage (implicit)(refer to Desat)(fig.2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kaeriyama to include the voltage measurement circuit of Liu to provide the advantage of using a simple well-known circuit for sensing voltage having a low stray capacitance so that noise coupling and switching delays are reduced.
Regarding claim 5, Kaeriyama and Liu teach the device of claim 4, wherein the filter unit comprises: a third resistor (i.e. Kaeriyama resistor R)(fig.5)(i.e. Liu resistor R2)(fig.2) in which one end is connected to the other end of the first resistor (implicit)(refer to Liu resistors R2 and R4)(fig.2); and a capacitor (i.e. Kaeriyama capacitor C)(fig.5)(i.e. Liu capacitor C1)(fig.2) connecting the other end of the third resistor to a pre-determined ground (refer to Kaeriyama capacitor C and GND)(fig.5)(refer to Liu GND)(fig.2), and wherein the filter unit outputs a voltage applied to the capacitor as the first voltage (refer to Kaeriyama terminal opposite VDsen)(fig.5)(refer to Liu Desat)(fig.2).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaeriyama and Liu as applied to claim 5 above, and further in view of Norling et al. U.S. Patent Application 2019/0074827 (hereinafter “Norling”).
Regarding claim 6, Kaeriyama and Liu teach the device of claim 5, wherein the amplifying unit comprises: an amplifier (i.e. Kaeriyama amplifier circuit AMP1)(fig.2) that the other end of the third resistor is a first input terminal (+) of the amplifier (implicit)(refer to Kaeriyama SAC and AMP1+)(fig.2), wherein the amplifying unit outputs an voltage at an output terminal of the amplifier as the second voltage (implicit)(refer to Kaeriyama AMP1)(fig.2); however, Kaeriyama and Liu do not teach a fourth resistor connecting an output terminal of the amplifier to a second input terminal (-) of the amplifier; and a fifth resistor connecting the second input terminal (-) of the amplifier to a pre- determined ground. However, Norling teaches a fourth resistor (i.e. resistor Rg2)(fig.15) connecting an output terminal of the amplifier to a second input terminal (-) of the amplifier (implicit)(refer to operational amplifier 1502)(fig.15); and a fifth resistor (i.e. resistor Rg1)(fig.15) connecting the second input terminal (-) of the amplifier to a pre- determined ground (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kaeriyama and Liu to include the amplifier circuit of Norling to provide the advantage of allowing for more precise control of the gain of the amplifier circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST.
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838