DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 7, the recitation of “wherein capacitance of the balance capacitors of the MOSFET cells N=1 to N=(n-1) are identical” is inconsistent with the limitation of claim 6 which it depends on, thus, the metes and bound of the claim cannot be determined renders the claim indefinite.
Claim 9 is indefinite because of the technical deficiencies of claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ren Yu et al. “A Single Gate Driver Based Solid State Circuit Breaker Using Series Connected SiC MOSFETs”, Applicant’s cited prior art.
Regarding claim 11, Ren Yu et al.’s figure 1 shows a switching circuit comprising a gate terminal (A), a source terminal (source terminal of M1), a drain terminal (drain terminal of M1) and a cascading terminal (terminal between C1 and Rg2);; a MOSFET (MN) having a gate node (Gate electrode), source node (source terminal) and drain node (drain terminal) connected to the gate, source and drain terminals respectively; a gate resistor (Rg1/Rg2) between the gate node and a gate terminal; a balance capacitor (C2) between the source node and the cascading terminal; a balance resistor (Var1/Var2) in parallel with the balance capacitor; and a gate driver (generates A and B) connected to drive the gate node (G1) of the first MOSFET cell; wherein the switching circuit cell is configured to be connected with a gate driver and at least one like cell in series to provide a high voltage switching circuit as called for in claim 11.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 7, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ren Yu et al. “A Single Gate Driver Based Solid State Circuit Breaker Using Series Connected SiC MOSFETs”, Applicant’s cited prior art.
Regarding claim 1, Ren Yu et al.’s figure 1 shows A switching circuit comprising: a plurality of n MOSFET cells (n = 2, n=2 in this configuration), each MOSFET cell comprising: a gate terminal (A), a source terminal (source terminal of M1), a drain terminal (drain terminal of M1) and a cascading terminal (terminal between C1 and Rg2); a MOSFET (M1, M2) having a gate node, source node and drain node connected to the gate, source and drain terminals (A, source terminal of M1 and drain terminal of M1) respectively; a gate resistor (Rg1) between the gate node and a gate terminal (A); a balance capacitor (C1; C2) between the source node and the cascading terminal; a balance resistor (Var1, Var2, which is a form of resistor) in parallel with the balance capacitor; a gate driver (generating the signal between terminals A and B) connected to drive the gate node of the first MOSFET cell; wherein: the drain terminal of each of the MOSFET cells is connected to the source terminal of an adjacent, MOSFET cell (see fig.1, the drain of M1 is connected to the source of M2); the cascading terminal of each of the MOSFET cells is connected to the gate terminal of an adjacent, MOSFET cell (C1 is connected to Rg2); and, the drain terminal and cascading terminal of the nth MOSFET cell (containing M2) is connected to a supply voltage (P); such that: in an off state, the supply voltage (Vs) provided across the cascading terminal of the nth cell and the source terminal of the first cell charges the balance capacitor CB of each cell (inherently present); and, upon provision of a gate driving voltage to the gate terminal of the first cell (N=1) to activate the MOSFET (M,) of the first cell, the balance capacitor (C,) discharges to the gate terminal of the adjacent cell to switch on the MOSFET (M2) thereof (inherently present).
The difference seen between Ren Yu et al. reference and the present invention is that Ren Yu et al. reference shows only the first MOSFET cell with a cathode-cathode series connected Zener diodes (Zd1 and Zd2) and the second MOSFET cell has one Zener diode. Ren Yu et al. suggests the using of a single Zener diode in a second MOSFET cell instead of two cathode-cathode Zener diodes is to reduce cost. Thus, one skilled in the art would have been readily recognized the additional Zener in the second MOSFET cell would have not changed the circuit operation. Therefore, outside of any non-obvious results, the obviousness of using two cathode-cathode Zener diodes in each MOSFET cell will not be patentable under 35USc 103.
Regarding claim 2, wherein n >= 2, and upon activation of the MOSFET (M2) of the second cell, the balance capacitor (C2) is capable of discharging to the gate terminal of the adjacent cell to switch the MOSFET (M3) thereof.
Regarding claim 5, wherein each MOSFET cell from N=1 to N=(n-1) comprises a supply diode Ds (D1) directed from the gate terminal to the cascading terminal.
Claim 7, insofar being understood, depends on claim 1 calls for “wherein capacitance of the balance capacitors of the MOSFET cells N=1 to N=(n-1) are identical” is also anticipated by Ren Yu et al.’s capacitors C2 assumed to be equal in all MOSFET cells unless stated otherwise.
Regarding claim 10, Ren Yu et al.’s switch circuit operable with power supply of 1.2kv instead of greater 2kv as called for in claim 10. However, one skilled in the art would have readily recognized that Ren Yu et al.’s can also operate at high power supply with bigger transistors and more cells. Therefore, outside of any non-obvious results, the obviousness on including more cells and bigger transistors in order operable with power supply greater than 2Kv will not be patentable under 35USC 103.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ren Yu et al. “A Single Gate Driver Based Solid State Circuit Breaker Using Series Connected SiC MOSFETs” in view of Thomson (EP 0215707A1), Applicant’s cited prior art.
Regarding claims 3 and 5, Ren Yu et al. reference discloses a switching circuit comprising all the aspects of the present invention except only the first MOSSFET cell comprises a supply diode Ds (D1) directed from the gate terminal to the cascading terminal instead of having each MOSSFET cell comprises a supply diode Ds (D1) directed from the gate terminal to the cascading terminal as called for in claims 3 and 5.
Thomson’s figure 1 show a switching circuit with stacked transistors for handling high voltage application comprising a supply diode (D8) directed from the gate terminal to the cascading terminal to guarantee positive gate voltage (forward biasing of the diode). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include a supply diode in a second MOSFET cells for the purpose of guarantee positive gate voltage as taught by Thomson reference.
Regarding claim 4,Thomson’s figure 1 shows the supply diode Ds can be selectively disconnected in the final cell (N=n).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ren Yu et al. “A Single Gate Driver Based Solid State Circuit Breaker Using Series Connected SiC MOSFETs” in view of Mott et al. (US 2013/0002149), Applicant’s cited prior art.
Regarding claim 6, Ren Yu et al. reference discloses a switching circuit comprising all the aspects of the present invention as noted above except the balance capacitor of the MOSFET cell N=n has a capacitance at least twice as high as the balance capacitors of the MOSFET cells N=1 to N=(n-1) as called for in claim 6.
Mott et al.’s figure 6A shows a switching circuit comprising a plurality of MOSFET cells each including a balance capacitor (CP) and the cell N=n has a capacitance at least multiple time high of the balance capacitors of the MOSFET cells N=1 to N=(n-1) (see paragraph 0079 and 0080). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Ren Yu et al.’s capacitance of a balance capacitor of the MOSFET cell N=n at least twice as high as the capacitance of the balance capacitors of the MOSFET cells N=1 to N=(n-1) as taught by Mott et al. reference.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN T LAM/Primary Examiner, Art Unit 2842 10/2/2025