DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The instant application with Application Number 18/702,328 filed on 04/18/2024 is presented for examination. As per the remarks of 05/31/2024, claims 7, 15 and 16 are amended. Claims 1-17 are pending.
Information Disclosure Statment
The Information Disclosure Statement dated 04/17/2024 is acknowledged and the cited references have been considered in this examination.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 16-17 are rejected under 35 U.S.C. 102(a1) as being anticipated by Qian et al. (CN114487761).
With respect to claim 1, Qian discloses a temperature detection circuit, including an enable signal generation module and a detection output module, wherein: the enable signal generation module is configured to segmentally generate four detection enable signals including an ultra-low temperature detection enable signal, a low temperature detection enable signal, a high temperature detection enable signal and an ultra-high temperature detection enable signal (Paraa. # 0050: the status signal T_abv_n10 corresponding to the minimum protection temperature detection item, the status signal T_abv_0 corresponding to the first intermediate temperature detection item, the status signal T_abv_45 corresponding to the second intermediate temperature detection item, the status signal T_abv_60 corresponding to the maximum protection temperature detection item, the status signal ovp_t corresponding to the overvoltage threshold detection item, the status signal uvp_t corresponding to the undervoltage threshold detection item, the status signal occ_t corresponding to the maximum charging current threshold detection item, and the status signal ocd_t corresponding to the maximum discharging current threshold detection item); the detection output module is connected to an output terminal of the enable signal generation module (Fig. 1, 230; Para. # 0115: object selection unit 220 outputs a first selection signal det_X, it will trigger the detection enable unit 230 to output a second selection signal sen_X representing the same item to be detected based on the second enable signal sen_det), and is configured to segmentally generate four thresholds including an ultra-low temperature threshold, a low temperature threshold, a high temperature threshold, and an ultra-high temperature threshold based on the four detection enable signals (Para. # 0120: in the fourth small cycle, the first intermediate temperature detection item v_0 is detected, and the result is that this detection item is triggered, so the circuit allows discharge but prohibits charging, and in the next first polling clock signal phase<1>, only the undervoltage threshold detection item uvp is detected until the trigger state of the first intermediate temperature detection item v_0 is released, that is, the battery temperature is higher than the first intermediate temperature),
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and sequentially compare the four thresholds with a detection value, wherein a charging-prohibited signal is valid when a low temperature protection or a high temperature protection is triggered, and a charging-prohibited/discharging-prohibited signal is valid when an ultra-low temperature protection or an ultra-high temperature protection is triggered (Paa. # 0097: the circuit will sequentially detect detection item V_60. When the chip temperature is detected to be higher than the maximum protection temperature (e.g., 60 degrees Celsius), the circuit will shut down the main transmission transistor and prohibit charging and discharging).
With respect to claim 2, Qian discloses the temperature detection circuit as described above, wherein the enable signal generation module includes a timing unit (Para. # 0005: based on the priority of multiple detection items, enabling the timely allocation of time), a total enable signal generation unit (Para. #0007: a plurality of first enable signals from the multiple enable signals, and detects the multiple status signals based on the priority of the multiple polling clock signals, the plurality of first enable signals, and the multiple detection items, so as to generate a first selection signal according to the detection result; and a detection enable unit, which is connected to the polling clock generation unit and the polling object selection unit respectively, and generates a second selection signal based on a second enable signal from the multiple enable signals), and a detection enable signal generation unit (Fig. 1, 200/230; para. # 0072: The detection enable unit 230 is connected to the polling clock generation unit 210 a); wherein the timing unit is configured to generate a power-on signal during power-on, and then perform a timing operation (Fig. 3, timing wave form; Para. 0062: selection unit 220 includes a first priority processing subunit 221, a timing and clock adjustment subunit 222, and a second priority processing subunit 223); the total enable signal generation unit is connected to a signal output terminal of the timing unit (Fig. 1, 400), and is configured to generate a total enable signal based on the power-on signal when neither an over-charge protection nor an over-discharge protection is triggered; and the detection enable signal generation unit is connected to a timing output terminal of the timing unit and an output terminal of the total enable signal generation unit, and is configured to segmentally generate the four detection enable signals based on a timing result of the timing unit when the total enable signal is valid (Par. # 0075: the maximum protection temperature detection item, feedback signal vfb_ovp corresponding to the overvoltage threshold detection item, feedback signal vfb_uvp corresponding to the undervoltage threshold detection item, feedback signal vfb_occ corresponding to the maximum charging current threshold detection item, and feedback signal vfb_ocd corresponding to the maximum discharging current threshold detection item).
With respect to claim 16, Qian discloses a temperature detection chip, including the temperature detection circuit (Para. # 0026: detection circuit, method, and battery protection chip based on a battery protection chip).
With respect to claim 17, Qian discloses a temperature detection system, including the temperature detection chip (Para. # 0005, 0014-0015: battery protection chip provided by the present invention includes: a polling detection circuit based on the battery protection chip as described above, used to poll and detect the multiple detection items according to their priority, and generate multiple status signals according to the polling detection results).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 4-15 are dependent on the above objected claim of 3.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YALKEW FANTU whose telephone number is (571)272-8928. The examiner can normally be reached Monday-Friday 7:00AM-4:00PM.
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/YALKEW FANTU/Primary Examiner, Art Unit 2859
