Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office action, in response to the response to the restriction and amendment received 12/17/2025, is a non-final office action.
Election/Restrictions
2. Claims 13-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/17/2025. Claims 13-24 have been cancelled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
3. Claims 26-32 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claims 26-32 each recite the claims depend on the method of claim 13. However, claim 13 has been cancelled. It is believed each of these claims should depend on claim 25. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1, 2, 5, 8-10, 25-30 and 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al (US 8,873,606).
Regarding claim 1, Zhang discloses a wireless receiver device (Figure 6. Column 17, lines 4-12: embodiments can be incorporated into various types of communication systems such as traditional and wireless local area networks (LANs and WLANs and wired and wireless point-to-point connections.) comprising:
a wireless receiver circuit comprising an antenna configured to receive digital media content wirelessly from a source transmitter of a source device (Figure 6. Column 17, lines 4-12: embodiments can be incorporated into various types of communication systems such as traditional and wireless local area networks (LANs and WLANs) and wired and wireless point-to-point connections. Wireless signals are received via an antenna. The data content of the received signal does not change the receiver to a particular structure and therefore, does not limit the scope of the claim.);
a media content processing circuit configured to receive digital media data from the wireless receiver circuit and prepare the received digital media data for output (Figure 6: first mux 210 receives the timing signal from clock divider 228. Column 8, line 62 to column 9, line 3: first mux 210 converts K third parallel signals 242 to analog signals before providing L third parallel signals 244 to parallel to serial converter 212.);
a media content output circuit configured to receive the prepared digital media data and to output the prepared digital media data with a defined timing (Figure 6. Second mux 220 and parallel-to-serial converter 212: Second mux 220 receives the timing signal from clock divider 228. Parallel-to-serial converter 212 also receives signals from first mux 210. P/S 212 receives a clock signal from phase interpolator 226. Column 10, line 56 to column 11, line: Second mux 220 may be configured to receive M delayed fourth parallel signals 254. Second mux 220 may be configured to receive and convert M delayed fourth parallel signals 254 into L fifth parallel signals. Fifth parallel signals 256 may be received by parallel to serial converter 212.);
an oscillator (Figure 6: PLL 230);
a first clock signal generator coupled to an output of the oscillator (Figure 6: clock divider 228 receives the output of PLL 230.), the first clock signal generator configured to generate first timing signals for the media content processing circuit and the media content output circuit (Figure 6: clock divider 228 provides timing signals to second mux 220 and first mux 210.);
a clock compensation circuit coupled to the first clock signal generator (Figure 6: at least first phase interpolator 222, second phase interpolator 226, phase detector 604 and digital core 208. Phase detector 604 receives the output of clock divider 228.), the clock compensation circuit configured to:
receive a timing reference from the source transmitter of the source device (Figure 6: phase detector 604 receives a timing reference signal 258 from the source transmitter of the source device.),
receive the first timing signals from the first clock signal generator (Figure 6: Phase detector 604 receives the output of clock divider 228.),
adjust a phase and/or adjust a frequency of the first timing signals (Figure 6: phase detector 604 and digital core 208. Figure 7. Column 14, lines 1-41: Phase detector 604 may output a phase difference signal 608 indicating a difference in phase between divided receive clock signal 258 and divided transmit clock signal 262. Column 14, lines 42-63: Digital filter 702 may be configured to receive digital phase difference signal 610 as an input and may output phase adjustment signal 710.); and
output adjusted first timing signals (Figure 6: phase detector 604 and digital core 208. Figure 7. Column 14, lines 1-41: Phase detector 604 may output a phase difference signal 608 indicating a difference in phase between divided receive clock signal 258 and divided transmit clock signal 262. Column 14, lines 42-63: Digital filter 702 may be configured to receive digital phase difference signal 610 as an input and may output phase adjustment signal 710.); and
a second clock signal generator configured to receive the adjusted first timing signals from the clock compensation circuit and to output second timing signals for clocking the media content output circuit (Figure 7: at least clock and recovery logic 704, jitter filter 712, selection logic 708. Column 15, lines 9-21: selection logic 708 is configured to select either phase adjustment signal 710 or phase comparator signal 712. The selected signal is received by second phase interpolator 226 as second control signal.), wherein the clock compensation circuit is configured to compare the second timing signals to the timing reference received from the source transmitter of the source device (Figure 6: digital core 208 provides outputs to first phase interpolator 222 and second phase interpolator 226. First phase interpolator receives the second timing signals from selection logic 708 and the timing reference from the source transmitter.).
Regarding claim 2, Zhang discloses wherein the media content output circuit comprises a digital to analog converter coupled to an output transducer (Column 8, line 62 to column 9, line 3: in another embodiment, parallel to serial converter 212 receives third parallel signals as digital signals and converts L third parallel signals 224 into analog signals before providing analog serial output signal 246 to driver 244.).
Regarding claim 5, Zhang discloses wherein the clock compensation circuit is configured to receive a first timing reference signal from the wireless receiver circuit (Figure 6: PLL 230 provides a clock signal to clock divider 228.).
Regarding claim 8, Zhang discloses wherein the clock compensation circuit comprises at least one of a drift compensation circuit or a phase compensation circuit (Figure 6: phase detector 604 and digital core 208. Figure 7. Column 14, lines 1-41: Phase detector 604 may output a phase difference signal 608 indicating a difference in phase between divided receive clock signal 258 and divided transmit clock signal 262. Column 14, lines 42-63: Digital filter 702 may be configured to receive digital phase difference signal 610 as an input and may output phase adjustment signal 710.).
Regarding claim 9, Zhang discloses wherein the wireless receiver device is a first wireless receiver device of a plurality of wireless receiver devices, and each wireless receiver device of the plurality of wireless receiver devices is coupled to the source transmitter of the source device and configured to receive the timing reference from the source device (Figure 6: the receiver is coupled to the transmitter and receives the timing reference from the transmitter. A plurality of wireless receiver devices are not components of the wireless receiver recited in the claim. Any additional receiver devices will be external to the recited wireless receiver device of claim 1 and therefore do not limit the recited wireless receiver device to a particular structure. Therefore the claim is not limited in scope.).
Regarding claim 10, Zhang discloses wherein each wireless receiver device of the plurality of wireless receiver devices (Figure 6: the receiver is coupled to the transmitter and receives the timing reference from the transmitter. A plurality of wireless receiver devices are not components of the wireless receiver recited in the claim. Any additional receiver devices will be external to the recited wireless receiver device of claim 1 and therefore do not limit the recited wireless receiver device to a particular structure. Therefore the claim is not limited in scope.)are configured to: determine an offset based on detecting a time difference between the timing reference from the source device and a timing signal from a corresponding clock signal generator at each wireless receiver device (Figure 6: phase detector 604 and digital core 208. Figure 7. Column 14, lines 1-41: Phase detector 604 may output a phase difference signal 608 indicating a difference in phase between divided receive clock signal 258 and divided transmit clock signal 262. Column 14, lines 42-63: Digital filter 702 may be configured to receive digital phase difference signal 610 as an input and may output phase adjustment signal 710.); and adjust the timing signal from the corresponding clock signal generator to a predetermined value based on the offset (Figure 6: phase detector 604 and digital core 208. Figure 7. Column 14, lines 1-41: Phase detector 604 may output a phase difference signal 608 indicating a difference in phase between divided receive clock signal 258 and divided transmit clock signal 262. Column 14, lines 42-63: Digital filter 702 may be configured to receive digital phase difference signal 610 as an input and may output phase adjustment signal 710.).
Regarding claim 25, Zhang discloses a method comprising:
receiving, using an antenna of a wireless receiver circuit, digital media content wirelessly from a source transmitter of a source device (Figure 6. Column 17, lines 4-12: embodiments can be incorporated into various types of communication systems such as traditional and wireless local area networks (LANs and WLANs and wired and wireless point-to-point connections.);
receiving, using a media content processing circuit, digital media data from the wireless receiver circuit (Figure 6. Column 17, lines 4-12: embodiments can be incorporated into various types of communication systems such as traditional and wireless local area networks (LANs and WLANs) and wired and wireless point-to-point connections. Wireless signals are received via an antenna. The data content of the received signal does not change the receiver to a particular structure and therefore, does not limit the scope of the claim.);
preparing, using the media content processing circuit, the received digital media data for output (Figure 6: first mux 210 receives the timing signal from clock divider 228. Column 8, line 62 to column 9, line 3: first mux 210 converts K third parallel signals 242 to analog signals before providing L third parallel signals 244 to parallel to serial converter 212.);
receiving, using a media content output circuit, the prepared digital media data (Figure 6. Second mux 220 and parallel-to-serial converter 212: Second mux 220 receives the timing signal from clock divider 228. Parallel-to-serial converter 212 also receives signals from first mux 210. P/S 212 receives a clock signal from phase interpolator 226. Column 10, line 56 to column 11, line: Second mux 220 may be configured to receive M delayed fourth parallel signals 254. Second mux 220 may be configured to receive and convert M delayed fourth parallel signals 254 into L fifth parallel signals. Fifth parallel signals 256 may be received by parallel to serial converter 212.);
outputting, using the media content output circuit, the prepared digital media data with a defined timing (Figure 6. Second mux 220 and parallel-to-serial converter 212: Second mux 220 receives the timing signal from clock divider 228. Parallel-to-serial converter 212 also receives signals from first mux 210. P/S 212 receives a clock signal from phase interpolator 226. Column 10, line 56 to column 11, line: Second mux 220 may be configured to receive M delayed fourth parallel signals 254. Second mux 220 may be configured to receive and convert M delayed fourth parallel signals 254 into L fifth parallel signals. Fifth parallel signals 256 may be received by parallel to serial converter 212.);
generating, using a first clock signal generator coupled to an output of an oscillator, first timing signals for the media content processing circuit and the media content output circuit (Figure 6: clock divider 228 receives the output of PLL 230 and clock divider 228 provides timing signals to second mux 210 and first mux 210.);
receiving, using a clock compensation circuit coupled to the first clock signal generator, a timing reference from the source transmitter of the source device (Figure 6: phase detector 604 receives a timing reference signal 258 from the source transmitter of the source device.);
receiving, using the clock compensation circuit coupled to the first clock signal generator, the first timing signals from the first clock signal generator (Figure 6: Phase detector 604 receives the output of clock divider 228.);
adjusting, using the clock compensation circuit coupled to the first clock signal generator, a phase and/or adjust a frequency of the first timing signals (Figure 6: phase detector 604 and digital core 208. Figure 7. Column 14, lines 1-41: Phase detector 604 may output a phase difference signal 608 indicating a difference in phase between divided receive clock signal 258 and divided transmit clock signal 262. Column 14, lines 42-63: Digital filter 702 may be configured to receive digital phase difference signal 610 as an input and may output phase adjustment signal 710.);
outputting, using the clock compensation circuit coupled to the first clock signal generator, adjusted first timing signals (Figure 6: phase detector 604 and digital core 208. Figure 7. Column 14, lines 1-41: Phase detector 604 may output a phase difference signal 608 indicating a difference in phase between divided receive clock signal 258 and divided transmit clock signal 262. Column 14, lines 42-63: Digital filter 702 may be configured to receive digital phase difference signal 610 as an input and may output phase adjustment signal 710.);
receiving, using a second clock signal generator, the adjusted first timing signals from the clock compensation circuit (Figure 7: at least clock and recovery logic 704, jitter filter 712, selection logic 708. Column 15, lines 9-21: selection logic 708 is configured to select either phase adjustment signal 710 or phase comparator signal 712. The selected signal is received by second phase interpolator 226 as second control signal.);
outputting, using the second clock signal generator, second timing signals for clocking the media content output circuit (Figure 7: at least clock and recovery logic 704, jitter filter 712, selection logic 708. Column 15, lines 9-21: selection logic 708 is configured to select either phase adjustment signal 710 or phase comparator signal 712. The selected signal is received by second phase interpolator 226 as second control signal.); and
comparing, using the clock compensation circuit, the second timing signals to the timing reference received from the source transmitter of the source device (Figure 6: digital core 208 provides output A to first phase interpolator 222 and second phase interpolator 226. First phase interpolator receives the second timing signals from selection logic 708 and the timing reference from the source transmitter.).
Regarding claim 26, Zhang discloses wherein the media content output circuit comprises a digital to analog converter coupled to an output transducer (This claim does not limit the method in terms of scope since it does not require a step to be performed. Zhang: Column 8, line 62 to column 9, line 3: in another embodiment, parallel to serial converter 212 receives third parallel signals as digital signals and converts L third parallel signals 224 into analog signals before providing analog serial output signal 246 to driver 244.).
Regarding claim 27, Zhang discloses wherein the second clock signal generator and the media content output circuit are on a different integrated circuit from the first clock signal generator (this claim does not limit the recited method in terms of scope since the recited claim does not require a step to be performed.).
Regarding claim 28, Zhang discloses wherein the clock compensation circuit is configured to receive a first timing reference signal from the wireless receiver circuit (Figure 6: PLL 230 provides a clock signal to clock divider 228.).
Regarding claim 29, Zhang discloses wherein the clock compensation circuit comprises at least one of a drift compensation circuit or a phase compensation circuit (Figure 6: phase detector 604 and digital core 208. Figure 7. Column 14, lines 1-41: Phase detector 604 may output a phase difference signal 608 indicating a difference in phase between divided receive clock signal 258 and divided transmit clock signal 262. Column 14, lines 42-63: Digital filter 702 may be configured to receive digital phase difference signal 610 as an input and may output phase adjustment signal 710.).
Regarding claim 30, Zhang discloses wherein the wireless receiver device is a first wireless receiver device of a plurality of wireless receiver devices, and each wireless receiver device of the plurality of wireless receiver devices is coupled to the source transmitter of the source device and configured to receive the timing reference from the source device (Figure 6: the receiver is coupled to the transmitter and receives the timing reference from the transmitter. A plurality of wireless receiver devices are not steps in the method recited in the claim. The format of any additional receiver devices do not require a step to be performed and therefore the claim is not limited in scope.).
Regarding claim 32, Zhang discloses wherein the wireless receiver circuit is configured to receive the digital media content wirelessly from the source transmitter of the source device via a wireless low-power personal area network (Figure 6. Column 17, lines 4-12: embodiments can be incorporated into various types of communication systems such as traditional and wireless local area networks (LANs and WLANs and wired and wireless point-to-point connections. The wireless local area network will be low-power compared to high power networks.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 3, 4, 11, 12, 31 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 8,873,606) in view of Li et al (US 10,389,486).
Regarding claim 3, Zhang discloses the wireless receiver stated above. Zhang discloses the communication system for transmitting and receiving data is applicable in a telecommunications network in column 1, lines 12-24. Though Zhang discloses communicating telecommunications data, Zhang does not disclose the data content is digitally encoded audio and the receiver comprises a speaker.
Li discloses the communication network shown in figure 1. Column 1, lines 22-29 discloses recent years have seen the expansion of Bluetooth technology beyond the standard feature of cell phones and personal computers into diverse applications including internet of things systems and devices such as wireless speakers and headphones and more. Bluetooth (BT) and Bluetooth Low Energy (BLE) are unsurpassed for use in devices and systems that need to wirelessly send short bursts of data over short distances. Cellphones will comprise a speaker. The Bluetooth communications system will comprise a personal area network. Column 4, lines 39-50 discloses the antenna 102 can also be integrally formed on the same IC chip or on separate IC chip.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of Bluetooth as taught by Li into the wireless device of Zhang to achieve the unsurpassed advantages as stated by Li.
Regarding claim 4, Zhang discloses the wireless receive as stated above. Zhang does not disclose wherein the second clock signal generator and the media content output circuit are on a different integrated circuit from the first clock signal generator.
Li discloses the communication network shown in figure 1. Column 1, lines 22-29 discloses recent years have seen the expansion of Bluetooth technology beyond the standard feature of cell phones and personal computers into diverse applications including internet of things systems and devices such as wireless speakers and headphones and more. Bluetooth (BT) and Bluetooth Low Energy (BLE) are unsurpassed for use in devices and systems that need to wirelessly send short bursts of data over short distances. Cellphones will comprise a speaker. The Bluetooth communications system will comprise a personal area network. Column 4, lines 39-50 discloses the antenna 102 can also be integrally formed on the same IC chip or on separate IC chip. By implementing signal components on separate IC chips, interference between components can be reduced and replacement or repairs of components can be simplified. For these reasons, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Li into the wireless receiver of Zhang.
Regarding claims 11 and 31, Zhang discloses the wireless receiver stated above. Zhang discloses the communication system for transmitting and receiving data is applicable in a telecommunications network in column 1, lines 12-24. Though Zhang discloses communicating telecommunications data, Zhang does not disclose the wireless receiver device and the source device are Bluetooth Low Energy (BLE) devices.
Li discloses the communication network shown in figure 1. Column 1, lines 22-29 discloses recent years have seen the expansion of Bluetooth technology beyond the standard feature of cell phones and personal computers into diverse applications including internet of things systems and devices such as wireless speakers and headphones and more. Bluetooth (BT) and Bluetooth Low Energy (BLE) are unsurpassed for use in devices and systems that need to wirelessly send short bursts of data over short distances. Cellphones will comprise a speaker. The Bluetooth communications system will comprise a personal area network. Column 4, lines 39-50 discloses the antenna 102 can also be integrally formed on the same IC chip or on separate IC chip.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of Bluetooth as taught by Li into the wireless device of Zhang to achieve the unsurpassed advantages as stated by Li.
Regarding claims 12 and 32, Zhang discloses the wireless receiver stated above. Zhang discloses using a WLAN (Figure 6. Column 17, lines 4-12: embodiments can be incorporated into various types of communication systems such as traditional and wireless local area networks (LANs and WLANs and wired and wireless point-to-point connections. The wireless local area network will be low-power compared to high power networks.) but doesn’t explicitly recite communicating via a low-power personal area network.
Li discloses the communication network shown in figure 1. Column 1, lines 22-29 discloses recent years have seen the expansion of Bluetooth technology beyond the standard feature of cell phones and personal computers into diverse applications including internet of things systems and devices such as wireless speakers and headphones and more. Bluetooth (BT) and Bluetooth Low Energy (BLE) are unsurpassed for use in devices and systems that need to wirelessly send short bursts of data over short distances. Cellphones will comprise a speaker. The Bluetooth communications system will comprise a personal area network. Column 4, lines 39-50 discloses the antenna 102 can also be integrally formed on the same IC chip or on separate IC chip.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the features of Bluetooth as taught by Li into the wireless device of Zhang to achieve the unsurpassed advantages as stated by Li.
Allowable Subject Matter
6. Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the references disclose the features of claims 6 and 7. Zhang discloses the wireless receiver shown in figure 6. Zhang discloses outputting updated timing signals via the digital core 208 as shown in figures 6 and 7. Zhang discloses outputting data signals from driver 214. Zhang does not disclose the output from the P/S 246 or driver 214 is a timing signal that is received by the clock compensation circuit that comprises a feedback loop that compares the first timing reference signal with the second timing reference signal in the media content output circuit as recited in claims 6 and 7.
Conclusion
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/KEVIN M BURD/Primary Examiner, Art Unit 2632 2/5/2026