DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the step of wire bonding metal wires to the ohmic contacts of claim 13 must be shown or the features canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 18 and 19 are objected to because of the following informalities: it's unclear if "is obtainable by ALD" simply means that the structure is formed using ALD, or something else. Please adjust the wording accordingly (suggested change: "is formed using ALD"). For examination, the limitation was interpreted as referring to being formed by ALD. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Claim(s) 14-16, and 25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Asad et al. ("The Dependence of the High-Frequency Performance of Graphene Field-Effect Transistors in Channel Transport Properties"), hereinafter referred to as "Asad".
In regards to claim 14, Asad discloses an electronic device precursor comprising: a substrate (Si/SiO2 in Asad figures 2i-2iii); a patterned dielectric-material-capped graphene layer structure comprising a first dielectric material (1st dielectric layer in Asad figures 2i-2iii) on a graphene layer structure on the substrate (graphene in Asad figures 2i-2iii); ohmic contacts on the substrate (S and D in Asad figures 2ii-2iii), each ohmic contact adjacent an edge of the patterned dielectric-material-capped graphene layer structure (See Asad figure 2); and a second dielectric material on and across the patterned dielectric-material-capped graphene layer structure, the ohmic contacts, and at least an adjacent portion of the substrate (2nd dielectric layer in Asad figure 2iii); wherein the patterned dielectric-material-capped graphene layer structure has an area of 20 mm2 or less (Asad page 458 beginning of method section. Asad discusses GFETs with a gate width of 30µm and a gate length of 0.5µm – 2µm, which is a maximum value of 60µm2, which is less than 200mm2).
In regards to claim 15, the limitation “wherein the electronic device precursor is for forming a Hall sensor.” is recited, which gives the intended use of the electronic device precursor. As the device of Asad is in its precursor state in figure 2(iii), it would be able to be used to form a Hall sensor. It has been shown by the courts that "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" (see MPEP 2114(II)), so long as the prior art apparatus teaches all of the structural limitations of the claim. Thus, Asad’s device precursor, meeting all of the structural limitations of claim 14 and being capable of use in the way claim 15 recites, meets the claimed limitation.
In regards to claim 16, Asad discloses all of the limitations of claim 14, and further discloses that the graphene layer structure is formed on the substrate by CVD (Asad page 458, first column).
In regards to claim 25, Asad discloses all of the limitations of claim 14, and further discloses the thickness of the first dielectric material is greater than 5 nm, and/or less than 100 nm (it is 5nm, Asad page 458 second column).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
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Claims 1-2, 4, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (CN 103985762 A), hereinafter referred to as "Wei" in view of Asad.
In regards to claim 1, Wei discloses A method of producing an electronic device precursor, the method comprising: providing a substrate (1 in Wei figure 2)having a graphene layer structure on and across a surface thereof (graphene layer 2 in Wei figure 2); forming a first layer of dielectric material on and across the graphene layer structure by ALD (3 in Wei figure 3, see Wei translation paragraph 0025); forming a first patterned resist on the first layer of dielectric material (4 in Wei figure 4) to provide at least one protected region of dielectric material and underlying graphene (area under 4), and at least one unprotected region of dielectric material and underlying graphene (areas to left and right of 4); etching away the at least one unprotected region (Wei figures 5 and 6) to expose one or more corresponding portions of the substrate and thereby define at least one region of dielectric- material-capped graphene layer structure having one or more exposed edges (substrate is exposed on left and right of Wei figure 6, and the stack of 2 and 3 has left and right edges exposed); forming a second patterned resist on or over the region of dielectric-material-capped graphene layer structure and on sub-portions of the exposed portions of the substrate (4 in Wei figure 9) to define contact portions adjacent the one or more exposed edges; forming ohmic contacts in the contact portions (8 in Wei figure 7); exposing the dielectric material of the dielectric-material-capped graphene layer structure region by removing substantially all resist material (Wei figure 10);
Wei does not disclose forming a second dielectric layer.
Asad teaches forming a second layer of dielectric material on and across the at least one region of dielectric-material-capped graphene layer structure, the ohmic contacts and at least an adjacent portion of the substrate (Asad figure 2, see page 458, second column). Asad also teaches that this layer prevents short circuiting by overlapping the gate fingers (Asad page 458, second column).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the step of forming a second layer of dielectric material from Asad to the method of Wei in order to prevent short circuits.
In regards to claim 2, Wei in view of Asad discloses all of the limitations of claim 1. Wei further discloses that between steps of etching and of forming a second patterned resist, the first patterned resist is removed (Wei figure 8).
In regards to claim 4, Wei in view of Asad discloses all of the limitations of claim 1. Wei further discloses that the first layer of dielectric material and/or the second layer of dielectric material is an inorganic oxide (the first dielectric is TiO2, see Wei translation paragraph 0025).
In regards to claim 7, Wei in view of Asad discloses all of the limitations of claim 1. Asad further teaches that forming a second layer of dielectric material is by ALD (Asad figure 2, see page 458, second column) on and across the at least one region of dielectric- material-capped graphene layer structure, the ohmic contacts, and the entire substrate (Asad figure 2).
In regards to claim 8, Wei in view of Asad discloses all of the limitations of claim 1. Wei further discloses that forming a resist to provide the at least one protected region comprises forming:(i) one or more rectangular shaped regions of the resist and wherein the electronic device precursor is for forming a transistor; or (ii) one or more cross-shaped regions of the resist and wherein the electronic device precursor is for forming a Hall-sensor (resist 4 is rectangular in Wei figure 4 for forming a transistor).
In regards to claim 9, Wei in view of Asad discloses all of the limitations of claim 1. Wei does not explicitly discuss the dimensions of the graphene layer.
Asad teaches that a longest dimension of the graphene layer structure is 5 mm or less, and/or wherein an area of the graphene laver structure is 20 mm2 or less (Asad page 458 beginning of method section. Asad discusses GFETs with a gate width of 30µm and a gate length of 0.5µm – 2µm, which is a maximum value of 60µm2, which is less than 20mm2).
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dimensions of the device be small as in Asad in order to increase the device density in any application of the device.
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Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of Asad as applied to claim 1 above, and further in view of Liang et al. (CN 103107077 A), hereinafter referred to as "Liang".
In regards to claim 5, Wei in view of Asad discloses all of the limitations of claim 1. Wei further discloses a step of plasma etching to remove any remaining residue (Wei figure 6, see Wei translation paragraph 0025. The graphene layer 2 was not removed during the previous etch, and thus can be considered a residue).
Neither Wei nor Asad teach that the etching is reactive ion etching.
Liang teaches a method of manufacturing a semiconductor on graphene that includes etching that comprises reactive ion etching (Liang paragraph 0048, figure 5). Liang also teaches that this patterning method etches through both the dielectric material and the graphene material (Liang paragraph 0048).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the reactive ion etching of Liang in order to reduce the number of processing steps by etching both the first dielectric layer and the graphene layer in one etch.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of Asad as applied to claim 1 above, and further in view of Shirley (US 20220291400 A1), Hereinafter referred to as "Shirley".
In regards to claim 11, Wei in view of Asad discloses all of the limitations of claim 1. Neither Wei nor Asad explicitly disclose an array of the protected regions for the precursors.
Shirley teaches forming an array of GFETs (Shirley paragraph 0121), and further teaches that this produces many GFET devices at the same time (Shirley paragraph 0121).
In the process disclosed by Wei, a protected region is formed, corresponding to 1 device precursor. Therefore, applying Shirley’s teaching to Wei’s method would result in forming an array of protected regions, each corresponding to an electronic device precursor.
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form an array of these, as in Shirley, in order to produce many devices at once, which would also reduce the number of manufacturing steps.
In regards to claim 12, Wei in view of Asad and further in view of Shirley teaches all of the limitations of claim 11. Neither Wei nor Asad explicitly teach dicing electronic device precursors from an array.
Shirley further teaches dicing the substrate to separate electronic device precursors from the array, after step (viii) of forming a second layer of dielectric material (Shirley paragraph 0121. Shirley teaches dicing after the other device forming steps are done, so it would naturally be done after the last step of Wei’s method modified by Asad). Shirley teaches that this is done to make individual GFET chips.
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the dicing step of Shirley in order to make many individual chips from the array.
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Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of Asad as applied to claim 1 above, and further in view of Eckinger et al. (US 20150102807 A1), hereinafter referred to as "Eckinger".
In regards to claim 13, Wei in view of Asad discloses all of the limitations of claim 1. Wei does not disclose a step of wire bonding wires to the ohmic contacts.
Eckinger teaches a step of wire bonding metal wires to the ohmic contacts through the second layer of dielectric material (Eckinger figure 1H, paragraph 0033). Eckinger also teaches that this is to electrically connect the contacts to a further structure.
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the wire bonding step of Eckinger in order to electrically connect the contacts to a further structure.
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Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (CN 106920847 A), hereinafter referred to as "Song", in view of Wei and further in view of Asad.
In regards to claim 3, Song discloses a method of producing an electronic device precursor, the method comprising: providing a substrate (1 and 2 in Song figure 3a) having a graphene layer structure on and across a surface thereof (3 in Song figure 3a); forming a first layer of dielectric material on and across the graphene layer structure (4 in Song figure 3b); forming a first patterned resist on the first layer of dielectric material (Song figure 3c) to provide one protected region of dielectric material and underlying graphene (center portion in 3c), and a plurality of unprotected regions of dielectric material and underlying graphene (uncovered areas to the left and right of center area); etching away the plurality of unprotected regions (Song figure 3d) to expose corresponding portions of the substrate and thereby define one first region of dielectric-material-capped graphene layer structure having a plurality of exposed edges (center has exposed edges on left and right) and to define contact portions adjacent the one or more exposed edges (recesses on left and right of the center portion); forming ohmic contacts in the contact portions (5 and 6 in Song figure 3e); exposing the dielectric material of the dielectric-material-capped graphene layer structure region by removing substantially all resist material (Song figure 3e); forming a second patterned resist on the first region of dielectric-material-capped graphene layer structure, and optionally the ohmic contacts (Song figure 3f), to provide at least one protected region of dielectric material and underlying graphene adjacent a plurality of the ohmic contacts (protected center portion under the resist material), and at least one unprotected region of dielectric material and underlying graphene (unprotected regions on the far left and right); etching away the at least one unprotected region (Song figure 3f/3g) to expose one or more corresponding portions of the substrate and thereby define at least one second region of dielectric-material-capped graphene layer structure having a plurality of exposed edges whereby each ohmic contact remains adjacent an edge of the at least one second region of dielectric- material-capped graphene layer structure (center stack of 3&4 in figure 3g); exposing the dielectric material of the at least one second region of dielectric- material-capped graphene layer structure by removing substantially all resist material (Song figure 3g/3h);
Song does not disclose that the first dielectric layer is formed using ALD, nor does it disclose that the etching etches through the graphene to expose the substrate.
Wei teaches forming a first layer of dielectric material on and across the graphene layer structure by ALD (Wei translation paragraph 0025). Wei also teaches etching through the graphene layer to expose the substrate (Wei figure 6). Wei teaches that this greatly reduces the contact resistance of the graphene and the metal, which increases the maximum oscillation frequency and is beneficial for applying in a graphene field effect transistor (Wei abstract).
Neither Song nor Wei teaches forming a second dielectric layer.
Asad teaches forming a second layer of dielectric material on and across the at least one second region of dielectric-material-capped graphene layer structure, the ohmic contacts and at least an adjacent portion of the substrate. Asad also teaches that this layer prevents short circuiting by overlapping the gate fingers (Asad page 458, second column).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the step of forming a second layer of dielectric material from Asad to the method of Wei in order to prevent short circuits.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asad as applied to claim 14 above, and further in view of Glass et al. (WO 2021008938 A1), hereinafter referred to as "Glass" .
In regards to claim 17, Asad discloses all of the limitations of claim 16. Asada does not explicitly point out the charge carrier density of the graphene layer structure.
Glass teaches a graphene layer structure has a charge carrier density of less than 1x1012 cm-2 (Glass page 15, lines 28-30). Glass also teaches that this advantageously has a lower carrier concentration along with increased charge carrier mobilities (Glass page 15, lines 30-32).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the charge carrier density be less than 5x1011 cm-2 as in Glass in order to get lower carrier concentration with increased charge carrier mobilities.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Asad in view of Glass as applied to claim 17 above, and further in view of Snure et al. ("Two-dimensional BN buffer for plasma enhanced atomic layer deposition of Al2O3 gate dielectrics on graphene field effect transistors"), hereinafter referred to as "Snure".
In regards to claim 19, Asad in view of Glass teaches all of the limitations of claim 17. Neither Asad nor Glass explicitly disclose the first dielectric being formed by ALD, nor the relationship of the charge carrier density with the substrate and the formation of the dielectric.
Snure teaches a first dielectric material on a graphene layer structure that is obtainable by ALD (Snure introduction, second paragraph). Snure also teaches that ALD is ideally suited for depositing high quality thin dielectrics for gates, tunneling barriers, etc. which is useful for high performance 2D devices (Snure introduction, second paragraph).
Snure further teaches a substrate selected so that the charge carrier density of the graphene layer structure formed by CVD is sufficient to counteract the doping resulting from the formation of the first dielectric material thereon (Snure results, paragraph 4; the BN layer on sapphire substrate helps mitigate the effects of unintentional doping).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first dielectric layer by ALD in order to get a high quality, thin dielectric layer, which is useful for high performance 2d devices, while selecting the substrate as in Snure to prevent unintentional doping from occurring during this process.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Asad in view of Glass in view of Snure as applied to claim 19 above, and further in view of Vangala et al. ("Wafer scale BN on sapphire substrates for improved graphene transport"), hereinafter referred to as "Vangala".
In regards to claim 20, Asad in view of Glass and Snure teach all the limitations of claim 19. Snure further teaches that the substrate is a sapphire substrate (Snure results first paragraph), but does not explicitly disclose that it is a c-plane sapphire substrate.
In a paper cited by Snure, Vangala teaches graphene grown by CVD on a very similar substrate, except they also specifically note that the substrate is c-plane sapphire (Vangala methods, first paragraph). Vangala also teaches that this allows for uniform, few layer BN to be grown, which is an important component to the substrate used in Snure.
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize c-plane sapphire as in Vangala in order to grow uniform, few layer BN, as already utilized by Snure.
Claims 18 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Asad as applied to claim 14 above, and further in view of Nayfeh et al. (“Impact of Plasma-Assisted Atomic-Layer-Deposited Gate Dielectric on Graphene Transistors”), hereinafter referred to as “Nayfeh”.
In regards to claim 18, Asad discloses all of the limitations of claim 1. Asad does not explicitly disclose by what method the first dielectric layer is formed.
Nayfeh teaches a first dielectric material on a graphene layer structure that is obtainable by ALD (Nayfeh section I). Nayfeh also teaches that this method is beneficial because it achieves a gate thickness of around 9 nanometers, as well as improvements in the drive current and peak transconductance (Nayfeh section I).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first dielectric layer by ALD in order to improve the gate thickness, drive current and peak transconductance.
In regards to claim 23, Asad in view of Nayfeh teaches all of the limitations of claim 18. Nayfeh further teaches that the ALD is performed at a temperature of less than 120°C (Nayfeh section II, second paragraph).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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